3 # This is the specification for the ia32 assembler Firm-operations
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
8 # this string marks the beginning of a comment in emit
9 $comment_string = "/*";
11 # the number of additional opcodes you want to register
12 #$additional_opcodes = 0;
14 # The node description is done as a perl hash initializer with the
15 # following structure:
20 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
21 # "irn_flags" => "R|N|I|S"
22 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
23 # "state" => "floats|pinned|mem_pinned|exc_pinned",
25 # { "type" => "type 1", "name" => "name 1" },
26 # { "type" => "type 2", "name" => "name 2" },
29 # "comment" => "any comment for constructor",
30 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
31 # "cmp_attr" => "c source code for comparing node attributes",
32 # "emit" => "emit code with templates",
33 # "attr" => "attitional attribute arguments for constructor"
34 # "init_attr" => "emit attribute initialization template"
35 # "rd_constructor" => "c source code which constructs an ir_node"
36 # "latency" => "latency of this operation (can be float)"
39 # ... # (all nodes you need to describe)
41 # ); # close the %nodes initializer
43 # op_flags: flags for the operation, OPTIONAL (default is "N")
44 # the op_flags correspond to the firm irop_flags:
47 # C irop_flag_commutative
48 # X irop_flag_cfopcode
49 # I irop_flag_ip_cfopcode
52 # H irop_flag_highlevel
53 # c irop_flag_constlike
56 # irn_flags: special node flags, OPTIONAL (default is 0)
57 # following irn_flags are supported:
60 # I ignore for register allocation
61 # S modifies stack pointer
63 # state: state of the operation, OPTIONAL (default is "floats")
65 # arity: arity of the operation, MUST NOT BE OMITTED
67 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
68 # are always the first 3 arguments and are always autmatically
70 # If this key is missing the following arguments will be created:
71 # for i = 1 .. arity: ir_node *op_i
74 # outs: if a node defines more than one output, the names of the projections
75 # nodes having outs having automatically the mode mode_T
76 # One can also annotate some flags for each out, additional to irn_flags.
77 # They are separated from name with a colon ':', and concatenated by pipe '|'
78 # Only I and S are available at the moment (same meaning as in irn_flags).
79 # example: [ "frame:I", "stack:I|S", "M" ]
81 # comment: OPTIONAL comment for the node constructor
83 # rd_constructor: for every operation there will be a
84 # new_rd_<arch>_<op-name> function with the arguments from above
85 # which creates the ir_node corresponding to the defined operation
86 # you can either put the complete source code of this function here
88 # This key is OPTIONAL. If omitted, the following constructor will
90 # if (!op_<arch>_<op-name>) assert(0);
94 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
97 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
99 # latency: the latency of the operation, default is 1
103 # 0 - no special type
104 # 1 - caller save (register must be saved by the caller of a function)
105 # 2 - callee save (register must be saved by the called function)
106 # 4 - ignore (do not assign this register)
107 # 8 - emitter can choose an arbitrary register of this class
108 # 16 - the register is a virtual one
109 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
112 { "name" => "eax", "type" => 1 },
113 { "name" => "edx", "type" => 1 },
114 { "name" => "ebx", "type" => 2 },
115 { "name" => "ecx", "type" => 1 },
116 { "name" => "esi", "type" => 2 },
117 { "name" => "edi", "type" => 2 },
118 # { "name" => "r11", "type" => 1 },
119 # { "name" => "r12", "type" => 1 },
120 # { "name" => "r13", "type" => 1 },
121 # { "name" => "r14", "type" => 1 },
122 # { "name" => "r15", "type" => 1 },
123 # { "name" => "r16", "type" => 1 },
124 # { "name" => "r17", "type" => 1 },
125 # { "name" => "r18", "type" => 1 },
126 # { "name" => "r19", "type" => 1 },
127 # { "name" => "r20", "type" => 1 },
128 # { "name" => "r21", "type" => 1 },
129 # { "name" => "r22", "type" => 1 },
130 # { "name" => "r23", "type" => 1 },
131 # { "name" => "r24", "type" => 1 },
132 # { "name" => "r25", "type" => 1 },
133 # { "name" => "r26", "type" => 1 },
134 # { "name" => "r27", "type" => 1 },
135 # { "name" => "r28", "type" => 1 },
136 # { "name" => "r29", "type" => 1 },
137 # { "name" => "r30", "type" => 1 },
138 # { "name" => "r31", "type" => 1 },
139 # { "name" => "r32", "type" => 1 },
140 { "name" => "ebp", "type" => 2 },
141 { "name" => "esp", "type" => 4 },
142 { "name" => "gp_NOREG", "type" => 2 | 4 | 16 }, # we need a dummy register for NoReg nodes
143 { "name" => "gp_UKNWN", "type" => 2 | 4 | 8 | 16}, # we need a dummy register for Unknown nodes
144 { "mode" => "mode_P" }
147 { "name" => "xmm0", "type" => 1 },
148 { "name" => "xmm1", "type" => 1 },
149 { "name" => "xmm2", "type" => 1 },
150 { "name" => "xmm3", "type" => 1 },
151 { "name" => "xmm4", "type" => 1 },
152 { "name" => "xmm5", "type" => 1 },
153 { "name" => "xmm6", "type" => 1 },
154 { "name" => "xmm7", "type" => 1 },
155 { "name" => "xmm_NOREG", "type" => 2 | 4 | 16 }, # we need a dummy register for NoReg nodes
156 { "name" => "xmm_UKNWN", "type" => 2 | 4 | 8 | 16}, # we need a dummy register for Unknown nodes
157 { "mode" => "mode_D" }
160 { "name" => "vf0", "type" => 1 | 16 },
161 { "name" => "vf1", "type" => 1 | 16 },
162 { "name" => "vf2", "type" => 1 | 16 },
163 { "name" => "vf3", "type" => 1 | 16 },
164 { "name" => "vf4", "type" => 1 | 16 },
165 { "name" => "vf5", "type" => 1 | 16 },
166 { "name" => "vf6", "type" => 1 | 16 },
167 { "name" => "vf7", "type" => 1 | 16 },
168 { "name" => "vfp_NOREG", "type" => 2 | 4 | 16 }, # we need a dummy register for NoReg nodes
169 { "name" => "vfp_UKNWN", "type" => 2 | 4 | 8 | 16}, # we need a dummy register for Unknown nodes
170 { "mode" => "mode_E" }
173 { "name" => "st0", "type" => 1 },
174 { "name" => "st1", "type" => 1 },
175 { "name" => "st2", "type" => 1 },
176 { "name" => "st3", "type" => 1 },
177 { "name" => "st4", "type" => 1 },
178 { "name" => "st5", "type" => 1 },
179 { "name" => "st6", "type" => 1 },
180 { "name" => "st7", "type" => 1 },
181 { "mode" => "mode_E" }
186 "ALU" => [ 1, "ALU1", "ALU2", "ALU3", "ALU4" ],
187 "MUL" => [ 1, "MUL1", "MUL2" ],
188 "SSE" => [ 1, "SSE1", "SSE2" ],
189 "FPU" => [ 1, "FPU1" ],
190 "MEM" => [ 1, "MEM1", "MEM2" ],
191 "BRANCH" => [ 1, "BRANCH1", "BRANCH2" ],
192 "DUMMY" => [ 1, "DUMMY1", "DUMMY2", "DUMMY3", "DUMMY4" ]
197 "bundels_per_cycle" => 2
200 #--------------------------------------------------#
203 # _ __ _____ __ _ _ __ ___ _ __ ___ #
204 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
205 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
206 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
209 #--------------------------------------------------#
216 #-----------------------------------------------------------------#
219 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
220 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
221 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
222 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
225 #-----------------------------------------------------------------#
227 # commutative operations
230 # All nodes supporting Addressmode have 5 INs:
231 # 1 - base r1 == NoReg in case of no AM or no base
232 # 2 - index r2 == NoReg in case of no AM or no index
233 # 3 - op1 r3 == always present
234 # 4 - op2 r4 == NoReg in case of immediate operation
235 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
239 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
240 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
241 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
242 "emit" => '. add %ia32_emit_binop /* Add(%A3, %A4) -> %D1 */',
243 "outs" => [ "res", "M" ],
244 "units" => [ "ALU", "MEM" ],
248 "comment" => "construct Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
249 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
250 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
251 "emit" => '. adc %ia32_emit_binop /* AddC(%A3, %A4) -> %D1 */',
252 "outs" => [ "res", "M" ],
253 "units" => [ "ALU", "MEM" ],
258 "comment" => "construct 64Bit Add: Add(a_l, a_h, b_l, b_h) = a_l + b_l; a_h + b_h + carry",
260 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
262 . mov %D1, %S1 /* mov a_l into assigned l_res register */
263 . mov %D2, %S2 /* mov a_h into assigned h_res register */
264 . add %D1, %S3 /* a_l + b_l */
265 . adc %D2, %S4 /* a_h + b_h + carry */
267 "outs" => [ "low_res", "high_res" ],
268 "units" => [ "ALU", "MEM" ],
274 "cmp_attr" => " return 1;\n",
275 "comment" => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
281 "cmp_attr" => " return 1;\n",
282 "comment" => "construct lowered Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
287 # we should not rematrialize this node. It produces 2 results and has
288 # very strict constrains
289 "comment" => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
290 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
291 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] },
292 "emit" => '. mul %ia32_emit_unop /* Mul(%A1, %A2) -> %D1 */',
293 "outs" => [ "EAX", "EDX", "M" ],
295 "units" => [ "MUL" ],
299 # we should not rematrialize this node. It produces 2 results and has
300 # very strict constrains
302 "cmp_attr" => " return 1;\n",
303 "comment" => "construct lowered MulS: MulS(a, b) = MulS(b, a) = a * b",
304 "outs" => [ "EAX", "EDX", "M" ],
310 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
311 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
312 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
313 "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */',
314 "outs" => [ "res", "M" ],
316 "units" => [ "MUL" ],
321 "cmp_attr" => " return 1;\n",
322 "comment" => "construct lowered Mul: Mul(a, b) = Mul(b, a) = a * b",
326 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
328 # we should not rematrialize this node. It produces 2 results and has
329 # very strict constrains
330 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
331 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
332 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] },
333 "emit" => '. imul %ia32_emit_unop /* Mulh(%A1, %A2) -> %D1 */',
334 "outs" => [ "EAX", "EDX", "M" ],
336 "units" => [ "MUL" ],
341 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
342 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
343 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
344 "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */',
345 "outs" => [ "res", "M" ],
346 "units" => [ "ALU" ],
351 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
352 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
353 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
354 "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */',
355 "outs" => [ "res", "M" ],
356 "units" => [ "ALU" ],
361 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
362 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
363 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
364 "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */',
365 "outs" => [ "res", "M" ],
366 "units" => [ "ALU" ],
371 "cmp_attr" => " return 1;\n",
372 "comment" => "construct lowered Eor: Eor(a, b) = Eor(b, a) = a EOR b",
378 "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
379 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
381 '2. cmp %S1, %S2 /* prepare Max (%S1 - %S2), (%A1, %A2) */
382 if (mode_is_signed(get_irn_mode(n))) {
383 4. cmovl %D1, %S2 /* %S1 is less %S2 */
386 4. cmovb %D1, %S2 /* %S1 is below %S2 */
390 "units" => [ "ALU" ],
395 "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
396 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
398 '2. cmp %S1, %S2 /* prepare Min (%S1 - %S2), (%A1, %A2) */
399 if (mode_is_signed(get_irn_mode(n))) {
400 2. cmovg %D1, %S2 /* %S1 is greater %S2 */
403 2. cmova %D1, %S2, %D1 /* %S1 is above %S2 */
407 "units" => [ "ALU" ],
410 # not commutative operations
414 "comment" => "construct Sub: Sub(a, b) = a - b",
415 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
416 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
417 "emit" => '. sub %ia32_emit_binop /* Sub(%A3, %A4) -> %D1 */',
418 "outs" => [ "res", "M" ],
419 "units" => [ "ALU" ],
423 "comment" => "construct Sub with Carry: SubC(a, b) = a - b - carry",
424 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
425 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3 !in_r4" ] },
426 "emit" => '. sbb %ia32_emit_binop /* SubC(%A3, %A4) -> %D1 */',
427 "outs" => [ "res", "M" ],
428 "units" => [ "ALU" ],
433 "comment" => "construct 64Bit Sub: Sub(a_l, a_h, b_l, b_h) = a_l - b_l; a_h - b_h - borrow",
435 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
437 . mov %D1, %S1 /* mov a_l into assigned l_res register */
438 . mov %D2, %S2 /* mov a_h into assigned h_res register */
439 . sub %D1, %S3 /* a_l - b_l */
440 . sbb %D2, %S4 /* a_h - b_h - borrow */
442 "outs" => [ "low_res", "high_res" ],
443 "units" => [ "ALU" ],
448 "cmp_attr" => " return 1;\n",
449 "comment" => "construct lowered Sub: Sub(a, b) = a - b",
454 "cmp_attr" => " return 1;\n",
455 "comment" => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
461 "state" => "exc_pinned",
462 "reg_req" => { "in" => [ "eax", "gp", "edx", "none" ], "out" => [ "eax", "edx" ] },
463 "attr" => "ia32_op_flavour_t dm_flav",
464 "init_attr" => " attr->data.op_flav = dm_flav;",
465 "cmp_attr" => " return attr_a->data.op_flav != attr_b->data.op_flav;\n",
467 ' if (mode_is_signed(get_ia32_res_mode(n))) {
468 4. idiv %S2 /* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
471 4. div %S2 /* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
474 "outs" => [ "div_res", "mod_res", "M" ],
476 "units" => [ "ALU" ],
481 "comment" => "construct Shl: Shl(a, b) = a << b",
482 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
483 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
484 "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */',
485 "outs" => [ "res", "M" ],
486 "units" => [ "ALU1", "SSE1" ],
490 "cmp_attr" => " return 1;\n",
491 "comment" => "construct lowered Shl: Shl(a, b) = a << b",
497 "comment" => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
498 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
499 # Out requirements is: different from all in
500 # This is because, out must be different from LowPart and ShiftCount.
501 # We could say "!ecx !in_r4" but it can occur, that all values live through
502 # this Shift and the only value dying is the ShiftCount. Then there would be a
503 # register missing, as result must not be ecx and all other registers are
504 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
505 # (and probably never will). So we create artificial interferences of the result
506 # with all inputs, so the spiller can always assure a free register.
507 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!in" ] },
510 if (get_ia32_immop_type(n) == ia32_ImmNone) {
511 if (get_ia32_op_type(n) == ia32_AddrModeD) {
512 4. shld %ia32_emit_am, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
515 4. shld %S3, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
519 if (get_ia32_op_type(n) == ia32_AddrModeD) {
520 4. shld %ia32_emit_am, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
523 4. shld %S3, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
527 "outs" => [ "res", "M" ],
529 "units" => [ "ALU1", "SSE1" ],
533 "cmp_attr" => " return 1;\n",
534 "comment" => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
540 "comment" => "construct Shr: Shr(a, b) = a >> b",
541 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
542 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
543 "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */',
544 "outs" => [ "res", "M" ],
545 "units" => [ "ALU1", "SSE1" ],
549 "cmp_attr" => " return 1;\n",
550 "comment" => "construct lowered Shr: Shr(a, b) = a << b",
556 "comment" => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
557 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
558 # Out requirements is: different from all in
559 # This is because, out must be different from LowPart and ShiftCount.
560 # We could say "!ecx !in_r4" but it can occur, that all values live through
561 # this Shift and the only value dying is the ShiftCount. Then there would be a
562 # register missing, as result must not be ecx and all other registers are
563 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
564 # (and probably never will). So we create artificial interferences of the result
565 # with all inputs, so the spiller can always assure a free register.
566 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!in" ] },
569 if (get_ia32_immop_type(n) == ia32_ImmNone) {
570 if (get_ia32_op_type(n) == ia32_AddrModeD) {
571 4. shrd %ia32_emit_am, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
574 4. shrd %S3, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
578 if (get_ia32_op_type(n) == ia32_AddrModeD) {
579 4. shrd %ia32_emit_am, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
582 4. shrd %S3, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
586 "outs" => [ "res", "M" ],
588 "units" => [ "ALU1", "SSE1" ],
592 "cmp_attr" => " return 1;\n",
593 "comment" => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
599 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
600 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
601 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
602 "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */',
603 "outs" => [ "res", "M" ],
604 "units" => [ "ALU1", "SSE1" ],
608 "cmp_attr" => " return 1;\n",
609 "comment" => "construct lowered Shrs: Shrs(a, b) = a << b",
615 "comment" => "construct RotR: RotR(a, b) = a ROTR b",
616 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
617 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
618 "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */',
619 "outs" => [ "res", "M" ],
620 "units" => [ "ALU1", "SSE1" ],
625 "comment" => "construct RotL: RotL(a, b) = a ROTL b",
626 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
627 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
628 "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */',
629 "outs" => [ "res", "M" ],
630 "units" => [ "ALU1", "SSE1" ],
637 "comment" => "construct Minus: Minus(a) = -a",
638 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
639 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
640 "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */',
641 "outs" => [ "res", "M" ],
642 "units" => [ "ALU" ],
647 "comment" => "construct 64Bit Minus: Minus(a_l, a_h, 0) = 0 - a_l; 0 - a_h - borrow",
649 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
651 . mov %D1, %S1 /* l_res */
652 . mov %D2, %S1 /* h_res */
653 . sub %D1, %S2 /* 0 - a_l -> low_res */
654 . sbb %D2, %S3 /* 0 - a_h - borrow -> high_res */
656 "outs" => [ "low_res", "high_res" ],
657 "units" => [ "ALU" ],
662 "cmp_attr" => " return 1;\n",
663 "comment" => "construct lowered Minus: Minus(a) = -a",
669 "comment" => "construct Increment: Inc(a) = a++",
670 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
671 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
672 "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */',
673 "outs" => [ "res", "M" ],
674 "units" => [ "ALU" ],
679 "comment" => "construct Decrement: Dec(a) = a--",
680 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
681 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
682 "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */',
683 "outs" => [ "res", "M" ],
684 "units" => [ "ALU" ],
689 "comment" => "construct Not: Not(a) = !a",
690 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
691 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
692 "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */',
693 "outs" => [ "res", "M" ],
694 "units" => [ "ALU" ],
700 "op_flags" => "L|X|Y",
701 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
702 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
703 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
704 "outs" => [ "false", "true" ],
706 "units" => [ "BRANCH" ],
710 "op_flags" => "L|X|Y",
711 "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
712 "reg_req" => { "in" => [ "gp", "gp" ] },
713 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
714 "outs" => [ "false", "true" ],
716 "units" => [ "BRANCH" ],
720 "op_flags" => "L|X|Y",
721 "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
722 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
723 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
724 "outs" => [ "false", "true" ],
725 "units" => [ "BRANCH" ],
729 "op_flags" => "L|X|Y",
730 "comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
731 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
732 "reg_req" => { "in" => [ "gp", "gp" ] },
733 "units" => [ "BRANCH" ],
737 "op_flags" => "L|X|Y",
738 "comment" => "construct switch",
739 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
740 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
742 "units" => [ "BRANCH" ],
748 "comment" => "represents an integer constant",
749 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
750 "reg_req" => { "out" => [ "gp" ] },
751 "units" => [ "ALU" ],
755 # we should not rematrialize this node. It produces 2 results and has
756 # very strict constrains
757 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
758 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
759 "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */',
760 "outs" => [ "EAX", "EDX" ],
761 "units" => [ "ALU" ],
768 "state" => "exc_pinned",
769 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
770 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
771 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
774 ' if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) {
775 4. mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
778 4. mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
781 "outs" => [ "res", "M" ],
782 "units" => [ "MEM" ],
787 "cmp_attr" => " return 1;\n",
788 "comment" => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg",
789 "outs" => [ "res", "M" ],
795 "cmp_attr" => " return 1;\n",
796 "state" => "exc_pinned",
797 "comment" => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val",
804 "state" => "exc_pinned",
805 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
806 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
807 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
808 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
811 "units" => [ "MEM" ],
816 "state" => "exc_pinned",
817 "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
818 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
819 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
820 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
823 "units" => [ "MEM" ],
828 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
829 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
830 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
831 "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */',
833 "units" => [ "ALU" ],
837 "comment" => "push on the stack",
838 "reg_req" => { "in" => [ "gp", "gp", "gp", "esp", "none" ], "out" => [ "esp" ] },
839 "emit" => '. push %ia32_emit_unop /* PUSH(%A1) */',
840 "outs" => [ "stack:I|S", "M" ],
842 "units" => [ "MEM" ],
846 # We don't set class modify stack here (but we will do this on proj 1)
847 "comment" => "pop a gp register from the stack",
848 "reg_req" => { "in" => [ "gp", "gp", "esp", "none" ], "out" => [ "gp", "esp" ] },
849 "emit" => '. pop %ia32_emit_unop /* POP(%A1) */',
850 "outs" => [ "res", "stack:I|S", "M" ],
852 "units" => [ "MEM" ],
856 "comment" => "create stack frame",
857 "reg_req" => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] },
858 "emit" => '. enter /* Enter */',
859 "outs" => [ "frame:I", "stack:I|S", "M" ],
861 "units" => [ "MEM" ],
865 "comment" => "destroy stack frame",
866 "reg_req" => { "in" => [ "esp", "ebp" ], "out" => [ "ebp", "esp" ] },
867 "emit" => '. leave /* Leave */',
868 "outs" => [ "frame:I", "stack:I|S", "M" ],
870 "units" => [ "MEM" ],
875 "comment" => "allocate space on stack",
876 "reg_req" => { "in" => [ "esp", "gp" ], "out" => [ "esp", "none" ] },
877 "outs" => [ "stack:S", "M" ],
878 "units" => [ "ALU" ],
883 "comment" => "free space on stack",
884 "reg_req" => { "in" => [ "esp", "gp" ], "out" => [ "esp", "none" ] },
885 "outs" => [ "stack:S", "M" ],
886 "units" => [ "ALU" ],
891 "comment" => "get the TLS base address",
892 "reg_req" => { "out" => [ "gp" ] },
893 "units" => [ "MEM" ],
898 #-----------------------------------------------------------------------------#
899 # _____ _____ ______ __ _ _ _ #
900 # / ____/ ____| ____| / _| | | | | | #
901 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
902 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
903 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
904 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
905 #-----------------------------------------------------------------------------#
907 # commutative operations
911 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
912 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
913 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
914 "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */',
915 "outs" => [ "res", "M" ],
917 "units" => [ "SSE" ],
922 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
923 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
924 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
925 "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */',
926 "outs" => [ "res", "M" ],
928 "units" => [ "SSE" ],
933 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
934 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
935 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
936 "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */',
937 "outs" => [ "res", "M" ],
939 "units" => [ "SSE" ],
944 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
945 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
946 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
947 "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */',
948 "outs" => [ "res", "M" ],
950 "units" => [ "SSE" ],
955 "comment" => "construct SSE And: And(a, b) = a AND b",
956 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
957 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
958 "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */',
959 "outs" => [ "res", "M" ],
961 "units" => [ "SSE" ],
966 "comment" => "construct SSE Or: Or(a, b) = a OR b",
967 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
968 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
969 "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */',
970 "outs" => [ "res", "M" ],
971 "units" => [ "SSE" ],
976 "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
977 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
978 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
979 "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */',
980 "outs" => [ "res", "M" ],
982 "units" => [ "SSE" ],
985 # not commutative operations
989 "comment" => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
990 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
991 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
992 "emit" => '. andnp%M %ia32_emit_binop /* SSE AndNot(%A3, %A4) -> %D1 */',
993 "outs" => [ "res", "M" ],
995 "units" => [ "SSE" ],
1000 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
1001 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1002 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
1003 "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */',
1004 "outs" => [ "res", "M" ],
1006 "units" => [ "SSE" ],
1011 "comment" => "construct SSE Div: Div(a, b) = a / b",
1012 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1013 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
1014 "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */',
1015 "outs" => [ "res", "M" ],
1017 "units" => [ "SSE" ],
1024 "comment" => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
1025 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
1026 "outs" => [ "res", "M" ],
1028 "units" => [ "SSE" ],
1032 "op_flags" => "L|X|Y",
1033 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
1034 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1035 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
1036 "outs" => [ "false", "true" ],
1038 "units" => [ "SSE" ],
1044 "comment" => "represents a SSE constant",
1045 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1046 "reg_req" => { "out" => [ "xmm" ] },
1047 "emit" => '. movs%M %D1, %C /* Load fConst into register */',
1049 "units" => [ "SSE" ],
1055 "op_flags" => "L|F",
1056 "state" => "exc_pinned",
1057 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
1058 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1059 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm" ] },
1060 "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */',
1061 "outs" => [ "res", "M" ],
1063 "units" => [ "SSE" ],
1067 "op_flags" => "L|F",
1068 "state" => "exc_pinned",
1069 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
1070 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1071 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
1072 "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */',
1075 "units" => [ "MEM" ],
1079 "op_flags" => "L|F",
1080 "state" => "exc_pinned",
1081 "comment" => "construct Store without index: Store(ptr, val, mem) = ST ptr,val",
1082 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1083 "reg_req" => { "in" => [ "gp", "xmm", "none" ] },
1084 "emit" => '. movs%M %ia32_emit_am, %S2 /* store XMM0 onto stack */',
1087 "units" => [ "MEM" ],
1091 "op_flags" => "L|F",
1092 "comment" => "construct: transfer a value from x87 FPU into a SSE register",
1093 "cmp_attr" => " return 1;\n",
1098 "op_flags" => "L|F",
1099 "comment" => "construct: transfer a value from SSE register to x87 FPU",
1100 "cmp_attr" => " return 1;\n",
1105 "op_flags" => "L|F",
1107 "state" => "exc_pinned",
1108 "comment" => "store ST0 onto stack",
1109 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1110 "reg_req" => { "in" => [ "gp", "none" ] },
1111 "emit" => '. fstp %ia32_emit_am /* store ST0 onto stack */',
1114 "units" => [ "MEM" ],
1118 "op_flags" => "L|F",
1120 "state" => "exc_pinned",
1121 "comment" => "load ST0 from stack",
1122 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1123 "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "vf0", "none" ] },
1124 "emit" => '. fld %ia32_emit_am /* load ST0 from stack */',
1125 "outs" => [ "res", "M" ],
1127 "units" => [ "MEM" ],
1133 "op_flags" => "F|H",
1134 "state" => "pinned",
1135 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
1136 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "edi", "esi", "ecx", "none" ] },
1137 "outs" => [ "DST", "SRC", "CNT", "M" ],
1138 "units" => [ "MEM" ],
1142 "op_flags" => "F|H",
1143 "state" => "pinned",
1144 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
1145 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1146 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "edi", "esi", "none" ] },
1147 "outs" => [ "DST", "SRC", "M" ],
1148 "units" => [ "MEM" ],
1154 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
1155 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1156 "comment" => "construct Conv Int -> Int",
1157 "outs" => [ "res", "M" ],
1158 "units" => [ "ALU" ],
1162 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
1163 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1164 "comment" => "construct Conv Int -> Int",
1165 "outs" => [ "res", "M" ],
1166 "units" => [ "ALU" ],
1170 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
1171 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1172 "comment" => "construct Conv Int -> Floating Point",
1173 "outs" => [ "res", "M" ],
1175 "units" => [ "SSE" ],
1179 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
1180 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1181 "comment" => "construct Conv Floating Point -> Int",
1182 "outs" => [ "res", "M" ],
1184 "units" => [ "SSE" ],
1188 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
1189 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1190 "comment" => "construct Conv Floating Point -> Floating Point",
1191 "outs" => [ "res", "M" ],
1193 "units" => [ "SSE" ],
1198 "comment" => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
1199 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "in_r4" ] },
1201 "units" => [ "ALU" ],
1206 "comment" => "check if Psi condition tree evaluates to true and move result accordingly",
1207 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r3" ] },
1209 "units" => [ "ALU" ],
1214 "comment" => "construct Conditional Move: SSE Compare + int CMov ",
1215 "reg_req" => { "in" => [ "xmm", "xmm", "gp", "gp" ], "out" => [ "in_r4" ] },
1217 "units" => [ "SSE" ],
1222 "comment" => "construct Conditional Move: x87 Compare + int CMov",
1223 "reg_req" => { "in" => [ "vfp", "vfp", "gp", "gp" ], "out" => [ "in_r4" ] },
1225 "units" => [ "FPU" ],
1230 "comment" => "construct Set: Set(sel) == sel ? 1 : 0",
1231 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1232 "outs" => [ "res", "M" ],
1234 "units" => [ "ALU" ],
1239 "comment" => "check if Psi condition tree evaluates to true and set result accordingly",
1240 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax ebx ecx edx" ] },
1242 "units" => [ "ALU" ],
1247 "comment" => "construct Set: SSE Compare + int Set",
1248 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1249 "outs" => [ "res", "M" ],
1251 "units" => [ "SSE" ],
1256 "comment" => "construct Set: x87 Compare + int Set",
1257 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1258 "outs" => [ "res", "M" ],
1260 "units" => [ "FPU" ],
1265 "comment" => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
1266 "reg_req" => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] },
1268 "units" => [ "FPU" ],
1271 #----------------------------------------------------------#
1273 # (_) | | | | / _| | | | #
1274 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
1275 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
1276 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
1277 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
1279 # _ __ ___ __| | ___ ___ #
1280 # | '_ \ / _ \ / _` |/ _ \/ __| #
1281 # | | | | (_) | (_| | __/\__ \ #
1282 # |_| |_|\___/ \__,_|\___||___/ #
1283 #----------------------------------------------------------#
1287 "comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
1288 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1289 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1290 "outs" => [ "res", "M" ],
1292 "units" => [ "FPU" ],
1297 "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1298 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1299 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1300 "outs" => [ "res", "M" ],
1302 "units" => [ "FPU" ],
1307 "cmp_attr" => " return 1;\n",
1308 "comment" => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1314 "comment" => "virtual fp Sub: Sub(a, b) = a - b",
1315 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1316 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1317 "outs" => [ "res", "M" ],
1319 "units" => [ "FPU" ],
1323 "cmp_attr" => " return 1;\n",
1324 "comment" => "lowered virtual fp Sub: Sub(a, b) = a - b",
1329 "comment" => "virtual fp Div: Div(a, b) = a / b",
1330 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1331 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1332 "outs" => [ "res", "M" ],
1334 "units" => [ "FPU" ],
1338 "cmp_attr" => " return 1;\n",
1339 "comment" => "lowered virtual fp Div: Div(a, b) = a / b",
1344 "comment" => "virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1345 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1346 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1347 "outs" => [ "res", "M" ],
1349 "units" => [ "FPU" ],
1353 "cmp_attr" => " return 1;\n",
1354 "comment" => "lowered virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1360 "comment" => "virtual fp Abs: Abs(a) = |a|",
1361 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1363 "units" => [ "FPU" ],
1368 "comment" => "virtual fp Chs: Chs(a) = -a",
1369 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1371 "units" => [ "FPU" ],
1376 "comment" => "virtual fp Sin: Sin(a) = sin(a)",
1377 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1379 "units" => [ "FPU" ],
1384 "comment" => "virtual fp Cos: Cos(a) = cos(a)",
1385 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1387 "units" => [ "FPU" ],
1392 "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
1393 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1395 "units" => [ "FPU" ],
1398 # virtual Load and Store
1401 "op_flags" => "L|F",
1402 "state" => "exc_pinned",
1403 "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
1404 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1405 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1406 "outs" => [ "res", "M" ],
1408 "units" => [ "FPU" ],
1412 "op_flags" => "L|F",
1413 "state" => "exc_pinned",
1414 "comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
1415 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1416 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1419 "units" => [ "FPU" ],
1425 "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1426 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1427 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1428 "outs" => [ "res", "M" ],
1430 "units" => [ "FPU" ],
1434 "cmp_attr" => " return 1;\n",
1435 "comment" => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1436 "outs" => [ "res", "M" ],
1441 "comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1442 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1443 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1446 "units" => [ "FPU" ],
1450 "cmp_attr" => " return 1;\n",
1451 "comment" => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1461 "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg",
1462 "reg_req" => { "out" => [ "vfp" ] },
1464 "units" => [ "FPU" ],
1469 "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg",
1470 "reg_req" => { "out" => [ "vfp" ] },
1472 "units" => [ "FPU" ],
1477 "comment" => "virtual fp Load pi: Ld pi -> reg",
1478 "reg_req" => { "out" => [ "vfp" ] },
1480 "units" => [ "FPU" ],
1485 "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg",
1486 "reg_req" => { "out" => [ "vfp" ] },
1488 "units" => [ "FPU" ],
1493 "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg",
1494 "reg_req" => { "out" => [ "vfp" ] },
1496 "units" => [ "FPU" ],
1501 "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg",
1502 "reg_req" => { "out" => [ "vfp" ] },
1504 "units" => [ "FPU" ],
1509 "comment" => "virtual fp Load ld e: Ld ld e -> reg",
1510 "reg_req" => { "out" => [ "vfp" ] },
1512 "units" => [ "FPU" ],
1518 "init_attr" => " set_ia32_ls_mode(res, mode);",
1519 "comment" => "represents a virtual floating point constant",
1520 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1521 "reg_req" => { "out" => [ "vfp" ] },
1523 "units" => [ "FPU" ],
1529 "op_flags" => "L|X|Y",
1530 "comment" => "represents a virtual floating point compare",
1531 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1532 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] },
1533 "outs" => [ "false", "true", "temp_reg_eax" ],
1535 "units" => [ "FPU" ],
1538 #------------------------------------------------------------------------#
1539 # ___ _____ __ _ _ _ #
1540 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1541 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1542 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1543 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1544 #------------------------------------------------------------------------#
1548 "rd_constructor" => "NONE",
1549 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1551 "emit" => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A3, %A4) -> %D1 */',
1556 "rd_constructor" => "NONE",
1557 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1559 "emit" => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A3, %A4) -> %D1 */',
1564 "rd_constructor" => "NONE",
1565 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1567 "emit" => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A3, %A4) -> %D1 */',
1572 "rd_constructor" => "NONE",
1573 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1575 "emit" => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A3, %A4) -> %D1 */',,
1580 "rd_constructor" => "NONE",
1581 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1583 "emit" => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A3, %A4) -> %D1 */',
1588 "rd_constructor" => "NONE",
1589 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1591 "emit" => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A3, %A4) -> %D1 */',
1596 "rd_constructor" => "NONE",
1598 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1600 "emit" => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A3, %A4) -> %D1 */',
1605 "rd_constructor" => "NONE",
1607 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1609 "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A3, %A4) -> %D1 */',
1614 "rd_constructor" => "NONE",
1615 "comment" => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1617 "emit" => '. fprem1 /* x87 fprem(%A3, %A4) -> %D1 */',
1620 # this node is just here, to keep the simulator running
1621 # we can omit this when a fprem simulation function exists
1624 "rd_constructor" => "NONE",
1625 "comment" => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1627 "emit" => '. fprem1 /* x87 fprem(%A3, %A4) -> %D1 WITH POP */',
1632 "rd_constructor" => "NONE",
1633 "comment" => "x87 fp Div: Div(a, b) = a / b",
1635 "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A3, %A4) -> %D1 */',
1640 "rd_constructor" => "NONE",
1641 "comment" => "x87 fp Div: Div(a, b) = a / b",
1643 "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A3, %A4) -> %D1 */',
1648 "rd_constructor" => "NONE",
1649 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1651 "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A3, %A4) -> %D1 */',
1656 "rd_constructor" => "NONE",
1657 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1659 "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A3, %A4) -> %D1 */',
1664 "rd_constructor" => "NONE",
1665 "comment" => "x87 fp Abs: Abs(a) = |a|",
1667 "emit" => '. fabs /* x87 fabs(%A1) -> %D1 */',
1672 "rd_constructor" => "NONE",
1673 "comment" => "x87 fp Chs: Chs(a) = -a",
1675 "emit" => '. fchs /* x87 fchs(%A1) -> %D1 */',
1680 "rd_constructor" => "NONE",
1681 "comment" => "x87 fp Sin: Sin(a) = sin(a)",
1683 "emit" => '. fsin /* x87 sin(%A1) -> %D1 */',
1688 "rd_constructor" => "NONE",
1689 "comment" => "x87 fp Cos: Cos(a) = cos(a)",
1691 "emit" => '. fcos /* x87 cos(%A1) -> %D1 */',
1696 "rd_constructor" => "NONE",
1697 "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1699 "emit" => '. fsqrt $ /* x87 sqrt(%A1) -> %D1 */',
1702 # x87 Load and Store
1705 "rd_constructor" => "NONE",
1706 "op_flags" => "R|L|F",
1707 "state" => "exc_pinned",
1708 "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1710 "emit" => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */',
1714 "rd_constructor" => "NONE",
1715 "op_flags" => "R|L|F",
1716 "state" => "exc_pinned",
1717 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1719 "emit" => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */',
1723 "rd_constructor" => "NONE",
1724 "op_flags" => "R|L|F",
1725 "state" => "exc_pinned",
1726 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1728 "emit" => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */',
1735 "rd_constructor" => "NONE",
1736 "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1738 "emit" => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */',
1743 "rd_constructor" => "NONE",
1744 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1746 "emit" => '. fist %ia32_emit_am /* integer Store(%A3) -> (%A1) */',
1751 "rd_constructor" => "NONE",
1752 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1754 "emit" => '. fistp %ia32_emit_am /* integer Store(%A3) -> (%A1) and pop */',
1760 "op_flags" => "R|c",
1762 "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
1763 "reg_req" => { "out" => [ "vfp" ] },
1764 "emit" => '. fldz /* x87 0.0 -> %D1 */',
1768 "op_flags" => "R|c",
1770 "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
1771 "reg_req" => { "out" => [ "vfp" ] },
1772 "emit" => '. fld1 /* x87 1.0 -> %D1 */',
1776 "op_flags" => "R|c",
1778 "comment" => "x87 fp Load pi: Ld pi -> reg",
1779 "reg_req" => { "out" => [ "vfp" ] },
1780 "emit" => '. fldpi /* x87 pi -> %D1 */',
1784 "op_flags" => "R|c",
1786 "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
1787 "reg_req" => { "out" => [ "vfp" ] },
1788 "emit" => '. fldln2 /* x87 ln(2) -> %D1 */',
1792 "op_flags" => "R|c",
1794 "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
1795 "reg_req" => { "out" => [ "vfp" ] },
1796 "emit" => '. fldlg2 /* x87 log(2) -> %D1 */',
1800 "op_flags" => "R|c",
1802 "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
1803 "reg_req" => { "out" => [ "vfp" ] },
1804 "emit" => '. fldll2t /* x87 ld(10) -> %D1 */',
1808 "op_flags" => "R|c",
1810 "comment" => "x87 fp Load ld e: Ld ld e -> reg",
1811 "reg_req" => { "out" => [ "vfp" ] },
1812 "emit" => '. fldl2e /* x87 ld(e) -> %D1 */',
1816 "op_flags" => "R|c",
1818 "rd_constructor" => "NONE",
1819 "comment" => "represents a x87 constant",
1820 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1821 "reg_req" => { "out" => [ "vfp" ] },
1822 "emit" => '. fld %ia32_emit_adr /* Load fConst into register -> %D1 */',
1826 # Note that it is NEVER allowed to do CSE on these nodes
1827 # Moreover, note the virtual register requierements!
1830 "op_flags" => "R|K",
1831 "comment" => "x87 stack exchange",
1833 "cmp_attr" => " return 1;\n",
1834 "emit" => '. fxch %X1 /* x87 swap %X1, %X3 */',
1838 "op_flags" => "R|K",
1839 "comment" => "x87 stack push",
1841 "cmp_attr" => " return 1;\n",
1842 "emit" => '. fld %X1 /* x87 push %X1 */',
1847 "comment" => "x87 stack push",
1848 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1849 "cmp_attr" => " return 1;\n",
1850 "emit" => '. fld %X1 /* x87 push %X1 */',
1854 "op_flags" => "R|K",
1855 "comment" => "x87 stack pop",
1857 "cmp_attr" => " return 1;\n",
1858 "emit" => '. fstp %X1 /* x87 pop %X1 */',
1864 "op_flags" => "L|X|Y",
1865 "comment" => "floating point compare",
1866 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1871 "op_flags" => "L|X|Y",
1872 "comment" => "floating point compare and pop",
1873 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1878 "op_flags" => "L|X|Y",
1879 "comment" => "floating point compare and pop twice",
1880 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1885 "op_flags" => "L|X|Y",
1886 "comment" => "floating point compare reverse",
1887 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1892 "op_flags" => "L|X|Y",
1893 "comment" => "floating point compare reverse and pop",
1894 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1899 "op_flags" => "L|X|Y",
1900 "comment" => "floating point compare reverse and pop twice",
1901 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",