3 # This is the specification for the ia32 assembler Firm-operations
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
8 # this strings mark the beginning and the end of a comment in emit
9 $comment_string = "/*";
10 $comment_string_end = "*/";
12 # the number of additional opcodes you want to register
13 #$additional_opcodes = 0;
15 # The node description is done as a perl hash initializer with the
16 # following structure:
21 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
22 # "irn_flags" => "R|N|I|S"
23 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
24 # "state" => "floats|pinned|mem_pinned|exc_pinned",
26 # { "type" => "type 1", "name" => "name 1" },
27 # { "type" => "type 2", "name" => "name 2" },
30 # "comment" => "any comment for constructor",
31 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
32 # "cmp_attr" => "c source code for comparing node attributes",
33 # "emit" => "emit code with templates",
34 # "attr" => "attitional attribute arguments for constructor"
35 # "init_attr" => "emit attribute initialization template"
36 # "rd_constructor" => "c source code which constructs an ir_node"
37 # "latency" => "latency of this operation (can be float)"
40 # ... # (all nodes you need to describe)
42 # ); # close the %nodes initializer
44 # op_flags: flags for the operation, OPTIONAL (default is "N")
45 # the op_flags correspond to the firm irop_flags:
48 # C irop_flag_commutative
49 # X irop_flag_cfopcode
50 # I irop_flag_ip_cfopcode
53 # H irop_flag_highlevel
54 # c irop_flag_constlike
57 # irn_flags: special node flags, OPTIONAL (default is 0)
58 # following irn_flags are supported:
61 # I ignore for register allocation
62 # S modifies stack pointer
64 # state: state of the operation, OPTIONAL (default is "floats")
66 # arity: arity of the operation, MUST NOT BE OMITTED
68 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
69 # are always the first 3 arguments and are always autmatically
71 # If this key is missing the following arguments will be created:
72 # for i = 1 .. arity: ir_node *op_i
75 # outs: if a node defines more than one output, the names of the projections
76 # nodes having outs having automatically the mode mode_T
77 # One can also annotate some flags for each out, additional to irn_flags.
78 # They are separated from name with a colon ':', and concatenated by pipe '|'
79 # Only I and S are available at the moment (same meaning as in irn_flags).
80 # example: [ "frame:I", "stack:I|S", "M" ]
82 # comment: OPTIONAL comment for the node constructor
84 # rd_constructor: for every operation there will be a
85 # new_rd_<arch>_<op-name> function with the arguments from above
86 # which creates the ir_node corresponding to the defined operation
87 # you can either put the complete source code of this function here
89 # This key is OPTIONAL. If omitted, the following constructor will
91 # if (!op_<arch>_<op-name>) assert(0);
95 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
98 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
100 # latency: the latency of the operation, default is 1
104 # 0 - no special type
105 # 1 - caller save (register must be saved by the caller of a function)
106 # 2 - callee save (register must be saved by the called function)
107 # 4 - ignore (do not assign this register)
108 # 8 - emitter can choose an arbitrary register of this class
109 # 16 - the register is a virtual one
110 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
113 { "name" => "eax", "type" => 1 },
114 { "name" => "edx", "type" => 1 },
115 { "name" => "ebx", "type" => 2 },
116 { "name" => "ecx", "type" => 1 },
117 { "name" => "esi", "type" => 2 },
118 { "name" => "edi", "type" => 2 },
119 # { "name" => "r11", "type" => 1 },
120 # { "name" => "r12", "type" => 1 },
121 # { "name" => "r13", "type" => 1 },
122 # { "name" => "r14", "type" => 1 },
123 # { "name" => "r15", "type" => 1 },
124 # { "name" => "r16", "type" => 1 },
125 # { "name" => "r17", "type" => 1 },
126 # { "name" => "r18", "type" => 1 },
127 # { "name" => "r19", "type" => 1 },
128 # { "name" => "r20", "type" => 1 },
129 # { "name" => "r21", "type" => 1 },
130 # { "name" => "r22", "type" => 1 },
131 # { "name" => "r23", "type" => 1 },
132 # { "name" => "r24", "type" => 1 },
133 # { "name" => "r25", "type" => 1 },
134 # { "name" => "r26", "type" => 1 },
135 # { "name" => "r27", "type" => 1 },
136 # { "name" => "r28", "type" => 1 },
137 # { "name" => "r29", "type" => 1 },
138 # { "name" => "r30", "type" => 1 },
139 # { "name" => "r31", "type" => 1 },
140 # { "name" => "r32", "type" => 1 },
141 { "name" => "ebp", "type" => 2 },
142 { "name" => "esp", "type" => 4 },
143 { "name" => "gp_NOREG", "type" => 2 | 4 | 16 }, # we need a dummy register for NoReg nodes
144 { "name" => "gp_UKNWN", "type" => 2 | 4 | 8 | 16}, # we need a dummy register for Unknown nodes
145 { "mode" => "mode_P" }
148 { "name" => "xmm0", "type" => 1 },
149 { "name" => "xmm1", "type" => 1 },
150 { "name" => "xmm2", "type" => 1 },
151 { "name" => "xmm3", "type" => 1 },
152 { "name" => "xmm4", "type" => 1 },
153 { "name" => "xmm5", "type" => 1 },
154 { "name" => "xmm6", "type" => 1 },
155 { "name" => "xmm7", "type" => 1 },
156 { "name" => "xmm_NOREG", "type" => 2 | 4 | 16 }, # we need a dummy register for NoReg nodes
157 { "name" => "xmm_UKNWN", "type" => 2 | 4 | 8 | 16}, # we need a dummy register for Unknown nodes
158 { "mode" => "mode_D" }
161 { "name" => "vf0", "type" => 1 | 16 },
162 { "name" => "vf1", "type" => 1 | 16 },
163 { "name" => "vf2", "type" => 1 | 16 },
164 { "name" => "vf3", "type" => 1 | 16 },
165 { "name" => "vf4", "type" => 1 | 16 },
166 { "name" => "vf5", "type" => 1 | 16 },
167 { "name" => "vf6", "type" => 1 | 16 },
168 { "name" => "vf7", "type" => 1 | 16 },
169 { "name" => "vfp_NOREG", "type" => 2 | 4 | 16 }, # we need a dummy register for NoReg nodes
170 { "name" => "vfp_UKNWN", "type" => 2 | 4 | 8 | 16}, # we need a dummy register for Unknown nodes
171 { "mode" => "mode_E" }
174 { "name" => "st0", "type" => 1 },
175 { "name" => "st1", "type" => 1 },
176 { "name" => "st2", "type" => 1 },
177 { "name" => "st3", "type" => 1 },
178 { "name" => "st4", "type" => 1 },
179 { "name" => "st5", "type" => 1 },
180 { "name" => "st6", "type" => 1 },
181 { "name" => "st7", "type" => 1 },
182 { "mode" => "mode_E" }
187 "ALU" => [ 1, "ALU1", "ALU2", "ALU3", "ALU4" ],
188 "MUL" => [ 1, "MUL1", "MUL2" ],
189 "SSE" => [ 1, "SSE1", "SSE2" ],
190 "FPU" => [ 1, "FPU1" ],
191 "MEM" => [ 1, "MEM1", "MEM2" ],
192 "BRANCH" => [ 1, "BRANCH1", "BRANCH2" ],
193 "DUMMY" => [ 1, "DUMMY1", "DUMMY2", "DUMMY3", "DUMMY4" ]
198 "bundels_per_cycle" => 2
201 #--------------------------------------------------#
204 # _ __ _____ __ _ _ __ ___ _ __ ___ #
205 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
206 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
207 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
210 #--------------------------------------------------#
212 $default_cmp_attr = "return ia32_compare_immop_attr(attr_a, attr_b);";
219 #-----------------------------------------------------------------#
222 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
223 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
224 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
225 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
228 #-----------------------------------------------------------------#
230 # commutative operations
233 # All nodes supporting Addressmode have 5 INs:
234 # 1 - base r1 == NoReg in case of no AM or no base
235 # 2 - index r2 == NoReg in case of no AM or no index
236 # 3 - op1 r3 == always present
237 # 4 - op2 r4 == NoReg in case of immediate operation
238 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
242 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
243 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
244 "emit" => '. add %ia32_emit_binop /* Add(%A3, %A4) -> %D1 */',
245 "units" => [ "ALU", "MEM" ],
249 "comment" => "construct Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
250 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
251 "emit" => '. adc %ia32_emit_binop /* AddC(%A3, %A4) -> %D1 */',
252 "units" => [ "ALU", "MEM" ],
257 "comment" => "construct 64Bit Add: Add(a_l, a_h, b_l, b_h) = a_l + b_l; a_h + b_h + carry",
259 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
261 . mov %D1, %S1 /* mov a_l into assigned l_res register */
262 . mov %D2, %S2 /* mov a_h into assigned h_res register */
263 . add %D1, %S3 /* a_l + b_l */
264 . adc %D2, %S4 /* a_h + b_h + carry */
266 "outs" => [ "low_res", "high_res" ],
267 "units" => [ "ALU", "MEM" ],
273 "cmp_attr" => "return 1;",
274 "comment" => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
280 "cmp_attr" => "return 1;",
281 "comment" => "construct lowered Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
286 # we should not rematrialize this node. It produces 2 results and has
287 # very strict constrains
288 "comment" => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
289 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] },
290 "emit" => '. mul %ia32_emit_unop /* Mul(%A1, %A2) -> %D1 */',
291 "outs" => [ "EAX", "EDX", "M" ],
293 "units" => [ "MUL" ],
297 # we should not rematrialize this node. It produces 2 results and has
298 # very strict constrains
300 "cmp_attr" => "return 1;",
301 "comment" => "construct lowered MulS: MulS(a, b) = MulS(b, a) = a * b",
302 "outs" => [ "EAX", "EDX", "M" ],
308 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
309 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
310 "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */',
312 "units" => [ "MUL" ],
317 "cmp_attr" => "return 1;",
318 "comment" => "construct lowered Mul: Mul(a, b) = Mul(b, a) = a * b",
322 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
324 # we should not rematrialize this node. It produces 2 results and has
325 # very strict constrains
326 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
327 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] },
328 "emit" => '. imul %ia32_emit_unop /* Mulh(%A1, %A2) -> %D1 */',
329 "outs" => [ "EAX", "EDX", "M" ],
331 "units" => [ "MUL" ],
336 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
337 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
338 "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */',
339 "units" => [ "ALU" ],
344 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
345 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
346 "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */',
347 "units" => [ "ALU" ],
352 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
353 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
354 "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */',
355 "units" => [ "ALU" ],
360 "cmp_attr" => "return 1;",
361 "comment" => "construct lowered Eor: Eor(a, b) = Eor(b, a) = a EOR b",
367 "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
368 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
370 '2. cmp %S1, %S2 /* prepare Max (%S1 - %S2), (%A1, %A2) */
371 if (mode_is_signed(get_irn_mode(n))) {
372 4. cmovl %D1, %S2 /* %S1 is less %S2 */
375 4. cmovb %D1, %S2 /* %S1 is below %S2 */
379 "units" => [ "ALU" ],
384 "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
385 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
387 '2. cmp %S1, %S2 /* prepare Min (%S1 - %S2), (%A1, %A2) */
388 if (mode_is_signed(get_irn_mode(n))) {
389 2. cmovg %D1, %S2 /* %S1 is greater %S2 */
392 2. cmova %D1, %S2, %D1 /* %S1 is above %S2 */
396 "units" => [ "ALU" ],
399 # not commutative operations
403 "comment" => "construct Sub: Sub(a, b) = a - b",
404 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
405 "emit" => '. sub %ia32_emit_binop /* Sub(%A3, %A4) -> %D1 */',
406 "units" => [ "ALU" ],
410 "comment" => "construct Sub with Carry: SubC(a, b) = a - b - carry",
411 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3 !in_r4" ] },
412 "emit" => '. sbb %ia32_emit_binop /* SubC(%A3, %A4) -> %D1 */',
413 "units" => [ "ALU" ],
418 "comment" => "construct 64Bit Sub: Sub(a_l, a_h, b_l, b_h) = a_l - b_l; a_h - b_h - borrow",
420 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
422 . mov %D1, %S1 /* mov a_l into assigned l_res register */
423 . mov %D2, %S2 /* mov a_h into assigned h_res register */
424 . sub %D1, %S3 /* a_l - b_l */
425 . sbb %D2, %S4 /* a_h - b_h - borrow */
427 "outs" => [ "low_res", "high_res" ],
428 "units" => [ "ALU" ],
433 "cmp_attr" => "return 1;",
434 "comment" => "construct lowered Sub: Sub(a, b) = a - b",
439 "cmp_attr" => "return 1;",
440 "comment" => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
446 "state" => "exc_pinned",
447 "reg_req" => { "in" => [ "eax", "gp", "edx", "none" ], "out" => [ "eax", "edx" ] },
448 "attr" => "ia32_op_flavour_t dm_flav",
449 "init_attr" => " attr->data.op_flav = dm_flav;",
450 "cmp_attr" => " return attr_a->data.op_flav != attr_b->data.op_flav;\n",
452 ' if (mode_is_signed(get_ia32_res_mode(n))) {
453 4. idiv %S2 /* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
456 4. div %S2 /* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
459 "outs" => [ "div_res", "mod_res", "M" ],
461 "units" => [ "ALU" ],
466 "comment" => "construct Shl: Shl(a, b) = a << b",
467 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
468 "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */',
469 "units" => [ "ALU1", "SSE1" ],
473 "cmp_attr" => "return 1;",
474 "comment" => "construct lowered Shl: Shl(a, b) = a << b",
480 "comment" => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
481 # Out requirements is: different from all in
482 # This is because, out must be different from LowPart and ShiftCount.
483 # We could say "!ecx !in_r4" but it can occur, that all values live through
484 # this Shift and the only value dying is the ShiftCount. Then there would be a
485 # register missing, as result must not be ecx and all other registers are
486 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
487 # (and probably never will). So we create artificial interferences of the result
488 # with all inputs, so the spiller can always assure a free register.
489 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!in" ] },
492 if (get_ia32_immop_type(n) == ia32_ImmNone) {
493 if (get_ia32_op_type(n) == ia32_AddrModeD) {
494 4. shld %ia32_emit_am, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
497 4. shld %S3, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
501 if (get_ia32_op_type(n) == ia32_AddrModeD) {
502 4. shld %ia32_emit_am, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
505 4. shld %S3, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
510 "units" => [ "ALU1", "SSE1" ],
514 "cmp_attr" => "return 1;",
515 "comment" => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
521 "comment" => "construct Shr: Shr(a, b) = a >> b",
522 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
523 "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */',
524 "units" => [ "ALU1", "SSE1" ],
528 "cmp_attr" => "return 1;",
529 "comment" => "construct lowered Shr: Shr(a, b) = a << b",
535 "comment" => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
536 # Out requirements is: different from all in
537 # This is because, out must be different from LowPart and ShiftCount.
538 # We could say "!ecx !in_r4" but it can occur, that all values live through
539 # this Shift and the only value dying is the ShiftCount. Then there would be a
540 # register missing, as result must not be ecx and all other registers are
541 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
542 # (and probably never will). So we create artificial interferences of the result
543 # with all inputs, so the spiller can always assure a free register.
544 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!in" ] },
547 if (get_ia32_immop_type(n) == ia32_ImmNone) {
548 if (get_ia32_op_type(n) == ia32_AddrModeD) {
549 4. shrd %ia32_emit_am, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
552 4. shrd %S3, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
556 if (get_ia32_op_type(n) == ia32_AddrModeD) {
557 4. shrd %ia32_emit_am, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
560 4. shrd %S3, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
565 "units" => [ "ALU1", "SSE1" ],
569 "cmp_attr" => "return 1;",
570 "comment" => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
576 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
577 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
578 "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */',
579 "units" => [ "ALU1", "SSE1" ],
583 "cmp_attr" => "return 1;",
584 "comment" => "construct lowered Shrs: Shrs(a, b) = a << b",
590 "comment" => "construct RotR: RotR(a, b) = a ROTR b",
591 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
592 "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */',
593 "units" => [ "ALU1", "SSE1" ],
598 "comment" => "construct RotL: RotL(a, b) = a ROTL b",
599 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
600 "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */',
601 "units" => [ "ALU1", "SSE1" ],
608 "comment" => "construct Minus: Minus(a) = -a",
609 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
610 "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */',
611 "units" => [ "ALU" ],
616 "comment" => "construct 64Bit Minus: Minus(a_l, a_h, 0) = 0 - a_l; 0 - a_h - borrow",
618 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
620 . mov %D1, %S1 /* l_res */
621 . mov %D2, %S1 /* h_res */
622 . sub %D1, %S2 /* 0 - a_l -> low_res */
623 . sbb %D2, %S3 /* 0 - a_h - borrow -> high_res */
625 "outs" => [ "low_res", "high_res" ],
626 "units" => [ "ALU" ],
631 "cmp_attr" => "return 1;",
632 "comment" => "construct lowered Minus: Minus(a) = -a",
638 "comment" => "construct Increment: Inc(a) = a++",
639 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
640 "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */',
641 "units" => [ "ALU" ],
646 "comment" => "construct Decrement: Dec(a) = a--",
647 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
648 "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */',
649 "units" => [ "ALU" ],
654 "comment" => "construct Not: Not(a) = !a",
655 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
656 "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */',
657 "units" => [ "ALU" ],
663 "op_flags" => "L|X|Y",
664 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
665 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
666 "outs" => [ "false", "true" ],
668 "units" => [ "BRANCH" ],
672 "op_flags" => "L|X|Y",
673 "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
674 "reg_req" => { "in" => [ "gp", "gp" ] },
675 "outs" => [ "false", "true" ],
677 "units" => [ "BRANCH" ],
681 "op_flags" => "L|X|Y",
682 "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
683 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
684 "outs" => [ "false", "true" ],
685 "units" => [ "BRANCH" ],
689 "op_flags" => "L|X|Y",
690 "comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
691 "reg_req" => { "in" => [ "gp", "gp" ] },
692 "units" => [ "BRANCH" ],
696 "op_flags" => "L|X|Y",
697 "comment" => "construct switch",
698 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
700 "units" => [ "BRANCH" ],
706 "comment" => "represents an integer constant",
707 "reg_req" => { "out" => [ "gp" ] },
708 "units" => [ "ALU" ],
712 # we should not rematrialize this node. It produces 2 results and has
713 # very strict constrains
714 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
715 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
716 "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */',
717 "outs" => [ "EAX", "EDX" ],
718 "units" => [ "ALU" ],
725 "state" => "exc_pinned",
726 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
727 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
730 ' if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) {
731 4. mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
734 4. mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
737 "outs" => [ "res", "M" ],
738 "units" => [ "MEM" ],
743 "cmp_attr" => "return 1;",
744 "comment" => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg",
745 "outs" => [ "res", "M" ],
751 "cmp_attr" => "return 1;",
752 "state" => "exc_pinned",
753 "comment" => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val",
760 "state" => "exc_pinned",
761 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
762 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
763 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
765 "units" => [ "MEM" ],
771 "state" => "exc_pinned",
772 "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
773 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
774 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
776 "units" => [ "MEM" ],
782 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
783 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
784 "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */',
786 "units" => [ "ALU" ],
790 "comment" => "push on the stack",
791 "reg_req" => { "in" => [ "gp", "gp", "gp", "esp", "none" ], "out" => [ "esp" ] },
792 "emit" => '. push %ia32_emit_unop /* PUSH(%A1) */',
793 "outs" => [ "stack:I|S", "M" ],
795 "units" => [ "MEM" ],
799 # We don't set class modify stack here (but we will do this on proj 1)
800 "comment" => "pop a gp register from the stack",
801 "reg_req" => { "in" => [ "gp", "gp", "esp", "none" ], "out" => [ "gp", "esp" ] },
802 "emit" => '. pop %ia32_emit_unop /* POP(%A1) */',
803 "outs" => [ "res", "stack:I|S", "M" ],
805 "units" => [ "MEM" ],
809 "comment" => "create stack frame",
810 "reg_req" => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] },
811 "emit" => '. enter /* Enter */',
812 "outs" => [ "frame:I", "stack:I|S", "M" ],
814 "units" => [ "MEM" ],
818 "comment" => "destroy stack frame",
819 "reg_req" => { "in" => [ "esp", "ebp" ], "out" => [ "ebp", "esp" ] },
820 "emit" => '. leave /* Leave */',
821 "outs" => [ "frame:I", "stack:I|S", "M" ],
823 "units" => [ "MEM" ],
828 "comment" => "allocate space on stack",
829 "reg_req" => { "in" => [ "esp", "gp" ], "out" => [ "esp", "none" ] },
830 "outs" => [ "stack:S", "M" ],
831 "units" => [ "ALU" ],
836 "comment" => "free space on stack",
837 "reg_req" => { "in" => [ "esp", "gp" ], "out" => [ "esp", "none" ] },
838 "outs" => [ "stack:S", "M" ],
839 "units" => [ "ALU" ],
844 "comment" => "get the TLS base address",
845 "reg_req" => { "out" => [ "gp" ] },
846 "units" => [ "MEM" ],
851 #-----------------------------------------------------------------------------#
852 # _____ _____ ______ __ _ _ _ #
853 # / ____/ ____| ____| / _| | | | | | #
854 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
855 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
856 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
857 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
858 #-----------------------------------------------------------------------------#
860 # commutative operations
864 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
865 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
866 "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */',
868 "units" => [ "SSE" ],
873 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
874 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
875 "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */',
877 "units" => [ "SSE" ],
882 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
883 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
884 "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */',
886 "units" => [ "SSE" ],
891 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
892 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
893 "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */',
895 "units" => [ "SSE" ],
900 "comment" => "construct SSE And: And(a, b) = a AND b",
901 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
902 "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */',
904 "units" => [ "SSE" ],
909 "comment" => "construct SSE Or: Or(a, b) = a OR b",
910 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
911 "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */',
912 "units" => [ "SSE" ],
917 "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
918 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
919 "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */',
921 "units" => [ "SSE" ],
924 # not commutative operations
928 "comment" => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
929 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
930 "emit" => '. andnp%M %ia32_emit_binop /* SSE AndNot(%A3, %A4) -> %D1 */',
932 "units" => [ "SSE" ],
937 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
938 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
939 "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */',
941 "units" => [ "SSE" ],
946 "comment" => "construct SSE Div: Div(a, b) = a / b",
947 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
948 "outs" => [ "res", "M" ],
949 "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */',
951 "units" => [ "SSE" ],
958 "comment" => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
959 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
961 "units" => [ "SSE" ],
965 "op_flags" => "L|X|Y",
966 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
967 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
968 "outs" => [ "false", "true" ],
970 "units" => [ "SSE" ],
976 "comment" => "represents a SSE constant",
977 "reg_req" => { "out" => [ "xmm" ] },
978 "emit" => '. movs%M %D1, %C /* Load fConst into register */',
980 "units" => [ "SSE" ],
987 "state" => "exc_pinned",
988 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
989 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm" ] },
990 "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */',
991 "outs" => [ "res", "M" ],
993 "units" => [ "SSE" ],
998 "state" => "exc_pinned",
999 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
1000 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
1001 "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */',
1003 "units" => [ "MEM" ],
1008 "op_flags" => "L|F",
1009 "state" => "exc_pinned",
1010 "comment" => "construct Store without index: Store(ptr, val, mem) = ST ptr,val",
1011 "reg_req" => { "in" => [ "gp", "xmm", "none" ] },
1012 "emit" => '. movs%M %ia32_emit_am, %S2 /* store XMM0 onto stack */',
1014 "units" => [ "MEM" ],
1019 "op_flags" => "L|F",
1020 "comment" => "construct: transfer a value from x87 FPU into a SSE register",
1021 "cmp_attr" => "return 1;",
1026 "op_flags" => "L|F",
1027 "comment" => "construct: transfer a value from SSE register to x87 FPU",
1028 "cmp_attr" => "return 1;",
1033 "op_flags" => "L|F",
1035 "state" => "exc_pinned",
1036 "comment" => "store ST0 onto stack",
1037 "reg_req" => { "in" => [ "gp", "gp", "none" ] },
1038 "emit" => '. fstp %ia32_emit_am /* store ST0 onto stack */',
1040 "units" => [ "MEM" ],
1045 "op_flags" => "L|F",
1047 "state" => "exc_pinned",
1048 "comment" => "load ST0 from stack",
1049 "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "vf0", "none" ] },
1050 "emit" => '. fld %ia32_emit_am /* load ST0 from stack */',
1051 "outs" => [ "res", "M" ],
1053 "units" => [ "MEM" ],
1059 "op_flags" => "F|H",
1060 "state" => "pinned",
1061 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
1062 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "edi", "esi", "ecx", "none" ] },
1063 "outs" => [ "DST", "SRC", "CNT", "M" ],
1064 "units" => [ "MEM" ],
1068 "op_flags" => "F|H",
1069 "state" => "pinned",
1070 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
1071 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "edi", "esi", "none" ] },
1072 "outs" => [ "DST", "SRC", "M" ],
1073 "units" => [ "MEM" ],
1079 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
1080 "comment" => "construct Conv Int -> Int",
1081 "units" => [ "ALU" ],
1085 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
1086 "comment" => "construct Conv Int -> Int",
1087 "units" => [ "ALU" ],
1091 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
1092 "comment" => "construct Conv Int -> Floating Point",
1094 "units" => [ "SSE" ],
1098 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
1099 "comment" => "construct Conv Floating Point -> Int",
1101 "units" => [ "SSE" ],
1105 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
1106 "comment" => "construct Conv Floating Point -> Floating Point",
1108 "units" => [ "SSE" ],
1113 "comment" => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
1114 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "in_r4" ] },
1116 "units" => [ "ALU" ],
1121 "comment" => "check if Psi condition tree evaluates to true and move result accordingly",
1122 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r3" ] },
1124 "units" => [ "ALU" ],
1129 "comment" => "construct Conditional Move: SSE Compare + int CMov ",
1130 "reg_req" => { "in" => [ "xmm", "xmm", "gp", "gp" ], "out" => [ "in_r4" ] },
1132 "units" => [ "SSE" ],
1137 "comment" => "construct Conditional Move: x87 Compare + int CMov",
1138 "reg_req" => { "in" => [ "vfp", "vfp", "gp", "gp" ], "out" => [ "in_r4" ] },
1140 "units" => [ "FPU" ],
1145 "comment" => "construct Set: Set(sel) == sel ? 1 : 0",
1146 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1148 "units" => [ "ALU" ],
1153 "comment" => "check if Psi condition tree evaluates to true and set result accordingly",
1154 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax ebx ecx edx" ] },
1156 "units" => [ "ALU" ],
1161 "comment" => "construct Set: SSE Compare + int Set",
1162 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1164 "units" => [ "SSE" ],
1169 "comment" => "construct Set: x87 Compare + int Set",
1170 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1172 "units" => [ "FPU" ],
1177 "comment" => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
1178 "reg_req" => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] },
1180 "units" => [ "FPU" ],
1183 #----------------------------------------------------------#
1185 # (_) | | | | / _| | | | #
1186 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
1187 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
1188 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
1189 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
1191 # _ __ ___ __| | ___ ___ #
1192 # | '_ \ / _ \ / _` |/ _ \/ __| #
1193 # | | | | (_) | (_| | __/\__ \ #
1194 # |_| |_|\___/ \__,_|\___||___/ #
1195 #----------------------------------------------------------#
1199 "comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
1200 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1202 "units" => [ "FPU" ],
1207 "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1208 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1210 "units" => [ "FPU" ],
1215 "cmp_attr" => "return 1;",
1216 "comment" => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1222 "comment" => "virtual fp Sub: Sub(a, b) = a - b",
1223 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1225 "units" => [ "FPU" ],
1229 "cmp_attr" => "return 1;",
1230 "comment" => "lowered virtual fp Sub: Sub(a, b) = a - b",
1235 "comment" => "virtual fp Div: Div(a, b) = a / b",
1236 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1237 "outs" => [ "res", "M" ],
1239 "units" => [ "FPU" ],
1243 "cmp_attr" => "return 1;",
1244 "comment" => "lowered virtual fp Div: Div(a, b) = a / b",
1249 "comment" => "virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1250 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1252 "units" => [ "FPU" ],
1256 "cmp_attr" => "return 1;",
1257 "comment" => "lowered virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1263 "comment" => "virtual fp Abs: Abs(a) = |a|",
1264 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1266 "units" => [ "FPU" ],
1271 "comment" => "virtual fp Chs: Chs(a) = -a",
1272 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1274 "units" => [ "FPU" ],
1279 "comment" => "virtual fp Sin: Sin(a) = sin(a)",
1280 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1282 "units" => [ "FPU" ],
1287 "comment" => "virtual fp Cos: Cos(a) = cos(a)",
1288 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1290 "units" => [ "FPU" ],
1295 "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
1296 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1298 "units" => [ "FPU" ],
1301 # virtual Load and Store
1304 "op_flags" => "L|F",
1305 "state" => "exc_pinned",
1306 "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
1307 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1308 "outs" => [ "res", "M" ],
1310 "units" => [ "FPU" ],
1314 "op_flags" => "L|F",
1315 "state" => "exc_pinned",
1316 "comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
1317 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1319 "units" => [ "FPU" ],
1326 "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1327 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1328 "outs" => [ "res", "M" ],
1330 "units" => [ "FPU" ],
1334 "cmp_attr" => "return 1;",
1335 "comment" => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1336 "outs" => [ "res", "M" ],
1341 "comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1342 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1344 "units" => [ "FPU" ],
1349 "cmp_attr" => "return 1;",
1350 "comment" => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1360 "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg",
1361 "reg_req" => { "out" => [ "vfp" ] },
1363 "units" => [ "FPU" ],
1368 "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg",
1369 "reg_req" => { "out" => [ "vfp" ] },
1371 "units" => [ "FPU" ],
1376 "comment" => "virtual fp Load pi: Ld pi -> reg",
1377 "reg_req" => { "out" => [ "vfp" ] },
1379 "units" => [ "FPU" ],
1384 "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg",
1385 "reg_req" => { "out" => [ "vfp" ] },
1387 "units" => [ "FPU" ],
1392 "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg",
1393 "reg_req" => { "out" => [ "vfp" ] },
1395 "units" => [ "FPU" ],
1400 "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg",
1401 "reg_req" => { "out" => [ "vfp" ] },
1403 "units" => [ "FPU" ],
1408 "comment" => "virtual fp Load ld e: Ld ld e -> reg",
1409 "reg_req" => { "out" => [ "vfp" ] },
1411 "units" => [ "FPU" ],
1417 "init_attr" => " set_ia32_ls_mode(res, mode);",
1418 "comment" => "represents a virtual floating point constant",
1419 "reg_req" => { "out" => [ "vfp" ] },
1421 "units" => [ "FPU" ],
1427 "op_flags" => "L|X|Y",
1428 "comment" => "represents a virtual floating point compare",
1429 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] },
1430 "outs" => [ "false", "true", "temp_reg_eax" ],
1432 "units" => [ "FPU" ],
1435 #------------------------------------------------------------------------#
1436 # ___ _____ __ _ _ _ #
1437 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1438 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1439 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1440 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1441 #------------------------------------------------------------------------#
1445 "rd_constructor" => "NONE",
1446 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1448 "emit" => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A3, %A4) -> %D1 */',
1453 "rd_constructor" => "NONE",
1454 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1456 "emit" => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A3, %A4) -> %D1 */',
1461 "rd_constructor" => "NONE",
1462 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1464 "emit" => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A3, %A4) -> %D1 */',
1469 "rd_constructor" => "NONE",
1470 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1472 "emit" => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A3, %A4) -> %D1 */',,
1477 "rd_constructor" => "NONE",
1478 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1480 "emit" => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A3, %A4) -> %D1 */',
1485 "rd_constructor" => "NONE",
1486 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1488 "emit" => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A3, %A4) -> %D1 */',
1493 "rd_constructor" => "NONE",
1495 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1497 "emit" => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A3, %A4) -> %D1 */',
1502 "rd_constructor" => "NONE",
1504 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1506 "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A3, %A4) -> %D1 */',
1511 "rd_constructor" => "NONE",
1512 "comment" => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1514 "emit" => '. fprem1 /* x87 fprem(%A3, %A4) -> %D1 */',
1517 # this node is just here, to keep the simulator running
1518 # we can omit this when a fprem simulation function exists
1521 "rd_constructor" => "NONE",
1522 "comment" => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1524 "emit" => '. fprem1 /* x87 fprem(%A3, %A4) -> %D1 WITH POP */',
1529 "rd_constructor" => "NONE",
1530 "comment" => "x87 fp Div: Div(a, b) = a / b",
1532 "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A3, %A4) -> %D1 */',
1537 "rd_constructor" => "NONE",
1538 "comment" => "x87 fp Div: Div(a, b) = a / b",
1540 "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A3, %A4) -> %D1 */',
1545 "rd_constructor" => "NONE",
1546 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1548 "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A3, %A4) -> %D1 */',
1553 "rd_constructor" => "NONE",
1554 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1556 "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A3, %A4) -> %D1 */',
1561 "rd_constructor" => "NONE",
1562 "comment" => "x87 fp Abs: Abs(a) = |a|",
1564 "emit" => '. fabs /* x87 fabs(%A1) -> %D1 */',
1569 "rd_constructor" => "NONE",
1570 "comment" => "x87 fp Chs: Chs(a) = -a",
1572 "emit" => '. fchs /* x87 fchs(%A1) -> %D1 */',
1577 "rd_constructor" => "NONE",
1578 "comment" => "x87 fp Sin: Sin(a) = sin(a)",
1580 "emit" => '. fsin /* x87 sin(%A1) -> %D1 */',
1585 "rd_constructor" => "NONE",
1586 "comment" => "x87 fp Cos: Cos(a) = cos(a)",
1588 "emit" => '. fcos /* x87 cos(%A1) -> %D1 */',
1593 "rd_constructor" => "NONE",
1594 "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1596 "emit" => '. fsqrt $ /* x87 sqrt(%A1) -> %D1 */',
1599 # x87 Load and Store
1602 "rd_constructor" => "NONE",
1603 "op_flags" => "R|L|F",
1604 "state" => "exc_pinned",
1605 "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1607 "emit" => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */',
1611 "rd_constructor" => "NONE",
1612 "op_flags" => "R|L|F",
1613 "state" => "exc_pinned",
1614 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1616 "emit" => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */',
1621 "rd_constructor" => "NONE",
1622 "op_flags" => "R|L|F",
1623 "state" => "exc_pinned",
1624 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1626 "emit" => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */',
1634 "rd_constructor" => "NONE",
1635 "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1637 "emit" => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */',
1642 "rd_constructor" => "NONE",
1643 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1645 "emit" => '. fist %ia32_emit_am /* integer Store(%A3) -> (%A1) */',
1651 "rd_constructor" => "NONE",
1652 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1654 "emit" => '. fistp %ia32_emit_am /* integer Store(%A3) -> (%A1) and pop */',
1661 "op_flags" => "R|c",
1663 "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
1664 "reg_req" => { "out" => [ "vfp" ] },
1665 "emit" => '. fldz /* x87 0.0 -> %D1 */',
1669 "op_flags" => "R|c",
1671 "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
1672 "reg_req" => { "out" => [ "vfp" ] },
1673 "emit" => '. fld1 /* x87 1.0 -> %D1 */',
1677 "op_flags" => "R|c",
1679 "comment" => "x87 fp Load pi: Ld pi -> reg",
1680 "reg_req" => { "out" => [ "vfp" ] },
1681 "emit" => '. fldpi /* x87 pi -> %D1 */',
1685 "op_flags" => "R|c",
1687 "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
1688 "reg_req" => { "out" => [ "vfp" ] },
1689 "emit" => '. fldln2 /* x87 ln(2) -> %D1 */',
1693 "op_flags" => "R|c",
1695 "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
1696 "reg_req" => { "out" => [ "vfp" ] },
1697 "emit" => '. fldlg2 /* x87 log(2) -> %D1 */',
1701 "op_flags" => "R|c",
1703 "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
1704 "reg_req" => { "out" => [ "vfp" ] },
1705 "emit" => '. fldll2t /* x87 ld(10) -> %D1 */',
1709 "op_flags" => "R|c",
1711 "comment" => "x87 fp Load ld e: Ld ld e -> reg",
1712 "reg_req" => { "out" => [ "vfp" ] },
1713 "emit" => '. fldl2e /* x87 ld(e) -> %D1 */',
1717 "op_flags" => "R|c",
1719 "rd_constructor" => "NONE",
1720 "comment" => "represents a x87 constant",
1721 "reg_req" => { "out" => [ "vfp" ] },
1722 "emit" => '. fld %ia32_emit_adr /* Load fConst into register -> %D1 */',
1726 # Note that it is NEVER allowed to do CSE on these nodes
1727 # Moreover, note the virtual register requierements!
1730 "op_flags" => "R|K",
1731 "comment" => "x87 stack exchange",
1733 "cmp_attr" => "return 1;",
1734 "emit" => '. fxch %X1 /* x87 swap %X1, %X3 */',
1738 "op_flags" => "R|K",
1739 "comment" => "x87 stack push",
1741 "cmp_attr" => "return 1;",
1742 "emit" => '. fld %X1 /* x87 push %X1 */',
1747 "comment" => "x87 stack push",
1748 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1749 "cmp_attr" => "return 1;",
1750 "emit" => '. fld %X1 /* x87 push %X1 */',
1754 "op_flags" => "R|K",
1755 "comment" => "x87 stack pop",
1757 "cmp_attr" => "return 1;",
1758 "emit" => '. fstp %X1 /* x87 pop %X1 */',
1764 "op_flags" => "L|X|Y",
1765 "comment" => "floating point compare",
1770 "op_flags" => "L|X|Y",
1771 "comment" => "floating point compare and pop",
1776 "op_flags" => "L|X|Y",
1777 "comment" => "floating point compare and pop twice",
1782 "op_flags" => "L|X|Y",
1783 "comment" => "floating point compare reverse",
1788 "op_flags" => "L|X|Y",
1789 "comment" => "floating point compare reverse and pop",
1794 "op_flags" => "L|X|Y",
1795 "comment" => "floating point compare reverse and pop twice",