3 # This is the specification for the ia32 assembler Firm-operations
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
8 # this strings mark the beginning and the end of a comment in emit
9 $comment_string = "/*";
10 $comment_string_end = "*/";
12 # the number of additional opcodes you want to register
13 #$additional_opcodes = 0;
15 # The node description is done as a perl hash initializer with the
16 # following structure:
21 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
22 # "irn_flags" => "R|N|I|S"
23 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
24 # "state" => "floats|pinned|mem_pinned|exc_pinned",
26 # { "type" => "type 1", "name" => "name 1" },
27 # { "type" => "type 2", "name" => "name 2" },
30 # "comment" => "any comment for constructor",
31 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
32 # "cmp_attr" => "c source code for comparing node attributes",
33 # "emit" => "emit code with templates",
34 # "attr" => "attitional attribute arguments for constructor"
35 # "init_attr" => "emit attribute initialization template"
36 # "rd_constructor" => "c source code which constructs an ir_node"
37 # "latency" => "latency of this operation (can be float)"
40 # ... # (all nodes you need to describe)
42 # ); # close the %nodes initializer
44 # op_flags: flags for the operation, OPTIONAL (default is "N")
45 # the op_flags correspond to the firm irop_flags:
48 # C irop_flag_commutative
49 # X irop_flag_cfopcode
50 # I irop_flag_ip_cfopcode
53 # H irop_flag_highlevel
54 # c irop_flag_constlike
57 # irn_flags: special node flags, OPTIONAL (default is 0)
58 # following irn_flags are supported:
61 # I ignore for register allocation
62 # S modifies stack pointer
64 # state: state of the operation, OPTIONAL (default is "floats")
66 # arity: arity of the operation, MUST NOT BE OMITTED
68 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
69 # are always the first 3 arguments and are always autmatically
71 # If this key is missing the following arguments will be created:
72 # for i = 1 .. arity: ir_node *op_i
75 # outs: if a node defines more than one output, the names of the projections
76 # nodes having outs having automatically the mode mode_T
77 # One can also annotate some flags for each out, additional to irn_flags.
78 # They are separated from name with a colon ':', and concatenated by pipe '|'
79 # Only I and S are available at the moment (same meaning as in irn_flags).
80 # example: [ "frame:I", "stack:I|S", "M" ]
82 # comment: OPTIONAL comment for the node constructor
84 # rd_constructor: for every operation there will be a
85 # new_rd_<arch>_<op-name> function with the arguments from above
86 # which creates the ir_node corresponding to the defined operation
87 # you can either put the complete source code of this function here
89 # This key is OPTIONAL. If omitted, the following constructor will
91 # if (!op_<arch>_<op-name>) assert(0);
95 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
98 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
100 # latency: the latency of the operation, default is 1
104 # 0 - no special type
105 # 1 - caller save (register must be saved by the caller of a function)
106 # 2 - callee save (register must be saved by the called function)
107 # 4 - ignore (do not assign this register)
108 # 8 - emitter can choose an arbitrary register of this class
109 # 16 - the register is a virtual one
110 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
113 { "name" => "eax", "type" => 1 },
114 { "name" => "edx", "type" => 1 },
115 { "name" => "ebx", "type" => 2 },
116 { "name" => "ecx", "type" => 1 },
117 { "name" => "esi", "type" => 2 },
118 { "name" => "edi", "type" => 2 },
119 { "name" => "ebp", "type" => 2 },
120 { "name" => "esp", "type" => 4 },
121 { "name" => "gp_NOREG", "type" => 2 | 4 | 16 }, # we need a dummy register for NoReg nodes
122 { "name" => "gp_UKNWN", "type" => 2 | 4 | 8 | 16}, # we need a dummy register for Unknown nodes
123 { "mode" => "mode_P" }
126 { "name" => "xmm0", "type" => 1 },
127 { "name" => "xmm1", "type" => 1 },
128 { "name" => "xmm2", "type" => 1 },
129 { "name" => "xmm3", "type" => 1 },
130 { "name" => "xmm4", "type" => 1 },
131 { "name" => "xmm5", "type" => 1 },
132 { "name" => "xmm6", "type" => 1 },
133 { "name" => "xmm7", "type" => 1 },
134 { "name" => "xmm_NOREG", "type" => 2 | 4 | 16 }, # we need a dummy register for NoReg nodes
135 { "name" => "xmm_UKNWN", "type" => 2 | 4 | 8 | 16}, # we need a dummy register for Unknown nodes
136 { "mode" => "mode_D" }
139 { "name" => "vf0", "type" => 1 | 16 },
140 { "name" => "vf1", "type" => 1 | 16 },
141 { "name" => "vf2", "type" => 1 | 16 },
142 { "name" => "vf3", "type" => 1 | 16 },
143 { "name" => "vf4", "type" => 1 | 16 },
144 { "name" => "vf5", "type" => 1 | 16 },
145 { "name" => "vf6", "type" => 1 | 16 },
146 { "name" => "vf7", "type" => 1 | 16 },
147 { "name" => "vfp_NOREG", "type" => 2 | 4 | 16 }, # we need a dummy register for NoReg nodes
148 { "name" => "vfp_UKNWN", "type" => 2 | 4 | 8 | 16}, # we need a dummy register for Unknown nodes
149 { "mode" => "mode_E" }
152 { "name" => "st0", "type" => 1 },
153 { "name" => "st1", "type" => 1 },
154 { "name" => "st2", "type" => 1 },
155 { "name" => "st3", "type" => 1 },
156 { "name" => "st4", "type" => 1 },
157 { "name" => "st5", "type" => 1 },
158 { "name" => "st6", "type" => 1 },
159 { "name" => "st7", "type" => 1 },
160 { "mode" => "mode_E" }
162 "fp_cw" => [ # the floating point control word
163 { "name" => "fpcw", "type" => 0 },
164 { "mode" => "mode_Hu" },
169 "ALU" => [ 1, "ALU1", "ALU2", "ALU3", "ALU4" ],
170 "MUL" => [ 1, "MUL1", "MUL2" ],
171 "SSE" => [ 1, "SSE1", "SSE2" ],
172 "FPU" => [ 1, "FPU1" ],
173 "MEM" => [ 1, "MEM1", "MEM2" ],
174 "BRANCH" => [ 1, "BRANCH1", "BRANCH2" ],
175 "DUMMY" => [ 1, "DUMMY1", "DUMMY2", "DUMMY3", "DUMMY4" ]
180 "bundels_per_cycle" => 2
183 #--------------------------------------------------#
186 # _ __ _____ __ _ _ __ ___ _ __ ___ #
187 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
188 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
189 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
192 #--------------------------------------------------#
194 $default_cmp_attr = "return ia32_compare_immop_attr(attr_a, attr_b);";
201 #-----------------------------------------------------------------#
204 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
205 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
206 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
207 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
210 #-----------------------------------------------------------------#
212 # commutative operations
215 # All nodes supporting Addressmode have 5 INs:
216 # 1 - base r1 == NoReg in case of no AM or no base
217 # 2 - index r2 == NoReg in case of no AM or no index
218 # 3 - op1 r3 == always present
219 # 4 - op2 r4 == NoReg in case of immediate operation
220 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
224 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
225 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
226 "emit" => '. add %ia32_emit_binop /* Add(%A3, %A4) -> %D1 */',
227 "units" => [ "ALU", "MEM" ],
231 "comment" => "construct Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
232 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
233 "emit" => '. adc %ia32_emit_binop /* AddC(%A3, %A4) -> %D1 */',
234 "units" => [ "ALU", "MEM" ],
239 "comment" => "construct 64Bit Add: Add(a_l, a_h, b_l, b_h) = a_l + b_l; a_h + b_h + carry",
241 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
243 . mov %D1, %S1 /* mov a_l into assigned l_res register */
244 . mov %D2, %S2 /* mov a_h into assigned h_res register */
245 . add %D1, %S3 /* a_l + b_l */
246 . adc %D2, %S4 /* a_h + b_h + carry */
248 "outs" => [ "low_res", "high_res" ],
249 "units" => [ "ALU", "MEM" ],
255 "cmp_attr" => "return 1;",
256 "comment" => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
262 "cmp_attr" => "return 1;",
263 "comment" => "construct lowered Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
268 # we should not rematrialize this node. It produces 2 results and has
269 # very strict constrains
270 "comment" => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
271 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] },
272 "emit" => '. mul %ia32_emit_unop /* Mul(%A1, %A2) -> %D1 */',
273 "outs" => [ "EAX", "EDX", "M" ],
275 "units" => [ "MUL" ],
279 # we should not rematrialize this node. It produces 2 results and has
280 # very strict constrains
282 "cmp_attr" => "return 1;",
283 "comment" => "construct lowered MulS: MulS(a, b) = MulS(b, a) = a * b",
284 "outs" => [ "EAX", "EDX", "M" ],
290 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
291 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
292 "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */',
294 "units" => [ "MUL" ],
299 "cmp_attr" => "return 1;",
300 "comment" => "construct lowered Mul: Mul(a, b) = Mul(b, a) = a * b",
304 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
306 # we should not rematrialize this node. It produces 2 results and has
307 # very strict constrains
308 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
309 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] },
310 "emit" => '. imul %ia32_emit_unop /* Mulh(%A1, %A2) -> %D1 */',
311 "outs" => [ "EAX", "EDX", "M" ],
313 "units" => [ "MUL" ],
318 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
319 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
320 "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */',
321 "units" => [ "ALU" ],
326 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
327 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
328 "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */',
329 "units" => [ "ALU" ],
334 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
335 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
336 "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */',
337 "units" => [ "ALU" ],
342 "cmp_attr" => "return 1;",
343 "comment" => "construct lowered Eor: Eor(a, b) = Eor(b, a) = a EOR b",
349 "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
350 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
352 '2. cmp %S1, %S2 /* prepare Max (%S1 - %S2), (%A1, %A2) */
353 if (mode_is_signed(get_irn_mode(n))) {
354 4. cmovl %D1, %S2 /* %S1 is less %S2 */
357 4. cmovb %D1, %S2 /* %S1 is below %S2 */
361 "units" => [ "ALU" ],
366 "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
367 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
369 '2. cmp %S1, %S2 /* prepare Min (%S1 - %S2), (%A1, %A2) */
370 if (mode_is_signed(get_irn_mode(n))) {
371 2. cmovg %D1, %S2 /* %S1 is greater %S2 */
374 2. cmova %D1, %S2, %D1 /* %S1 is above %S2 */
378 "units" => [ "ALU" ],
381 # not commutative operations
385 "comment" => "construct Sub: Sub(a, b) = a - b",
386 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
387 "emit" => '. sub %ia32_emit_binop /* Sub(%A3, %A4) -> %D1 */',
388 "units" => [ "ALU" ],
392 "comment" => "construct Sub with Carry: SubC(a, b) = a - b - carry",
393 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3 !in_r4" ] },
394 "emit" => '. sbb %ia32_emit_binop /* SubC(%A3, %A4) -> %D1 */',
395 "units" => [ "ALU" ],
400 "comment" => "construct 64Bit Sub: Sub(a_l, a_h, b_l, b_h) = a_l - b_l; a_h - b_h - borrow",
402 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
404 . mov %D1, %S1 /* mov a_l into assigned l_res register */
405 . mov %D2, %S2 /* mov a_h into assigned h_res register */
406 . sub %D1, %S3 /* a_l - b_l */
407 . sbb %D2, %S4 /* a_h - b_h - borrow */
409 "outs" => [ "low_res", "high_res" ],
410 "units" => [ "ALU" ],
415 "cmp_attr" => "return 1;",
416 "comment" => "construct lowered Sub: Sub(a, b) = a - b",
421 "cmp_attr" => "return 1;",
422 "comment" => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
428 "state" => "exc_pinned",
429 "reg_req" => { "in" => [ "eax", "gp", "edx", "none" ], "out" => [ "eax", "edx" ] },
430 "attr" => "ia32_op_flavour_t dm_flav",
431 "init_attr" => " attr->data.op_flav = dm_flav;",
432 "cmp_attr" => " return attr_a->data.op_flav != attr_b->data.op_flav;\n",
434 ' if (mode_is_signed(get_ia32_res_mode(n))) {
435 4. idiv %S2 /* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
438 4. div %S2 /* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
441 "outs" => [ "div_res", "mod_res", "M" ],
443 "units" => [ "ALU" ],
448 "comment" => "construct Shl: Shl(a, b) = a << b",
449 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
450 "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */',
451 "units" => [ "ALU1", "SSE1" ],
455 "cmp_attr" => "return 1;",
456 "comment" => "construct lowered Shl: Shl(a, b) = a << b",
462 "comment" => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
463 # Out requirements is: different from all in
464 # This is because, out must be different from LowPart and ShiftCount.
465 # We could say "!ecx !in_r4" but it can occur, that all values live through
466 # this Shift and the only value dying is the ShiftCount. Then there would be a
467 # register missing, as result must not be ecx and all other registers are
468 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
469 # (and probably never will). So we create artificial interferences of the result
470 # with all inputs, so the spiller can always assure a free register.
471 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!in" ] },
474 if (get_ia32_immop_type(n) == ia32_ImmNone) {
475 if (get_ia32_op_type(n) == ia32_AddrModeD) {
476 4. shld %ia32_emit_am, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
479 4. shld %S3, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
483 if (get_ia32_op_type(n) == ia32_AddrModeD) {
484 4. shld %ia32_emit_am, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
487 4. shld %S3, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
492 "units" => [ "ALU1", "SSE1" ],
496 "cmp_attr" => "return 1;",
497 "comment" => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
503 "comment" => "construct Shr: Shr(a, b) = a >> b",
504 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
505 "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */',
506 "units" => [ "ALU1", "SSE1" ],
510 "cmp_attr" => "return 1;",
511 "comment" => "construct lowered Shr: Shr(a, b) = a << b",
517 "comment" => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
518 # Out requirements is: different from all in
519 # This is because, out must be different from LowPart and ShiftCount.
520 # We could say "!ecx !in_r4" but it can occur, that all values live through
521 # this Shift and the only value dying is the ShiftCount. Then there would be a
522 # register missing, as result must not be ecx and all other registers are
523 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
524 # (and probably never will). So we create artificial interferences of the result
525 # with all inputs, so the spiller can always assure a free register.
526 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!in" ] },
529 if (get_ia32_immop_type(n) == ia32_ImmNone) {
530 if (get_ia32_op_type(n) == ia32_AddrModeD) {
531 4. shrd %ia32_emit_am, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
534 4. shrd %S3, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
538 if (get_ia32_op_type(n) == ia32_AddrModeD) {
539 4. shrd %ia32_emit_am, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
542 4. shrd %S3, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
547 "units" => [ "ALU1", "SSE1" ],
551 "cmp_attr" => "return 1;",
552 "comment" => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
558 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
559 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
560 "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */',
561 "units" => [ "ALU1", "SSE1" ],
565 "cmp_attr" => "return 1;",
566 "comment" => "construct lowered Shrs: Shrs(a, b) = a << b",
572 "comment" => "construct RotR: RotR(a, b) = a ROTR b",
573 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
574 "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */',
575 "units" => [ "ALU1", "SSE1" ],
580 "comment" => "construct RotL: RotL(a, b) = a ROTL b",
581 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
582 "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */',
583 "units" => [ "ALU1", "SSE1" ],
590 "comment" => "construct Minus: Minus(a) = -a",
591 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
592 "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */',
593 "units" => [ "ALU" ],
598 "comment" => "construct 64Bit Minus: Minus(a_l, a_h, 0) = 0 - a_l; 0 - a_h - borrow",
600 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
602 . mov %D1, %S1 /* l_res */
603 . mov %D2, %S1 /* h_res */
604 . sub %D1, %S2 /* 0 - a_l -> low_res */
605 . sbb %D2, %S3 /* 0 - a_h - borrow -> high_res */
607 "outs" => [ "low_res", "high_res" ],
608 "units" => [ "ALU" ],
613 "cmp_attr" => "return 1;",
614 "comment" => "construct lowered Minus: Minus(a) = -a",
620 "comment" => "construct Increment: Inc(a) = a++",
621 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
622 "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */',
623 "units" => [ "ALU" ],
628 "comment" => "construct Decrement: Dec(a) = a--",
629 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
630 "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */',
631 "units" => [ "ALU" ],
636 "comment" => "construct Not: Not(a) = !a",
637 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
638 "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */',
639 "units" => [ "ALU" ],
645 "op_flags" => "L|X|Y",
646 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
647 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
648 "outs" => [ "false", "true" ],
650 "units" => [ "BRANCH" ],
654 "op_flags" => "L|X|Y",
655 "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
656 "reg_req" => { "in" => [ "gp", "gp" ] },
657 "outs" => [ "false", "true" ],
659 "units" => [ "BRANCH" ],
663 "op_flags" => "L|X|Y",
664 "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
665 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
666 "outs" => [ "false", "true" ],
667 "units" => [ "BRANCH" ],
671 "op_flags" => "L|X|Y",
672 "comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
673 "reg_req" => { "in" => [ "gp", "gp" ] },
674 "units" => [ "BRANCH" ],
678 "op_flags" => "L|X|Y",
679 "comment" => "construct switch",
680 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
682 "units" => [ "BRANCH" ],
688 "comment" => "represents an integer constant",
689 "reg_req" => { "out" => [ "gp" ] },
690 "units" => [ "ALU" ],
695 "comment" => "change floating point control word",
696 "reg_req" => { "out" => [ "fp_cw" ] },
699 "units" => [ "ALU" ],
704 "state" => "exc_pinned",
705 "comment" => "load floating point control word FldCW(ptr, mem) = LD ptr -> reg",
706 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "fp_cw" ] },
708 "emit" => ". fldcw %ia32_emit_am /* FldCW(%A1) -> %D1 */",
710 "units" => [ "MEM" ],
715 "state" => "exc_pinned",
716 "comment" => "store floating point control word: FstCW(ptr, mem) = ST ptr -> reg",
717 "reg_req" => { "in" => [ "gp", "gp", "fp_cw", "none" ] },
719 "emit" => ". fstcw %ia32_emit_am /* FstCW(%A3) -> %A1 */",
721 "units" => [ "MEM" ],
725 # we should not rematrialize this node. It produces 2 results and has
726 # very strict constrains
727 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
728 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
729 "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */',
730 "outs" => [ "EAX", "EDX" ],
731 "units" => [ "ALU" ],
738 "state" => "exc_pinned",
739 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
740 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
743 ' if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) {
744 4. mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
747 4. mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
750 "outs" => [ "res", "M" ],
751 "units" => [ "MEM" ],
756 "cmp_attr" => "return 1;",
757 "comment" => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg",
758 "outs" => [ "res", "M" ],
764 "cmp_attr" => "return 1;",
765 "state" => "exc_pinned",
766 "comment" => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val",
773 "state" => "exc_pinned",
774 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
775 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
776 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
778 "units" => [ "MEM" ],
784 "state" => "exc_pinned",
785 "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
786 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
787 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
789 "units" => [ "MEM" ],
795 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
796 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
797 "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */',
799 "units" => [ "ALU" ],
803 "comment" => "push on the stack",
804 "reg_req" => { "in" => [ "gp", "gp", "gp", "esp", "none" ], "out" => [ "esp" ] },
805 "emit" => '. push %ia32_emit_unop /* PUSH(%A1) */',
806 "outs" => [ "stack:I|S", "M" ],
808 "units" => [ "MEM" ],
812 # We don't set class modify stack here (but we will do this on proj 1)
813 "comment" => "pop a gp register from the stack",
814 "reg_req" => { "in" => [ "gp", "gp", "esp", "none" ], "out" => [ "gp", "esp" ] },
815 "emit" => '. pop %ia32_emit_unop /* POP(%A1) */',
816 "outs" => [ "res", "stack:I|S", "M" ],
818 "units" => [ "MEM" ],
822 "comment" => "create stack frame",
823 "reg_req" => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] },
824 "emit" => '. enter /* Enter */',
825 "outs" => [ "frame:I", "stack:I|S", "M" ],
827 "units" => [ "MEM" ],
831 "comment" => "destroy stack frame",
832 "reg_req" => { "in" => [ "esp", "ebp" ], "out" => [ "ebp", "esp" ] },
833 "emit" => '. leave /* Leave */',
834 "outs" => [ "frame:I", "stack:I|S", "M" ],
836 "units" => [ "MEM" ],
841 "comment" => "allocate space on stack",
842 "reg_req" => { "in" => [ "esp", "gp" ], "out" => [ "esp", "none" ] },
843 "outs" => [ "stack:S", "M" ],
844 "units" => [ "ALU" ],
849 "comment" => "free space on stack",
850 "reg_req" => { "in" => [ "esp", "gp" ], "out" => [ "esp", "none" ] },
851 "outs" => [ "stack:S", "M" ],
852 "units" => [ "ALU" ],
857 "comment" => "get the TLS base address",
858 "reg_req" => { "out" => [ "gp" ] },
859 "units" => [ "MEM" ],
864 #-----------------------------------------------------------------------------#
865 # _____ _____ ______ __ _ _ _ #
866 # / ____/ ____| ____| / _| | | | | | #
867 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
868 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
869 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
870 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
871 #-----------------------------------------------------------------------------#
873 # commutative operations
877 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
878 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
879 "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */',
881 "units" => [ "SSE" ],
886 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
887 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
888 "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */',
890 "units" => [ "SSE" ],
895 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
896 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
897 "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */',
899 "units" => [ "SSE" ],
904 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
905 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
906 "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */',
908 "units" => [ "SSE" ],
913 "comment" => "construct SSE And: And(a, b) = a AND b",
914 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
915 "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */',
917 "units" => [ "SSE" ],
922 "comment" => "construct SSE Or: Or(a, b) = a OR b",
923 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
924 "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */',
925 "units" => [ "SSE" ],
930 "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
931 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
932 "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */',
934 "units" => [ "SSE" ],
937 # not commutative operations
941 "comment" => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
942 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
943 "emit" => '. andnp%M %ia32_emit_binop /* SSE AndNot(%A3, %A4) -> %D1 */',
945 "units" => [ "SSE" ],
950 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
951 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
952 "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */',
954 "units" => [ "SSE" ],
959 "comment" => "construct SSE Div: Div(a, b) = a / b",
960 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
961 "outs" => [ "res", "M" ],
962 "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */',
964 "units" => [ "SSE" ],
971 "comment" => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
972 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
974 "units" => [ "SSE" ],
978 "op_flags" => "L|X|Y",
979 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
980 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
981 "outs" => [ "false", "true" ],
983 "units" => [ "SSE" ],
989 "comment" => "represents a SSE constant",
990 "reg_req" => { "out" => [ "xmm" ] },
991 "emit" => '. movs%M %D1, %C /* Load fConst into register */',
993 "units" => [ "SSE" ],
1000 "state" => "exc_pinned",
1001 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
1002 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm" ] },
1003 "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */',
1004 "outs" => [ "res", "M" ],
1006 "units" => [ "SSE" ],
1010 "op_flags" => "L|F",
1011 "state" => "exc_pinned",
1012 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
1013 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
1014 "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */',
1016 "units" => [ "MEM" ],
1021 "op_flags" => "L|F",
1022 "state" => "exc_pinned",
1023 "comment" => "construct Store without index: Store(ptr, val, mem) = ST ptr,val",
1024 "reg_req" => { "in" => [ "gp", "xmm", "none" ] },
1025 "emit" => '. movs%M %ia32_emit_am, %S2 /* store XMM0 onto stack */',
1027 "units" => [ "MEM" ],
1032 "op_flags" => "L|F",
1033 "comment" => "construct: transfer a value from x87 FPU into a SSE register",
1034 "cmp_attr" => "return 1;",
1039 "op_flags" => "L|F",
1040 "comment" => "construct: transfer a value from SSE register to x87 FPU",
1041 "cmp_attr" => "return 1;",
1046 "op_flags" => "L|F",
1048 "state" => "exc_pinned",
1049 "comment" => "store ST0 onto stack",
1050 "reg_req" => { "in" => [ "gp", "gp", "none" ] },
1051 "emit" => '. fstp %ia32_emit_am /* store ST0 onto stack */',
1053 "units" => [ "MEM" ],
1058 "op_flags" => "L|F",
1060 "state" => "exc_pinned",
1061 "comment" => "load ST0 from stack",
1062 "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "vf0", "none" ] },
1063 "emit" => '. fld %ia32_emit_am /* load ST0 from stack */',
1064 "outs" => [ "res", "M" ],
1066 "units" => [ "MEM" ],
1072 "op_flags" => "F|H",
1073 "state" => "pinned",
1074 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
1075 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "edi", "esi", "ecx", "none" ] },
1076 "outs" => [ "DST", "SRC", "CNT", "M" ],
1077 "units" => [ "MEM" ],
1081 "op_flags" => "F|H",
1082 "state" => "pinned",
1083 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
1084 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "edi", "esi", "none" ] },
1085 "outs" => [ "DST", "SRC", "M" ],
1086 "units" => [ "MEM" ],
1092 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
1093 "comment" => "construct Conv Int -> Int",
1094 "units" => [ "ALU" ],
1098 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
1099 "comment" => "construct Conv Int -> Int",
1100 "units" => [ "ALU" ],
1104 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
1105 "comment" => "construct Conv Int -> Floating Point",
1107 "units" => [ "SSE" ],
1111 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
1112 "comment" => "construct Conv Floating Point -> Int",
1114 "units" => [ "SSE" ],
1118 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
1119 "comment" => "construct Conv Floating Point -> Floating Point",
1121 "units" => [ "SSE" ],
1126 "comment" => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
1127 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "in_r4" ] },
1129 "units" => [ "ALU" ],
1134 "comment" => "check if Psi condition tree evaluates to true and move result accordingly",
1135 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r3" ] },
1137 "units" => [ "ALU" ],
1142 "comment" => "construct Conditional Move: SSE Compare + int CMov ",
1143 "reg_req" => { "in" => [ "xmm", "xmm", "gp", "gp" ], "out" => [ "in_r4" ] },
1145 "units" => [ "SSE" ],
1150 "comment" => "construct Conditional Move: x87 Compare + int CMov",
1151 "reg_req" => { "in" => [ "vfp", "vfp", "gp", "gp" ], "out" => [ "in_r4" ] },
1153 "units" => [ "FPU" ],
1158 "comment" => "construct Set: Set(sel) == sel ? 1 : 0",
1159 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1161 "units" => [ "ALU" ],
1166 "comment" => "check if Psi condition tree evaluates to true and set result accordingly",
1167 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax ebx ecx edx" ] },
1169 "units" => [ "ALU" ],
1174 "comment" => "construct Set: SSE Compare + int Set",
1175 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1177 "units" => [ "SSE" ],
1182 "comment" => "construct Set: x87 Compare + int Set",
1183 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1185 "units" => [ "FPU" ],
1190 "comment" => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
1191 "reg_req" => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] },
1193 "units" => [ "FPU" ],
1196 #----------------------------------------------------------#
1198 # (_) | | | | / _| | | | #
1199 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
1200 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
1201 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
1202 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
1204 # _ __ ___ __| | ___ ___ #
1205 # | '_ \ / _ \ / _` |/ _ \/ __| #
1206 # | | | | (_) | (_| | __/\__ \ #
1207 # |_| |_|\___/ \__,_|\___||___/ #
1208 #----------------------------------------------------------#
1212 "comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
1213 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1215 "units" => [ "FPU" ],
1220 "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1221 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1223 "units" => [ "FPU" ],
1228 "cmp_attr" => "return 1;",
1229 "comment" => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1235 "comment" => "virtual fp Sub: Sub(a, b) = a - b",
1236 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1238 "units" => [ "FPU" ],
1242 "cmp_attr" => "return 1;",
1243 "comment" => "lowered virtual fp Sub: Sub(a, b) = a - b",
1248 "comment" => "virtual fp Div: Div(a, b) = a / b",
1249 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1250 "outs" => [ "res", "M" ],
1252 "units" => [ "FPU" ],
1256 "cmp_attr" => "return 1;",
1257 "comment" => "lowered virtual fp Div: Div(a, b) = a / b",
1262 "comment" => "virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1263 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1265 "units" => [ "FPU" ],
1269 "cmp_attr" => "return 1;",
1270 "comment" => "lowered virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1276 "comment" => "virtual fp Abs: Abs(a) = |a|",
1277 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1279 "units" => [ "FPU" ],
1284 "comment" => "virtual fp Chs: Chs(a) = -a",
1285 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1287 "units" => [ "FPU" ],
1292 "comment" => "virtual fp Sin: Sin(a) = sin(a)",
1293 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1295 "units" => [ "FPU" ],
1300 "comment" => "virtual fp Cos: Cos(a) = cos(a)",
1301 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1303 "units" => [ "FPU" ],
1308 "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
1309 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1311 "units" => [ "FPU" ],
1314 # virtual Load and Store
1317 "op_flags" => "L|F",
1318 "state" => "exc_pinned",
1319 "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
1320 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1321 "outs" => [ "res", "M" ],
1323 "units" => [ "FPU" ],
1327 "op_flags" => "L|F",
1328 "state" => "exc_pinned",
1329 "comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
1330 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1332 "units" => [ "FPU" ],
1339 "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1340 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1341 "outs" => [ "res", "M" ],
1343 "units" => [ "FPU" ],
1347 "cmp_attr" => "return 1;",
1348 "comment" => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1349 "outs" => [ "res", "M" ],
1354 "comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1355 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1357 "units" => [ "FPU" ],
1362 "cmp_attr" => "return 1;",
1363 "comment" => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1373 "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg",
1374 "reg_req" => { "out" => [ "vfp" ] },
1376 "units" => [ "FPU" ],
1381 "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg",
1382 "reg_req" => { "out" => [ "vfp" ] },
1384 "units" => [ "FPU" ],
1389 "comment" => "virtual fp Load pi: Ld pi -> reg",
1390 "reg_req" => { "out" => [ "vfp" ] },
1392 "units" => [ "FPU" ],
1397 "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg",
1398 "reg_req" => { "out" => [ "vfp" ] },
1400 "units" => [ "FPU" ],
1405 "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg",
1406 "reg_req" => { "out" => [ "vfp" ] },
1408 "units" => [ "FPU" ],
1413 "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg",
1414 "reg_req" => { "out" => [ "vfp" ] },
1416 "units" => [ "FPU" ],
1421 "comment" => "virtual fp Load ld e: Ld ld e -> reg",
1422 "reg_req" => { "out" => [ "vfp" ] },
1424 "units" => [ "FPU" ],
1430 "init_attr" => " set_ia32_ls_mode(res, mode);",
1431 "comment" => "represents a virtual floating point constant",
1432 "reg_req" => { "out" => [ "vfp" ] },
1434 "units" => [ "FPU" ],
1440 "op_flags" => "L|X|Y",
1441 "comment" => "represents a virtual floating point compare",
1442 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] },
1443 "outs" => [ "false", "true", "temp_reg_eax" ],
1445 "units" => [ "FPU" ],
1448 #------------------------------------------------------------------------#
1449 # ___ _____ __ _ _ _ #
1450 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1451 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1452 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1453 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1454 #------------------------------------------------------------------------#
1458 "rd_constructor" => "NONE",
1459 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1461 "emit" => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A3, %A4) -> %D1 */',
1466 "rd_constructor" => "NONE",
1467 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1469 "emit" => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A3, %A4) -> %D1 */',
1474 "rd_constructor" => "NONE",
1475 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1477 "emit" => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A3, %A4) -> %D1 */',
1482 "rd_constructor" => "NONE",
1483 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1485 "emit" => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A3, %A4) -> %D1 */',,
1490 "rd_constructor" => "NONE",
1491 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1493 "emit" => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A3, %A4) -> %D1 */',
1498 "rd_constructor" => "NONE",
1499 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1501 "emit" => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A3, %A4) -> %D1 */',
1506 "rd_constructor" => "NONE",
1508 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1510 "emit" => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A3, %A4) -> %D1 */',
1515 "rd_constructor" => "NONE",
1517 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1519 "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A3, %A4) -> %D1 */',
1524 "rd_constructor" => "NONE",
1525 "comment" => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1527 "emit" => '. fprem1 /* x87 fprem(%A3, %A4) -> %D1 */',
1530 # this node is just here, to keep the simulator running
1531 # we can omit this when a fprem simulation function exists
1534 "rd_constructor" => "NONE",
1535 "comment" => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1537 "emit" => '. fprem1 /* x87 fprem(%A3, %A4) -> %D1 WITH POP */',
1542 "rd_constructor" => "NONE",
1543 "comment" => "x87 fp Div: Div(a, b) = a / b",
1545 "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A3, %A4) -> %D1 */',
1550 "rd_constructor" => "NONE",
1551 "comment" => "x87 fp Div: Div(a, b) = a / b",
1553 "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A3, %A4) -> %D1 */',
1558 "rd_constructor" => "NONE",
1559 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1561 "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A3, %A4) -> %D1 */',
1566 "rd_constructor" => "NONE",
1567 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1569 "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A3, %A4) -> %D1 */',
1574 "rd_constructor" => "NONE",
1575 "comment" => "x87 fp Abs: Abs(a) = |a|",
1577 "emit" => '. fabs /* x87 fabs(%A1) -> %D1 */',
1582 "rd_constructor" => "NONE",
1583 "comment" => "x87 fp Chs: Chs(a) = -a",
1585 "emit" => '. fchs /* x87 fchs(%A1) -> %D1 */',
1590 "rd_constructor" => "NONE",
1591 "comment" => "x87 fp Sin: Sin(a) = sin(a)",
1593 "emit" => '. fsin /* x87 sin(%A1) -> %D1 */',
1598 "rd_constructor" => "NONE",
1599 "comment" => "x87 fp Cos: Cos(a) = cos(a)",
1601 "emit" => '. fcos /* x87 cos(%A1) -> %D1 */',
1606 "rd_constructor" => "NONE",
1607 "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1609 "emit" => '. fsqrt $ /* x87 sqrt(%A1) -> %D1 */',
1612 # x87 Load and Store
1615 "rd_constructor" => "NONE",
1616 "op_flags" => "R|L|F",
1617 "state" => "exc_pinned",
1618 "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1620 "emit" => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */',
1624 "rd_constructor" => "NONE",
1625 "op_flags" => "R|L|F",
1626 "state" => "exc_pinned",
1627 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1629 "emit" => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */',
1634 "rd_constructor" => "NONE",
1635 "op_flags" => "R|L|F",
1636 "state" => "exc_pinned",
1637 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1639 "emit" => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */',
1647 "rd_constructor" => "NONE",
1648 "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1650 "emit" => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */',
1655 "rd_constructor" => "NONE",
1656 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1658 "emit" => '. fist %ia32_emit_am /* integer Store(%A3) -> (%A1) */',
1664 "rd_constructor" => "NONE",
1665 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1667 "emit" => '. fistp %ia32_emit_am /* integer Store(%A3) -> (%A1) and pop */',
1674 "op_flags" => "R|c",
1676 "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
1677 "reg_req" => { "out" => [ "vfp" ] },
1678 "emit" => '. fldz /* x87 0.0 -> %D1 */',
1682 "op_flags" => "R|c",
1684 "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
1685 "reg_req" => { "out" => [ "vfp" ] },
1686 "emit" => '. fld1 /* x87 1.0 -> %D1 */',
1690 "op_flags" => "R|c",
1692 "comment" => "x87 fp Load pi: Ld pi -> reg",
1693 "reg_req" => { "out" => [ "vfp" ] },
1694 "emit" => '. fldpi /* x87 pi -> %D1 */',
1698 "op_flags" => "R|c",
1700 "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
1701 "reg_req" => { "out" => [ "vfp" ] },
1702 "emit" => '. fldln2 /* x87 ln(2) -> %D1 */',
1706 "op_flags" => "R|c",
1708 "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
1709 "reg_req" => { "out" => [ "vfp" ] },
1710 "emit" => '. fldlg2 /* x87 log(2) -> %D1 */',
1714 "op_flags" => "R|c",
1716 "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
1717 "reg_req" => { "out" => [ "vfp" ] },
1718 "emit" => '. fldll2t /* x87 ld(10) -> %D1 */',
1722 "op_flags" => "R|c",
1724 "comment" => "x87 fp Load ld e: Ld ld e -> reg",
1725 "reg_req" => { "out" => [ "vfp" ] },
1726 "emit" => '. fldl2e /* x87 ld(e) -> %D1 */',
1730 "op_flags" => "R|c",
1732 "rd_constructor" => "NONE",
1733 "comment" => "represents a x87 constant",
1734 "reg_req" => { "out" => [ "vfp" ] },
1735 "emit" => '. fld %ia32_emit_adr /* Load fConst into register -> %D1 */',
1739 # Note that it is NEVER allowed to do CSE on these nodes
1740 # Moreover, note the virtual register requierements!
1743 "op_flags" => "R|K",
1744 "comment" => "x87 stack exchange",
1746 "cmp_attr" => "return 1;",
1747 "emit" => '. fxch %X1 /* x87 swap %X1, %X3 */',
1751 "op_flags" => "R|K",
1752 "comment" => "x87 stack push",
1754 "cmp_attr" => "return 1;",
1755 "emit" => '. fld %X1 /* x87 push %X1 */',
1760 "comment" => "x87 stack push",
1761 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1762 "cmp_attr" => "return 1;",
1763 "emit" => '. fld %X1 /* x87 push %X1 */',
1767 "op_flags" => "R|K",
1768 "comment" => "x87 stack pop",
1770 "cmp_attr" => "return 1;",
1771 "emit" => '. fstp %X1 /* x87 pop %X1 */',
1777 "op_flags" => "L|X|Y",
1778 "comment" => "floating point compare",
1783 "op_flags" => "L|X|Y",
1784 "comment" => "floating point compare and pop",
1789 "op_flags" => "L|X|Y",
1790 "comment" => "floating point compare and pop twice",
1795 "op_flags" => "L|X|Y",
1796 "comment" => "floating point compare reverse",
1801 "op_flags" => "L|X|Y",
1802 "comment" => "floating point compare reverse and pop",
1807 "op_flags" => "L|X|Y",
1808 "comment" => "floating point compare reverse and pop twice",