3 # This is the specification for the ia32 assembler Firm-operations
10 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
13 # The node description is done as a perl hash initializer with the
14 # following structure:
19 # op_flags => "N|L|C|X|I|F|Y|H|c|K",
20 # irn_flags => "R|N|I|S"
21 # arity => "0|1|2|3 ... |variable|dynamic|any",
22 # state => "floats|pinned|mem_pinned|exc_pinned",
24 # { type => "type 1", name => "name 1" },
25 # { type => "type 2", name => "name 2" },
28 # comment => "any comment for constructor",
29 # reg_req => { in => [ "reg_class|register" ], out => [ "reg_class|register|in_rX" ] },
30 # cmp_attr => "c source code for comparing node attributes",
31 # emit => "emit code with templates",
32 # attr => "attitional attribute arguments for constructor"
33 # init_attr => "emit attribute initialization template"
34 # rd_constructor => "c source code which constructs an ir_node"
35 # latency => "latency of this operation (can be float)"
38 # ... # (all nodes you need to describe)
40 # ); # close the %nodes initializer
42 # op_flags: flags for the operation, OPTIONAL (default is "N")
43 # the op_flags correspond to the firm irop_flags:
46 # C irop_flag_commutative
47 # X irop_flag_cfopcode
48 # I irop_flag_ip_cfopcode
51 # H irop_flag_highlevel
52 # c irop_flag_constlike
55 # irn_flags: special node flags, OPTIONAL (default is 0)
56 # following irn_flags are supported:
59 # I ignore for register allocation
60 # S modifies stack pointer
62 # state: state of the operation, OPTIONAL (default is "floats")
64 # arity: arity of the operation, MUST NOT BE OMITTED
66 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
67 # are always the first 3 arguments and are always autmatically
69 # If this key is missing the following arguments will be created:
70 # for i = 1 .. arity: ir_node *op_i
73 # outs: if a node defines more than one output, the names of the projections
74 # nodes having outs having automatically the mode mode_T
75 # One can also annotate some flags for each out, additional to irn_flags.
76 # They are separated from name with a colon ':', and concatenated by pipe '|'
77 # Only I and S are available at the moment (same meaning as in irn_flags).
78 # example: [ "frame:I", "stack:I|S", "M" ]
80 # comment: OPTIONAL comment for the node constructor
82 # rd_constructor: for every operation there will be a
83 # new_rd_<arch>_<op-name> function with the arguments from above
84 # which creates the ir_node corresponding to the defined operation
85 # you can either put the complete source code of this function here
87 # This key is OPTIONAL. If omitted, the following constructor will
89 # if (!op_<arch>_<op-name>) assert(0);
93 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
96 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
98 # latency: the latency of the operation, default is 1
102 # 0 - no special type
103 # 1 - caller save (register must be saved by the caller of a function)
104 # 2 - callee save (register must be saved by the called function)
105 # 4 - ignore (do not assign this register)
106 # 8 - emitter can choose an arbitrary register of this class
107 # 16 - the register is a virtual one
108 # 32 - register represents a state
109 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
112 { name => "eax", type => 1 },
113 { name => "edx", type => 1 },
114 { name => "ebx", type => 2 },
115 { name => "ecx", type => 1 },
116 { name => "esi", type => 2 },
117 { name => "edi", type => 2 },
118 { name => "ebp", type => 2 },
119 { name => "esp", type => 4 },
120 { name => "gp_NOREG", type => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
121 { name => "gp_UKNWN", type => 4 | 8 | 16 }, # we need a dummy register for Unknown nodes
122 { mode => "mode_Iu" }
125 { name => "xmm0", type => 1 },
126 { name => "xmm1", type => 1 },
127 { name => "xmm2", type => 1 },
128 { name => "xmm3", type => 1 },
129 { name => "xmm4", type => 1 },
130 { name => "xmm5", type => 1 },
131 { name => "xmm6", type => 1 },
132 { name => "xmm7", type => 1 },
133 { name => "xmm_NOREG", type => 4 | 16 }, # we need a dummy register for NoReg nodes
134 { name => "xmm_UKNWN", type => 4 | 8 | 16}, # we need a dummy register for Unknown nodes
138 { name => "vf0", type => 1 | 16 },
139 { name => "vf1", type => 1 | 16 },
140 { name => "vf2", type => 1 | 16 },
141 { name => "vf3", type => 1 | 16 },
142 { name => "vf4", type => 1 | 16 },
143 { name => "vf5", type => 1 | 16 },
144 { name => "vf6", type => 1 | 16 },
145 { name => "vf7", type => 1 | 16 },
146 { name => "vfp_NOREG", type => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
147 { name => "vfp_UKNWN", type => 4 | 8 | 16 }, # we need a dummy register for Unknown nodes
151 { name => "st0", realname => "st", type => 4 },
152 { name => "st1", realname => "st(1)", type => 4 },
153 { name => "st2", realname => "st(2)", type => 4 },
154 { name => "st3", realname => "st(3)", type => 4 },
155 { name => "st4", realname => "st(4)", type => 4 },
156 { name => "st5", realname => "st(5)", type => 4 },
157 { name => "st6", realname => "st(6)", type => 4 },
158 { name => "st7", realname => "st(7)", type => 4 },
161 fp_cw => [ # the floating point control word
162 { name => "fpcw", type => 4 | 32},
163 { mode => "mode_fpcw" }
166 { name => "eflags", type => 4 },
167 { mode => "mode_Iu" }
170 { name => "fpsw", type => 4 },
171 { mode => "mode_Hu" }
176 CF => { reg => "eflags", bit => 0 },
177 PF => { reg => "eflags", bit => 2 },
178 AF => { reg => "eflags", bit => 4 },
179 ZF => { reg => "eflags", bit => 6 },
180 SF => { reg => "eflags", bit => 7 },
181 TF => { reg => "eflags", bit => 8 },
182 IF => { reg => "eflags", bit => 9 },
183 DF => { reg => "eflags", bit => 10 },
184 OF => { reg => "eflags", bit => 11 },
185 IOPL0 => { reg => "eflags", bit => 12 },
186 IOPL1 => { reg => "eflags", bit => 13 },
187 NT => { reg => "eflags", bit => 14 },
188 RF => { reg => "eflags", bit => 16 },
189 VM => { reg => "eflags", bit => 17 },
190 AC => { reg => "eflags", bit => 18 },
191 VIF => { reg => "eflags", bit => 19 },
192 VIP => { reg => "eflags", bit => 20 },
193 ID => { reg => "eflags", bit => 21 },
195 FP_IE => { reg => "fpsw", bit => 0 },
196 FP_DE => { reg => "fpsw", bit => 1 },
197 FP_ZE => { reg => "fpsw", bit => 2 },
198 FP_OE => { reg => "fpsw", bit => 3 },
199 FP_UE => { reg => "fpsw", bit => 4 },
200 FP_PE => { reg => "fpsw", bit => 5 },
201 FP_SF => { reg => "fpsw", bit => 6 },
202 FP_ES => { reg => "fpsw", bit => 7 },
203 FP_C0 => { reg => "fpsw", bit => 8 },
204 FP_C1 => { reg => "fpsw", bit => 9 },
205 FP_C2 => { reg => "fpsw", bit => 10 },
206 FP_TOP0 => { reg => "fpsw", bit => 11 },
207 FP_TOP1 => { reg => "fpsw", bit => 12 },
208 FP_TOP2 => { reg => "fpsw", bit => 13 },
209 FP_C3 => { reg => "fpsw", bit => 14 },
210 FP_B => { reg => "fpsw", bit => 15 },
212 FP_IM => { reg => "fpcw", bit => 0 },
213 FP_DM => { reg => "fpcw", bit => 1 },
214 FP_ZM => { reg => "fpcw", bit => 2 },
215 FP_OM => { reg => "fpcw", bit => 3 },
216 FP_UM => { reg => "fpcw", bit => 4 },
217 FP_PM => { reg => "fpcw", bit => 5 },
218 FP_PC0 => { reg => "fpcw", bit => 8 },
219 FP_PC1 => { reg => "fpcw", bit => 9 },
220 FP_RC0 => { reg => "fpcw", bit => 10 },
221 FP_RC1 => { reg => "fpcw", bit => 11 },
222 FP_X => { reg => "fpcw", bit => 12 }
226 GP => [ 1, "GP_EAX", "GP_EBX", "GP_ECX", "GP_EDX", "GP_ESI", "GP_EDI", "GP_EBP" ],
227 SSE => [ 1, "SSE_XMM0", "SSE_XMM1", "SSE_XMM2", "SSE_XMM3", "SSE_XMM4", "SSE_XMM5", "SSE_XMM6", "SSE_XMM7" ],
228 VFP => [ 1, "VFP_VF0", "VFP_VF1", "VFP_VF2", "VFP_VF3", "VFP_VF4", "VFP_VF5", "VFP_VF6", "VFP_VF7" ],
229 BRANCH => [ 1, "BRANCH1", "BRANCH2" ],
234 bundels_per_cycle => 1
238 S0 => "${arch}_emit_source_register(env, node, 0);",
239 S1 => "${arch}_emit_source_register(env, node, 1);",
240 S2 => "${arch}_emit_source_register(env, node, 2);",
241 S3 => "${arch}_emit_source_register(env, node, 3);",
242 S4 => "${arch}_emit_source_register(env, node, 4);",
243 S5 => "${arch}_emit_source_register(env, node, 5);",
244 D0 => "${arch}_emit_dest_register(env, node, 0);",
245 D1 => "${arch}_emit_dest_register(env, node, 1);",
246 D2 => "${arch}_emit_dest_register(env, node, 2);",
247 D3 => "${arch}_emit_dest_register(env, node, 3);",
248 D4 => "${arch}_emit_dest_register(env, node, 4);",
249 D5 => "${arch}_emit_dest_register(env, node, 5);",
250 X0 => "${arch}_emit_x87_name(env, node, 0);",
251 X1 => "${arch}_emit_x87_name(env, node, 1);",
252 X2 => "${arch}_emit_x87_name(env, node, 2);",
253 C => "${arch}_emit_immediate(env, node);",
254 SE => "${arch}_emit_extend_suffix(env, get_ia32_ls_mode(node));",
255 ME => "if(get_mode_size_bits(get_ia32_ls_mode(node)) != 32)\n
256 ia32_emit_mode_suffix(env, node);",
257 M => "${arch}_emit_mode_suffix(env, node);",
258 XXM => "${arch}_emit_xmm_mode_suffix(env, node);",
259 XSD => "${arch}_emit_xmm_mode_suffix_s(env, node);",
260 AM => "${arch}_emit_am(env, node);",
261 unop => "${arch}_emit_unop(env, node);",
262 binop => "${arch}_emit_binop(env, node);",
263 x87_binop => "${arch}_emit_x87_binop(env, node);",
266 #--------------------------------------------------#
269 # _ __ _____ __ _ _ __ ___ _ __ ___ #
270 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
271 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
272 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
275 #--------------------------------------------------#
277 $default_cmp_attr = "return ia32_compare_attr(attr_a, attr_b);";
282 $mode_xmm = "mode_E";
283 $mode_gp = "mode_Iu";
284 $mode_fpcw = "mode_fpcw";
285 $status_flags = [ "CF", "PF", "AF", "ZF", "SF", "OF" ];
286 $fpcw_flags = [ "FP_IM", "FP_DM", "FP_ZM", "FP_OM", "FP_UM", "FP_PM",
287 "FP_PC0", "FP_PC1", "FP_RC0", "FP_RC1", "FP_X" ];
291 #-----------------------------------------------------------------#
294 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
295 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
296 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
297 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
300 #-----------------------------------------------------------------#
302 # commutative operations
305 # All nodes supporting Addressmode have 5 INs:
306 # 1 - base r1 == NoReg in case of no AM or no base
307 # 2 - index r2 == NoReg in case of no AM or no index
308 # 3 - op1 r3 == always present
309 # 4 - op2 r4 == NoReg in case of immediate operation
310 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
314 comment => "construct Add: Add(a, b) = Add(b, a) = a + b",
315 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
316 emit => '. add%M %binop',
319 modified_flags => $status_flags
323 comment => "construct Add with Carry: Adc(a, b) = Add(b, a) = a + b + carry",
324 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
325 emit => '. adc%M %binop',
328 modified_flags => $status_flags
333 comment => "construct 64Bit Add: Add(a_l, a_h, b_l, b_h) = a_l + b_l; a_h + b_h + carry",
335 reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
342 outs => [ "low_res", "high_res" ],
344 modified_flags => $status_flags
350 cmp_attr => "return 1;",
351 comment => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
357 cmp_attr => "return 1;",
358 comment => "construct lowered Add with Carry: Adc(a, b) = Adc(b, a) = a + b + carry",
363 # we should not rematrialize this node. It produces 2 results and has
364 # very strict constrains
365 comment => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
366 reg_req => { in => [ "gp", "gp", "eax", "gp", "none" ], out => [ "eax", "edx", "none" ] },
367 emit => '. mul%M %unop',
368 outs => [ "EAX", "EDX", "M" ],
371 modified_flags => $status_flags
375 # we should not rematrialize this node. It produces 2 results and has
376 # very strict constrains
378 cmp_attr => "return 1;",
379 comment => "construct lowered MulS: Mul(a, b) = Mul(b, a) = a * b",
380 outs => [ "EAX", "EDX", "M" ],
386 comment => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
387 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
388 emit => '. imul%M %binop',
392 modified_flags => $status_flags
397 comment => "construct Mul (1 operand format): Mul(a, b) = Mul(b, a) = a * b",
398 reg_req => { in => [ "gp", "gp", "eax", "gp", "none" ], out => [ "eax", "edx", "none" ] },
399 emit => '. imul%M %unop',
400 outs => [ "EAX", "EDX", "M" ],
403 modified_flags => $status_flags
408 cmp_attr => "return 1;",
409 comment => "construct lowered IMul: IMul(a, b) = IMul(b, a) = a * b",
415 comment => "construct And: And(a, b) = And(b, a) = a AND b",
416 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
417 emit => '. and%M %binop',
420 modified_flags => $status_flags
425 comment => "construct Or: Or(a, b) = Or(b, a) = a OR b",
426 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
427 emit => '. or%M %binop',
430 modified_flags => $status_flags
435 comment => "construct Xor: Xor(a, b) = Xor(b, a) = a EOR b",
436 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
437 emit => '. xor%M %binop',
440 modified_flags => $status_flags
445 cmp_attr => "return 1;",
446 comment => "construct lowered Xor: Xor(a, b) = Xor(b, a) = a XOR b",
448 modified_flags => $status_flags
451 # not commutative operations
455 comment => "construct Sub: Sub(a, b) = a - b",
456 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
457 emit => '. sub%M %binop',
460 modified_flags => $status_flags
464 comment => "construct Sub with Carry: SubC(a, b) = a - b - carry",
465 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3 !in_r4" ] },
466 emit => '. sbb%M %binop',
469 modified_flags => $status_flags
474 comment => "construct 64Bit Sub: Sub(a_l, a_h, b_l, b_h) = a_l - b_l; a_h - b_h - borrow",
476 reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
483 outs => [ "low_res", "high_res" ],
485 modified_flags => $status_flags
490 cmp_attr => "return 1;",
491 comment => "construct lowered Sub: Sub(a, b) = a - b",
496 cmp_attr => "return 1;",
497 comment => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
503 state => "exc_pinned",
504 reg_req => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ], out => [ "eax", "edx", "none" ] },
505 attr => "ia32_op_flavour_t dm_flav",
506 init_attr => "attr->data.op_flav = dm_flav;",
507 emit => ". idiv%M %unop",
508 outs => [ "div_res", "mod_res", "M" ],
511 modified_flags => $status_flags
516 state => "exc_pinned",
517 reg_req => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ], out => [ "eax", "edx", "none" ] },
518 attr => "ia32_op_flavour_t dm_flav",
519 init_attr => "attr->data.op_flav = dm_flav;",
520 emit => ". div%M %unop",
521 outs => [ "div_res", "mod_res", "M" ],
524 modified_flags => $status_flags
529 comment => "construct Shl: Shl(a, b) = a << b",
530 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
531 emit => '. shl%M %binop',
534 modified_flags => $status_flags
538 cmp_attr => "return 1;",
539 comment => "construct lowered Shl: Shl(a, b) = a << b",
545 comment => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
546 # Out requirements is: different from all in
547 # This is because, out must be different from LowPart and ShiftCount.
548 # We could say "!ecx !in_r4" but it can occur, that all values live through
549 # this Shift and the only value dying is the ShiftCount. Then there would be a
550 # register missing, as result must not be ecx and all other registers are
551 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
552 # (and probably never will). So we create artificial interferences of the result
553 # with all inputs, so the spiller can always assure a free register.
554 reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
557 if (get_ia32_immop_type(node) == ia32_ImmNone) {
558 if (get_ia32_op_type(node) == ia32_AddrModeD) {
559 . shld%M %%cl, %S3, %AM
561 . shld%M %%cl, %S3, %S2
564 if (get_ia32_op_type(node) == ia32_AddrModeD) {
565 . shld%M %C, %S3, %AM
567 . shld%M %C, %S3, %S2
574 modified_flags => $status_flags
578 cmp_attr => "return 1;",
579 comment => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
585 comment => "construct Shr: Shr(a, b) = a >> b",
586 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
587 emit => '. shr%M %binop',
590 modified_flags => $status_flags
594 cmp_attr => "return 1;",
595 comment => "construct lowered Shr: Shr(a, b) = a << b",
601 comment => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
602 # Out requirements is: different from all in
603 # This is because, out must be different from LowPart and ShiftCount.
604 # We could say "!ecx !in_r4" but it can occur, that all values live through
605 # this Shift and the only value dying is the ShiftCount. Then there would be a
606 # register missing, as result must not be ecx and all other registers are
607 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
608 # (and probably never will). So we create artificial interferences of the result
609 # with all inputs, so the spiller can always assure a free register.
610 reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
612 if (get_ia32_immop_type(node) == ia32_ImmNone) {
613 if (get_ia32_op_type(node) == ia32_AddrModeD) {
614 . shrd%M %%cl, %S3, %AM
616 . shrd%M %%cl, %S3, %S2
619 if (get_ia32_op_type(node) == ia32_AddrModeD) {
620 . shrd%M %C, %S3, %AM
622 . shrd%M %C, %S3, %S2
629 modified_flags => $status_flags
633 cmp_attr => "return 1;",
634 comment => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
640 comment => "construct Shrs: Shrs(a, b) = a >> b",
641 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
642 emit => '. sar%M %binop',
645 modified_flags => $status_flags
649 cmp_attr => "return 1;",
650 comment => "construct lowered Sar: Sar(a, b) = a << b",
656 comment => "construct Ror: Ror(a, b) = a ROR b",
657 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
658 emit => '. ror%M %binop',
661 modified_flags => $status_flags
666 comment => "construct Rol: Rol(a, b) = a ROL b",
667 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
668 emit => '. rol%M %binop',
671 modified_flags => $status_flags
678 comment => "construct Minus: Minus(a) = -a",
679 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
680 emit => '. neg%M %unop',
683 modified_flags => $status_flags
688 comment => "construct 64Bit Minus: Minus(a_l, a_h, 0) = 0 - a_l; 0 - a_h - borrow",
690 reg_req => { in => [ "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
697 outs => [ "low_res", "high_res" ],
699 modified_flags => $status_flags
704 cmp_attr => "return 1;",
705 comment => "construct lowered Minus: Minus(a) = -a",
711 comment => "construct Increment: Inc(a) = a++",
712 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
713 emit => '. inc%M %unop',
716 modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
721 comment => "construct Decrement: Dec(a) = a--",
722 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
723 emit => '. dec%M %unop',
726 modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
731 comment => "construct Not: Not(a) = !a",
732 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
733 emit => '. not%M %unop',
744 comment => "construct conditional jump: CMP A, B && JMPxx LABEL",
745 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ] },
746 outs => [ "false", "true" ],
748 units => [ "BRANCH" ],
754 comment => "construct conditional jump: TEST A, B && JMPxx LABEL",
755 reg_req => { in => [ "gp", "gp" ] },
756 outs => [ "false", "true" ],
758 units => [ "BRANCH" ],
764 comment => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
765 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "none", "none" ] },
766 outs => [ "false", "true" ],
767 units => [ "BRANCH" ],
773 comment => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
774 reg_req => { in => [ "gp", "gp" ] },
775 units => [ "BRANCH" ],
781 comment => "construct switch",
782 reg_req => { in => [ "gp" ], out => [ "none" ] },
784 units => [ "BRANCH" ],
790 comment => "represents an integer constant",
791 reg_req => { out => [ "gp" ] },
800 comment => "unknown value",
801 reg_req => { out => [ "gp_UKNWN" ] },
811 comment => "unknown value",
812 reg_req => { out => [ "vfp_UKNWN" ] },
822 comment => "unknown value",
823 reg_req => { out => [ "xmm_UKNWN" ] },
833 comment => "noreg GP value",
834 reg_req => { out => [ "gp_NOREG" ] },
844 comment => "noreg VFP value",
845 reg_req => { out => [ "vfp_NOREG" ] },
855 comment => "noreg XMM value",
856 reg_req => { out => [ "xmm_NOREG" ] },
866 comment => "change floating point control word",
867 reg_req => { out => [ "fp_cw" ] },
871 modified_flags => $fpcw_flags
876 state => "exc_pinned",
877 comment => "load floating point control word FldCW(ptr, mem) = LD ptr -> reg",
878 reg_req => { in => [ "gp", "gp", "none" ], out => [ "fp_cw" ] },
880 emit => ". fldcw %AM",
883 modified_flags => $fpcw_flags
888 state => "exc_pinned",
889 comment => "store floating point control word: FstCW(ptr, mem) = ST ptr -> reg",
890 reg_req => { in => [ "gp", "gp", "fp_cw", "none" ], out => [ "none" ] },
892 emit => ". fnstcw %AM",
898 # we should not rematrialize this node. It produces 2 results and has
899 # very strict constrains
900 comment => "construct CDQ: sign extend EAX -> EDX:EAX",
901 reg_req => { in => [ "gp" ], out => [ "eax in_r1", "edx" ] },
903 outs => [ "EAX", "EDX" ],
911 state => "exc_pinned",
912 comment => "construct Load: Load(ptr, mem) = LD ptr -> reg",
913 reg_req => { in => [ "gp", "gp", "none" ], out => [ "gp", "none" ] },
915 emit => ". mov%SE%ME%.l %AM, %D0",
916 outs => [ "res", "M" ],
922 cmp_attr => "return 1;",
923 comment => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg",
924 outs => [ "res", "M" ],
930 cmp_attr => "return 1;",
931 state => "exc_pinned",
932 comment => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val",
939 state => "exc_pinned",
940 comment => "construct Store: Store(ptr, val, mem) = ST ptr,val",
941 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "none" ] },
942 emit => '. mov%M %binop',
950 state => "exc_pinned",
951 comment => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
952 reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => ["none" ] },
953 emit => '. mov%M %binop',
961 comment => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
962 reg_req => { in => [ "gp", "gp" ], out => [ "in_r1" ] },
963 emit => '. leal %AM, %D0',
967 modified_flags => [],
971 comment => "push on the stack",
972 reg_req => { in => [ "gp", "gp", "gp", "esp", "none" ], out => [ "esp", "none" ] },
973 emit => '. push%M %unop',
974 outs => [ "stack:I|S", "M" ],
977 modified_flags => [],
981 comment => "pop a gp register from the stack",
982 reg_req => { in => [ "gp", "gp", "esp", "none" ], out => [ "esp", "gp", "none" ] },
983 emit => '. pop%M %unop',
984 outs => [ "stack:I|S", "res", "M" ],
987 modified_flags => [],
991 comment => "create stack frame",
992 reg_req => { in => [ "esp" ], out => [ "ebp", "esp" ] },
994 outs => [ "frame:I", "stack:I|S", "M" ],
1000 comment => "destroy stack frame",
1001 reg_req => { in => [ "esp", "ebp" ], out => [ "ebp", "esp" ] },
1003 outs => [ "frame:I", "stack:I|S" ],
1010 comment => "allocate space on stack",
1011 reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "none" ] },
1012 emit => '. addl %binop',
1013 outs => [ "stack:S", "M" ],
1015 modified_flags => $status_flags
1020 comment => "free space on stack",
1021 reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "none" ] },
1022 emit => '. subl %binop',
1023 outs => [ "stack:S", "M" ],
1025 modified_flags => $status_flags
1030 comment => "get the TLS base address",
1031 reg_req => { out => [ "gp" ] },
1037 #-----------------------------------------------------------------------------#
1038 # _____ _____ ______ __ _ _ _ #
1039 # / ____/ ____| ____| / _| | | | | | #
1040 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1041 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1042 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1043 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1044 #-----------------------------------------------------------------------------#
1046 # commutative operations
1050 comment => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
1051 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1052 emit => '. add%XXM %binop',
1060 comment => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
1061 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1062 emit => '. mul%XXM %binop',
1070 comment => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
1071 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1072 emit => '. max%XXM %binop',
1080 comment => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
1081 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1082 emit => '. min%XXM %binop',
1090 comment => "construct SSE And: And(a, b) = a AND b",
1091 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1092 emit => '. andp%XSD %binop',
1100 comment => "construct SSE Or: Or(a, b) = a OR b",
1101 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1102 emit => '. orp%XSD %binop',
1109 comment => "construct SSE Xor: Xor(a, b) = a XOR b",
1110 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1111 emit => '. xorp%XSD %binop',
1117 # not commutative operations
1121 comment => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
1122 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] },
1123 emit => '. andnp%XSD %binop',
1131 comment => "construct SSE Sub: Sub(a, b) = a - b",
1132 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1133 emit => '. sub%XXM %binop',
1141 comment => "construct SSE Div: Div(a, b) = a / b",
1142 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] },
1143 outs => [ "res", "M" ],
1144 emit => '. div%XXM %binop',
1153 comment => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
1154 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] },
1162 op_flags => "L|X|Y",
1163 comment => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
1164 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "none", "none" ] },
1165 outs => [ "false", "true" ],
1173 comment => "represents a SSE constant",
1174 reg_req => { out => [ "xmm" ] },
1175 emit => '. mov%XXM %C, %D0',
1185 state => "exc_pinned",
1186 comment => "construct SSE Load: Load(ptr, mem) = LD ptr",
1187 reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none" ] },
1188 emit => '. mov%XXM %AM, %D0',
1189 outs => [ "res", "M" ],
1196 state => "exc_pinned",
1197 comment => "construct Store: Store(ptr, val, mem) = ST ptr,val",
1198 reg_req => { in => [ "gp", "gp", "xmm", "none" ] },
1199 emit => '. mov%XXM %binop',
1207 state => "exc_pinned",
1208 comment => "construct Store without index: Store(ptr, val, mem) = ST ptr,val",
1209 reg_req => { in => [ "gp", "xmm", "none" ] },
1210 emit => '. mov%XXM %S1, %AM',
1218 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm" ] },
1219 emit => '. cvtsi2ss %D0, %AM',
1227 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm" ] },
1228 emit => '. cvtsi2sd %unop',
1237 comment => "construct: transfer a value from x87 FPU into a SSE register",
1238 cmp_attr => "return 1;",
1244 comment => "construct: transfer a value from SSE register to x87 FPU",
1245 cmp_attr => "return 1;",
1252 state => "exc_pinned",
1253 comment => "store ST0 onto stack",
1254 reg_req => { in => [ "gp", "gp", "none" ] },
1255 emit => '. fstp%M %AM',
1264 state => "exc_pinned",
1265 comment => "load ST0 from stack",
1266 reg_req => { in => [ "gp", "none" ], out => [ "vf0", "none" ] },
1267 emit => '. fld%M %AM',
1268 outs => [ "res", "M" ],
1278 comment => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
1279 reg_req => { in => [ "edi", "esi", "ecx", "none" ], out => [ "edi", "esi", "ecx", "none" ] },
1280 outs => [ "DST", "SRC", "CNT", "M" ],
1282 modified_flags => [ "DF" ]
1288 comment => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
1289 reg_req => { in => [ "edi", "esi", "none" ], out => [ "edi", "esi", "none" ] },
1290 outs => [ "DST", "SRC", "M" ],
1292 modified_flags => [ "DF" ]
1298 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3", "none" ] },
1299 comment => "construct Conv Int -> Int",
1302 modified_flags => $status_flags
1306 reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => [ "in_r3", "none" ] },
1307 comment => "construct Conv Int -> Int",
1310 modified_flags => $status_flags
1314 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm", "none" ] },
1315 comment => "construct Conv Int -> Floating Point",
1322 reg_req => { in => [ "gp", "gp", "xmm", "none" ], out => [ "gp", "none" ] },
1323 comment => "construct Conv Floating Point -> Int",
1330 reg_req => { in => [ "gp", "gp", "xmm", "none" ], out => [ "xmm", "none" ] },
1331 comment => "construct Conv Floating Point -> Floating Point",
1339 comment => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
1340 reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "in_r4" ] },
1348 comment => "check if Psi condition tree evaluates to true and move result accordingly",
1349 reg_req => { in => [ "gp", "gp", "gp" ], out => [ "in_r3" ] },
1357 comment => "construct Conditional Move: SSE Compare + int CMov ",
1358 reg_req => { in => [ "xmm", "xmm", "gp", "gp" ], out => [ "in_r4" ] },
1366 comment => "construct Conditional Move: x87 Compare + int CMov",
1367 reg_req => { in => [ "vfp", "vfp", "gp", "gp" ], out => [ "in_r4" ] },
1375 comment => "construct Set: Set(sel) == sel ? 1 : 0",
1376 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "eax ebx ecx edx" ] },
1384 comment => "check if Psi condition tree evaluates to true and set result accordingly",
1385 reg_req => { in => [ "gp" ], out => [ "eax ebx ecx edx" ] },
1393 comment => "construct Set: SSE Compare + int Set",
1394 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "eax ebx ecx edx" ] },
1402 comment => "construct Set: x87 Compare + int Set",
1403 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "eax ebx ecx edx" ] },
1411 comment => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
1412 reg_req => { in => [ "vfp", "vfp", "vfp", "vfp" ], out => [ "vfp" ] },
1418 #----------------------------------------------------------#
1420 # (_) | | | | / _| | | | #
1421 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
1422 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
1423 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
1424 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
1426 # _ __ ___ __| | ___ ___ #
1427 # | '_ \ / _ \ / _` |/ _ \/ __| #
1428 # | | | | (_) | (_| | __/\__ \ #
1429 # |_| |_|\___/ \__,_|\___||___/ #
1430 #----------------------------------------------------------#
1434 comment => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
1435 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1443 comment => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1444 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1452 cmp_attr => "return 1;",
1453 comment => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1459 comment => "virtual fp Sub: Sub(a, b) = a - b",
1460 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1467 cmp_attr => "return 1;",
1468 comment => "lowered virtual fp Sub: Sub(a, b) = a - b",
1473 comment => "virtual fp Div: Div(a, b) = a / b",
1474 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1475 outs => [ "res", "M" ],
1481 cmp_attr => "return 1;",
1482 comment => "lowered virtual fp Div: Div(a, b) = a / b",
1483 outs => [ "res", "M" ],
1488 comment => "virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1489 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1496 cmp_attr => "return 1;",
1497 comment => "lowered virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1503 comment => "virtual fp Abs: Abs(a) = |a|",
1504 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1512 comment => "virtual fp Chs: Chs(a) = -a",
1513 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1521 comment => "virtual fp Sin: Sin(a) = sin(a)",
1522 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1530 comment => "virtual fp Cos: Cos(a) = cos(a)",
1531 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1539 comment => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
1540 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1546 # virtual Load and Store
1550 state => "exc_pinned",
1551 comment => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
1552 reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] },
1553 outs => [ "res", "M" ],
1560 state => "exc_pinned",
1561 comment => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
1562 reg_req => { in => [ "gp", "gp", "vfp", "none" ] },
1571 comment => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1572 reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] },
1573 outs => [ "res", "M" ],
1579 cmp_attr => "return 1;",
1580 comment => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1581 outs => [ "res", "M" ],
1586 comment => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1587 reg_req => { in => [ "gp", "gp", "vfp", "fpcw", "none" ] },
1594 cmp_attr => "return 1;",
1595 comment => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1605 comment => "virtual fp Load 0.0: Ld 0.0 -> reg",
1606 reg_req => { out => [ "vfp" ] },
1614 comment => "virtual fp Load 1.0: Ld 1.0 -> reg",
1615 reg_req => { out => [ "vfp" ] },
1623 comment => "virtual fp Load pi: Ld pi -> reg",
1624 reg_req => { out => [ "vfp" ] },
1632 comment => "virtual fp Load ln 2: Ld ln 2 -> reg",
1633 reg_req => { out => [ "vfp" ] },
1641 comment => "virtual fp Load lg 2: Ld lg 2 -> reg",
1642 reg_req => { out => [ "vfp" ] },
1650 comment => "virtual fp Load ld 10: Ld ld 10 -> reg",
1651 reg_req => { out => [ "vfp" ] },
1659 comment => "virtual fp Load ld e: Ld ld e -> reg",
1660 reg_req => { out => [ "vfp" ] },
1669 # init_attr => " set_ia32_ls_mode(res, mode);",
1670 comment => "represents a virtual floating point constant",
1671 reg_req => { out => [ "vfp" ] },
1681 op_flags => "L|X|Y",
1682 comment => "represents a virtual floating point compare",
1683 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "none", "none", "eax" ] },
1684 outs => [ "false", "true", "temp_reg_eax" ],
1689 #------------------------------------------------------------------------#
1690 # ___ _____ __ _ _ _ #
1691 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1692 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1693 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1694 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1695 #------------------------------------------------------------------------#
1697 # Note: gas is strangely buggy: fdivrp and fdivp as well as fsubrp and fsubp
1698 # are swapped, we work this around in the emitter...
1702 rd_constructor => "NONE",
1703 comment => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1705 emit => '. fadd%M %x87_binop',
1710 rd_constructor => "NONE",
1711 comment => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1713 emit => '. faddp %x87_binop',
1718 rd_constructor => "NONE",
1719 comment => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1721 emit => '. fmul%M %x87_binop',
1726 rd_constructor => "NONE",
1727 comment => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1729 emit => '. fmulp %x87_binop',,
1734 rd_constructor => "NONE",
1735 comment => "x87 fp Sub: Sub(a, b) = a - b",
1737 emit => '. fsub%M %x87_binop',
1742 rd_constructor => "NONE",
1743 comment => "x87 fp Sub: Sub(a, b) = a - b",
1745 # see note about gas bugs
1746 emit => '. fsubrp %x87_binop',
1751 rd_constructor => "NONE",
1753 comment => "x87 fp SubR: SubR(a, b) = b - a",
1755 emit => '. fsubr%M %x87_binop',
1760 rd_constructor => "NONE",
1762 comment => "x87 fp SubR: SubR(a, b) = b - a",
1764 # see note about gas bugs
1765 emit => '. fsubp %x87_binop',
1770 rd_constructor => "NONE",
1771 comment => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1776 # this node is just here, to keep the simulator running
1777 # we can omit this when a fprem simulation function exists
1780 rd_constructor => "NONE",
1781 comment => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1788 rd_constructor => "NONE",
1789 comment => "x87 fp Div: Div(a, b) = a / b",
1791 emit => '. fdiv%M %x87_binop',
1796 rd_constructor => "NONE",
1797 comment => "x87 fp Div: Div(a, b) = a / b",
1799 # see note about gas bugs
1800 emit => '. fdivrp %x87_binop',
1805 rd_constructor => "NONE",
1806 comment => "x87 fp DivR: DivR(a, b) = b / a",
1808 emit => '. fdivr%M %x87_binop',
1813 rd_constructor => "NONE",
1814 comment => "x87 fp DivR: DivR(a, b) = b / a",
1816 # see note about gas bugs
1817 emit => '. fdivp %x87_binop',
1822 rd_constructor => "NONE",
1823 comment => "x87 fp Abs: Abs(a) = |a|",
1830 rd_constructor => "NONE",
1831 comment => "x87 fp Chs: Chs(a) = -a",
1838 rd_constructor => "NONE",
1839 comment => "x87 fp Sin: Sin(a) = sin(a)",
1846 rd_constructor => "NONE",
1847 comment => "x87 fp Cos: Cos(a) = cos(a)",
1854 rd_constructor => "NONE",
1855 comment => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1857 emit => '. fsqrt $',
1860 # x87 Load and Store
1863 rd_constructor => "NONE",
1864 op_flags => "R|L|F",
1865 state => "exc_pinned",
1866 comment => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1868 emit => '. fld%M %AM',
1872 rd_constructor => "NONE",
1873 op_flags => "R|L|F",
1874 state => "exc_pinned",
1875 comment => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1877 emit => '. fst%M %AM',
1882 rd_constructor => "NONE",
1883 op_flags => "R|L|F",
1884 state => "exc_pinned",
1885 comment => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1887 emit => '. fstp%M %AM',
1895 rd_constructor => "NONE",
1896 comment => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1898 emit => '. fild%M %AM',
1903 rd_constructor => "NONE",
1904 comment => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1906 emit => '. fist%M %AM',
1912 rd_constructor => "NONE",
1913 comment => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1915 emit => '. fistp%M %AM',
1924 comment => "x87 fp Load 0.0: Ld 0.0 -> reg",
1932 comment => "x87 fp Load 1.0: Ld 1.0 -> reg",
1940 comment => "x87 fp Load pi: Ld pi -> reg",
1948 comment => "x87 fp Load ln 2: Ld ln 2 -> reg",
1956 comment => "x87 fp Load lg 2: Ld lg 2 -> reg",
1964 comment => "x87 fp Load ld 10: Ld ld 10 -> reg",
1966 emit => '. fldll2t',
1972 comment => "x87 fp Load ld e: Ld ld e -> reg",
1978 # Note that it is NEVER allowed to do CSE on these nodes
1979 # Moreover, note the virtual register requierements!
1983 comment => "x87 stack exchange",
1985 cmp_attr => "return 1;",
1986 emit => '. fxch %X0',
1991 comment => "x87 stack push",
1993 cmp_attr => "return 1;",
1994 emit => '. fld %X0',
1999 comment => "x87 stack push",
2000 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
2001 cmp_attr => "return 1;",
2002 emit => '. fld %X0',
2007 comment => "x87 stack pop",
2009 cmp_attr => "return 1;",
2010 emit => '. fstp %X0',
2016 op_flags => "L|X|Y",
2017 comment => "floating point compare",
2022 op_flags => "L|X|Y",
2023 comment => "floating point compare and pop",
2028 op_flags => "L|X|Y",
2029 comment => "floating point compare and pop twice",
2034 op_flags => "L|X|Y",
2035 comment => "floating point compare reverse",
2040 op_flags => "L|X|Y",
2041 comment => "floating point compare reverse and pop",
2046 op_flags => "L|X|Y",
2047 comment => "floating point compare reverse and pop twice",
2052 # -------------------------------------------------------------------------------- #
2053 # ____ ____ _____ _ _ #
2054 # / ___/ ___|| ____| __ _____ ___| |_ ___ _ __ _ __ ___ __| | ___ ___ #
2055 # \___ \___ \| _| \ \ / / _ \/ __| __/ _ \| '__| | '_ \ / _ \ / _` |/ _ \/ __| #
2056 # ___) |__) | |___ \ V / __/ (__| || (_) | | | | | | (_) | (_| | __/\__ \ #
2057 # |____/____/|_____| \_/ \___|\___|\__\___/|_| |_| |_|\___/ \__,_|\___||___/ #
2059 # -------------------------------------------------------------------------------- #
2062 # Spilling and reloading of SSE registers, hardcoded, not generated #
2066 state => "exc_pinned",
2067 comment => "construct SSE Load: Load(ptr, mem) = LD ptr",
2068 reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none" ] },
2069 emit => '. movdqu %D0, %AM',
2070 outs => [ "res", "M" ],
2076 state => "exc_pinned",
2077 comment => "construct Store: Store(ptr, val, mem) = ST ptr,val",
2078 reg_req => { in => [ "gp", "gp", "xmm", "none" ] },
2079 emit => '. movdqu %binop',
2086 # Include the generated SIMD node specification written by the SIMD optimization
2087 $my_script_name = dirname($myname) . "/../ia32/ia32_simd_spec.pl";
2088 unless ($return = do $my_script_name) {
2089 warn "couldn't parse $my_script_name: $@" if $@;
2090 warn "couldn't do $my_script_name: $!" unless defined $return;
2091 warn "couldn't run $my_script_name" unless $return;