3 # This is the specification for the ia32 assembler Firm-operations
7 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
10 # The node description is done as a perl hash initializer with the
11 # following structure:
16 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
17 # "irn_flags" => "R|N|I|S"
18 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
19 # "state" => "floats|pinned|mem_pinned|exc_pinned",
21 # { "type" => "type 1", "name" => "name 1" },
22 # { "type" => "type 2", "name" => "name 2" },
25 # "comment" => "any comment for constructor",
26 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
27 # "cmp_attr" => "c source code for comparing node attributes",
28 # "emit" => "emit code with templates",
29 # "attr" => "attitional attribute arguments for constructor"
30 # "init_attr" => "emit attribute initialization template"
31 # "rd_constructor" => "c source code which constructs an ir_node"
32 # "latency" => "latency of this operation (can be float)"
35 # ... # (all nodes you need to describe)
37 # ); # close the %nodes initializer
39 # op_flags: flags for the operation, OPTIONAL (default is "N")
40 # the op_flags correspond to the firm irop_flags:
43 # C irop_flag_commutative
44 # X irop_flag_cfopcode
45 # I irop_flag_ip_cfopcode
48 # H irop_flag_highlevel
49 # c irop_flag_constlike
52 # irn_flags: special node flags, OPTIONAL (default is 0)
53 # following irn_flags are supported:
56 # I ignore for register allocation
57 # S modifies stack pointer
59 # state: state of the operation, OPTIONAL (default is "floats")
61 # arity: arity of the operation, MUST NOT BE OMITTED
63 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
64 # are always the first 3 arguments and are always autmatically
66 # If this key is missing the following arguments will be created:
67 # for i = 1 .. arity: ir_node *op_i
70 # outs: if a node defines more than one output, the names of the projections
71 # nodes having outs having automatically the mode mode_T
72 # One can also annotate some flags for each out, additional to irn_flags.
73 # They are separated from name with a colon ':', and concatenated by pipe '|'
74 # Only I and S are available at the moment (same meaning as in irn_flags).
75 # example: [ "frame:I", "stack:I|S", "M" ]
77 # comment: OPTIONAL comment for the node constructor
79 # rd_constructor: for every operation there will be a
80 # new_rd_<arch>_<op-name> function with the arguments from above
81 # which creates the ir_node corresponding to the defined operation
82 # you can either put the complete source code of this function here
84 # This key is OPTIONAL. If omitted, the following constructor will
86 # if (!op_<arch>_<op-name>) assert(0);
90 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
93 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
95 # latency: the latency of the operation, default is 1
100 # 1 - caller save (register must be saved by the caller of a function)
101 # 2 - callee save (register must be saved by the called function)
102 # 4 - ignore (do not assign this register)
103 # 8 - emitter can choose an arbitrary register of this class
104 # 16 - the register is a virtual one
105 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
108 { "name" => "eax", "type" => 1 },
109 { "name" => "edx", "type" => 1 },
110 { "name" => "ebx", "type" => 2 },
111 { "name" => "ecx", "type" => 1 },
112 { "name" => "esi", "type" => 2 },
113 { "name" => "edi", "type" => 2 },
114 { "name" => "ebp", "type" => 2 },
115 { "name" => "esp", "type" => 4 },
116 { "name" => "gp_NOREG", "type" => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
117 { "name" => "gp_UKNWN", "type" => 4 | 8 | 16 }, # we need a dummy register for Unknown nodes
118 { "mode" => "mode_Iu" }
121 { "name" => "xmm0", "type" => 1 },
122 { "name" => "xmm1", "type" => 1 },
123 { "name" => "xmm2", "type" => 1 },
124 { "name" => "xmm3", "type" => 1 },
125 { "name" => "xmm4", "type" => 1 },
126 { "name" => "xmm5", "type" => 1 },
127 { "name" => "xmm6", "type" => 1 },
128 { "name" => "xmm7", "type" => 1 },
129 { "name" => "xmm_NOREG", "type" => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
130 { "name" => "xmm_UKNWN", "type" => 4 | 8 | 16 }, # we need a dummy register for Unknown nodes
131 { "mode" => "mode_E" }
134 { "name" => "vf0", "type" => 1 | 16 },
135 { "name" => "vf1", "type" => 1 | 16 },
136 { "name" => "vf2", "type" => 1 | 16 },
137 { "name" => "vf3", "type" => 1 | 16 },
138 { "name" => "vf4", "type" => 1 | 16 },
139 { "name" => "vf5", "type" => 1 | 16 },
140 { "name" => "vf6", "type" => 1 | 16 },
141 { "name" => "vf7", "type" => 1 | 16 },
142 { "name" => "vfp_NOREG", "type" => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
143 { "name" => "vfp_UKNWN", "type" => 4 | 8 | 16 }, # we need a dummy register for Unknown nodes
144 { "mode" => "mode_E" }
147 { "name" => "st0", "type" => 1 },
148 { "name" => "st1", "type" => 1 },
149 { "name" => "st2", "type" => 1 },
150 { "name" => "st3", "type" => 1 },
151 { "name" => "st4", "type" => 1 },
152 { "name" => "st5", "type" => 1 },
153 { "name" => "st6", "type" => 1 },
154 { "name" => "st7", "type" => 1 },
155 { "mode" => "mode_E" }
157 "fp_cw" => [ # the floating point control word
158 { "name" => "fpcw", "type" => 0 },
159 { "mode" => "mode_Hu" },
164 "GP" => [ 1, "GP_EAX", "GP_EBX", "GP_ECX", "GP_EDX", "GP_ESI", "GP_EDI", "GP_EBP" ],
165 "SSE" => [ 1, "SSE_XMM0", "SSE_XMM1", "SSE_XMM2", "SSE_XMM3", "SSE_XMM4", "SSE_XMM5", "SSE_XMM6", "SSE_XMM7" ],
166 "VFP" => [ 1, "VFP_VF0", "VFP_VF1", "VFP_VF2", "VFP_VF3", "VFP_VF4", "VFP_VF5", "VFP_VF6", "VFP_VF7" ],
167 "BRANCH" => [ 1, "BRANCH1", "BRANCH2" ],
172 "bundels_per_cycle" => 1
176 "S1" => "${arch}_emit_source_register(env, node, 0);",
177 "S2" => "${arch}_emit_source_register(env, node, 1);",
178 "S3" => "${arch}_emit_source_register(env, node, 2);",
179 "S4" => "${arch}_emit_source_register(env, node, 3);",
180 "S5" => "${arch}_emit_source_register(env, node, 4);",
181 "S6" => "${arch}_emit_source_register(env, node, 5);",
182 "D1" => "${arch}_emit_dest_register(env, node, 0);",
183 "D2" => "${arch}_emit_dest_register(env, node, 1);",
184 "D3" => "${arch}_emit_dest_register(env, node, 2);",
185 "D4" => "${arch}_emit_dest_register(env, node, 3);",
186 "D5" => "${arch}_emit_dest_register(env, node, 4);",
187 "D6" => "${arch}_emit_dest_register(env, node, 5);",
188 "A1" => "${arch}_emit_in_node_name(env, node, 0);",
189 "A2" => "${arch}_emit_in_node_name(env, node, 1);",
190 "A3" => "${arch}_emit_in_node_name(env, node, 2);",
191 "A4" => "${arch}_emit_in_node_name(env, node, 3);",
192 "A5" => "${arch}_emit_in_node_name(env, node, 4);",
193 "A6" => "${arch}_emit_in_node_name(env, node, 5);",
194 "X1" => "${arch}_emit_x87_name(env, node, 0);",
195 "X2" => "${arch}_emit_x87_name(env, node, 1);",
196 "X3" => "${arch}_emit_x87_name(env, node, 2);",
197 "C" => "${arch}_emit_immediate(env, node);",
198 "SE" => "${arch}_emit_extend_suffix(env, get_ia32_ls_mode(node));",
199 "ME" => "if(get_mode_size_bits(get_ia32_ls_mode(node)) != 32)\n
200 ${arch}_emit_mode_suffix(env, get_ia32_ls_mode(node));",
201 "M" => "${arch}_emit_mode_suffix(env, get_ia32_ls_mode(node));",
202 "XM" => "${arch}_emit_x87_mode_suffix(env, node);",
203 "XXM" => "${arch}_emit_xmm_mode_suffix(env, node);",
204 "XSD" => "${arch}_emit_xmm_mode_suffix_s(env, node);",
205 "AM" => "${arch}_emit_am(env, node);",
206 "unop" => "${arch}_emit_unop(env, node);",
207 "binop" => "${arch}_emit_binop(env, node);",
208 "x87_binop" => "${arch}_emit_x87_binop(env, node);",
211 #--------------------------------------------------#
214 # _ __ _____ __ _ _ __ ___ _ __ ___ #
215 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
216 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
217 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
220 #--------------------------------------------------#
222 $default_cmp_attr = "return ia32_compare_attr(attr_a, attr_b);";
229 #-----------------------------------------------------------------#
232 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
233 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
234 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
235 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
238 #-----------------------------------------------------------------#
240 # commutative operations
243 # All nodes supporting Addressmode have 5 INs:
244 # 1 - base r1 == NoReg in case of no AM or no base
245 # 2 - index r2 == NoReg in case of no AM or no index
246 # 3 - op1 r3 == always present
247 # 4 - op2 r4 == NoReg in case of immediate operation
248 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
252 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
253 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
254 "emit" => '. addl %binop',
260 "comment" => "construct Add with Carry: Adc(a, b) = Add(b, a) = a + b + carry",
261 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
262 "emit" => '. adcl %binop',
269 "comment" => "construct 64Bit Add: Add(a_l, a_h, b_l, b_h) = a_l + b_l; a_h + b_h + carry",
271 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
278 "outs" => [ "low_res", "high_res" ],
285 "cmp_attr" => "return 1;",
286 "comment" => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
292 "cmp_attr" => "return 1;",
293 "comment" => "construct lowered Add with Carry: Adc(a, b) = Adc(b, a) = a + b + carry",
298 # we should not rematrialize this node. It produces 2 results and has
299 # very strict constrains
300 "comment" => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
301 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx", "none" ] },
302 "emit" => '. mull %unop',
303 "outs" => [ "EAX", "EDX", "M" ],
309 # we should not rematrialize this node. It produces 2 results and has
310 # very strict constrains
312 "cmp_attr" => "return 1;",
313 "comment" => "construct lowered MulS: Mul(a, b) = Mul(b, a) = a * b",
314 "outs" => [ "EAX", "EDX", "M" ],
320 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
321 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
322 "emit" => '. imull %binop',
330 "comment" => "construct Mul (1 operand format): Mul(a, b) = Mul(b, a) = a * b",
331 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx", "none" ] },
332 "emit" => '. imull %unop',
333 "outs" => [ "EAX", "EDX", "M" ],
340 "cmp_attr" => "return 1;",
341 "comment" => "construct lowered IMul: IMul(a, b) = IMul(b, a) = a * b",
347 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
348 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
349 "emit" => '. andl %binop',
356 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
357 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
358 "emit" => '. orl %binop',
365 "comment" => "construct Xor: Xor(a, b) = Xor(b, a) = a EOR b",
366 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
367 "emit" => '. xorl %binop',
374 "cmp_attr" => "return 1;",
375 "comment" => "construct lowered Xor: Xor(a, b) = Xor(b, a) = a XOR b",
379 # not commutative operations
383 "comment" => "construct Sub: Sub(a, b) = a - b",
384 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
385 "emit" => '. subl %binop',
391 "comment" => "construct Sub with Carry: SubC(a, b) = a - b - carry",
392 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3 !in_r4" ] },
393 "emit" => '. sbbl %binop',
400 "comment" => "construct 64Bit Sub: Sub(a_l, a_h, b_l, b_h) = a_l - b_l; a_h - b_h - borrow",
402 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
409 "outs" => [ "low_res", "high_res" ],
415 "cmp_attr" => "return 1;",
416 "comment" => "construct lowered Sub: Sub(a, b) = a - b",
421 "cmp_attr" => "return 1;",
422 "comment" => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
428 "state" => "exc_pinned",
429 "reg_req" => { "in" => [ "gp", "gp", "eax", "edx", "gp", "none" ], "out" => [ "eax", "edx", "none" ] },
430 "attr" => "ia32_op_flavour_t dm_flav",
431 "init_attr" => "attr->data.op_flav = dm_flav;",
432 "emit" => ". idivl %unop",
433 "outs" => [ "div_res", "mod_res", "M" ],
440 "state" => "exc_pinned",
441 "reg_req" => { "in" => [ "gp", "gp", "eax", "edx", "gp", "none" ], "out" => [ "eax", "edx", "none" ] },
442 "attr" => "ia32_op_flavour_t dm_flav",
443 "init_attr" => "attr->data.op_flav = dm_flav;",
444 "emit" => ". divl %unop",
445 "outs" => [ "div_res", "mod_res", "M" ],
452 "comment" => "construct Shl: Shl(a, b) = a << b",
453 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
454 "emit" => '. shll %binop',
460 "cmp_attr" => "return 1;",
461 "comment" => "construct lowered Shl: Shl(a, b) = a << b",
467 "comment" => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
468 # Out requirements is: different from all in
469 # This is because, out must be different from LowPart and ShiftCount.
470 # We could say "!ecx !in_r4" but it can occur, that all values live through
471 # this Shift and the only value dying is the ShiftCount. Then there would be a
472 # register missing, as result must not be ecx and all other registers are
473 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
474 # (and probably never will). So we create artificial interferences of the result
475 # with all inputs, so the spiller can always assure a free register.
476 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!in" ] },
479 if (get_ia32_immop_type(node) == ia32_ImmNone) {
480 if (get_ia32_op_type(node) == ia32_AddrModeD) {
481 . shldl %%cl, %S4, %AM
483 . shldl %%cl, %S4, %S3
486 if (get_ia32_op_type(node) == ia32_AddrModeD) {
487 . shldl $%C, %S4, %AM
489 . shldl $%C, %S4, %S3
499 "cmp_attr" => "return 1;",
500 "comment" => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
506 "comment" => "construct Shr: Shr(a, b) = a >> b",
507 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
508 "emit" => '. shrl %binop',
514 "cmp_attr" => "return 1;",
515 "comment" => "construct lowered Shr: Shr(a, b) = a << b",
521 "comment" => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
522 # Out requirements is: different from all in
523 # This is because, out must be different from LowPart and ShiftCount.
524 # We could say "!ecx !in_r4" but it can occur, that all values live through
525 # this Shift and the only value dying is the ShiftCount. Then there would be a
526 # register missing, as result must not be ecx and all other registers are
527 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
528 # (and probably never will). So we create artificial interferences of the result
529 # with all inputs, so the spiller can always assure a free register.
530 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!in" ] },
532 if (get_ia32_immop_type(node) == ia32_ImmNone) {
533 if (get_ia32_op_type(node) == ia32_AddrModeD) {
534 . shrdl %%cl, %S4, %AM
536 . shrdl %%cl, %S4, %S3
539 if (get_ia32_op_type(node) == ia32_AddrModeD) {
540 . shrdl $%C, %S4, %AM
542 . shrdl $%C, %S4, %S3
552 "cmp_attr" => "return 1;",
553 "comment" => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
559 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
560 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
561 "emit" => '. sarl %binop',
567 "cmp_attr" => "return 1;",
568 "comment" => "construct lowered Sar: Sar(a, b) = a << b",
574 "comment" => "construct Ror: Ror(a, b) = a ROR b",
575 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
576 "emit" => '. rorl %binop',
583 "comment" => "construct Rol: Rol(a, b) = a ROL b",
584 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
585 "emit" => '. roll %binop',
594 "comment" => "construct Minus: Minus(a) = -a",
595 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
596 "emit" => '. negl %unop',
603 "comment" => "construct 64Bit Minus: Minus(a_l, a_h, 0) = 0 - a_l; 0 - a_h - borrow",
605 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
612 "outs" => [ "low_res", "high_res" ],
618 "cmp_attr" => "return 1;",
619 "comment" => "construct lowered Minus: Minus(a) = -a",
625 "comment" => "construct Increment: Inc(a) = a++",
626 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
627 "emit" => '. incl %unop',
634 "comment" => "construct Decrement: Dec(a) = a--",
635 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
636 "emit" => '. decl %unop',
643 "comment" => "construct Not: Not(a) = !a",
644 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
645 "emit" => '. notl %unop',
653 "op_flags" => "L|X|Y",
654 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
655 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
656 "outs" => [ "false", "true" ],
658 "units" => [ "BRANCH" ],
662 "op_flags" => "L|X|Y",
663 "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
664 "reg_req" => { "in" => [ "gp", "gp" ] },
665 "outs" => [ "false", "true" ],
667 "units" => [ "BRANCH" ],
671 "op_flags" => "L|X|Y",
672 "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
673 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
674 "outs" => [ "false", "true" ],
675 "units" => [ "BRANCH" ],
679 "op_flags" => "L|X|Y",
680 "comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
681 "reg_req" => { "in" => [ "gp", "gp" ] },
682 "units" => [ "BRANCH" ],
686 "op_flags" => "L|X|Y",
687 "comment" => "construct switch",
688 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
690 "units" => [ "BRANCH" ],
696 "comment" => "represents an integer constant",
697 "reg_req" => { "out" => [ "gp" ] },
705 "comment" => "unknown value",
706 "reg_req" => { "out" => [ "gp_UKNWN" ] },
715 "comment" => "unknown value",
716 "reg_req" => { "out" => [ "vfp_UKNWN" ] },
725 "comment" => "unknown value",
726 "reg_req" => { "out" => [ "xmm_UKNWN" ] },
735 "comment" => "unknown GP value",
736 "reg_req" => { "out" => [ "gp_NOREG" ] },
745 "comment" => "unknown VFP value",
746 "reg_req" => { "out" => [ "vfp_NOREG" ] },
755 "comment" => "unknown XMM value",
756 "reg_req" => { "out" => [ "xmm_NOREG" ] },
764 "comment" => "change floating point control word",
765 "reg_req" => { "out" => [ "fp_cw" ] },
773 "state" => "exc_pinned",
774 "comment" => "load floating point control word FldCW(ptr, mem) = LD ptr -> reg",
775 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "fp_cw" ] },
777 "emit" => ". fldcw %AM",
784 "state" => "exc_pinned",
785 "comment" => "store floating point control word: FstCW(ptr, mem) = ST ptr -> reg",
786 "reg_req" => { "in" => [ "gp", "gp", "fp_cw", "none" ] },
788 "emit" => ". fstcw %AM",
794 # we should not rematrialize this node. It produces 2 results and has
795 # very strict constrains
796 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
797 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
799 "outs" => [ "EAX", "EDX" ],
807 "state" => "exc_pinned",
808 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
809 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp", "none" ] },
811 "emit" => ". mov%SE%ME%.l %AM, %D1",
812 "outs" => [ "res", "M" ],
818 "cmp_attr" => "return 1;",
819 "comment" => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg",
820 "outs" => [ "res", "M" ],
826 "cmp_attr" => "return 1;",
827 "state" => "exc_pinned",
828 "comment" => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val",
835 "state" => "exc_pinned",
836 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
837 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
838 "emit" => '. mov%M %binop',
846 "state" => "exc_pinned",
847 "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
848 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
849 "emit" => '. mov%M %binop',
857 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
858 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
859 "emit" => '. leal %AM, %D1',
866 "comment" => "push on the stack",
867 "reg_req" => { "in" => [ "gp", "gp", "gp", "esp", "none" ], "out" => [ "esp", "none" ] },
868 "emit" => '. pushl %unop',
869 "outs" => [ "stack:I|S", "M" ],
875 "comment" => "pop a gp register from the stack",
876 "reg_req" => { "in" => [ "gp", "gp", "esp", "none" ], "out" => [ "esp", "gp", "none" ] },
877 "emit" => '. popl %unop',
878 "outs" => [ "stack:I|S", "res", "M" ],
884 "comment" => "create stack frame",
885 "reg_req" => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] },
887 "outs" => [ "frame:I", "stack:I|S", "M" ],
893 "comment" => "destroy stack frame",
894 "reg_req" => { "in" => [ "esp", "ebp" ], "out" => [ "ebp", "esp" ] },
896 "outs" => [ "frame:I", "stack:I|S" ],
903 "comment" => "allocate space on stack",
904 "reg_req" => { "in" => [ "gp", "gp", "esp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
905 "emit" => '. addl %binop',
906 "outs" => [ "stack:S", "M" ],
912 "comment" => "free space on stack",
913 "reg_req" => { "in" => [ "gp", "gp", "esp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
914 "emit" => '. subl %binop',
915 "outs" => [ "stack:S", "M" ],
921 "comment" => "get the TLS base address",
922 "reg_req" => { "out" => [ "gp" ] },
928 #-----------------------------------------------------------------------------#
929 # _____ _____ ______ __ _ _ _ #
930 # / ____/ ____| ____| / _| | | | | | #
931 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
932 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
933 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
934 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
935 #-----------------------------------------------------------------------------#
937 # commutative operations
941 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
942 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
943 "emit" => '. add%XXM %binop',
945 "units" => [ "SSE" ],
951 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
952 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
953 "emit" => '. mul%XXM %binop',
955 "units" => [ "SSE" ],
961 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
962 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
963 "emit" => '. max%XXM %binop',
965 "units" => [ "SSE" ],
971 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
972 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
973 "emit" => '. min%XXM %binop',
975 "units" => [ "SSE" ],
981 "comment" => "construct SSE And: And(a, b) = a AND b",
982 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
983 "emit" => '. andp%XSD %binop',
985 "units" => [ "SSE" ],
991 "comment" => "construct SSE Or: Or(a, b) = a OR b",
992 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
993 "emit" => '. orp%XSD %binop',
994 "units" => [ "SSE" ],
1000 "comment" => "construct SSE Xor: Xor(a, b) = a XOR b",
1001 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
1002 "emit" => '. xorp%XSD %binop',
1004 "units" => [ "SSE" ],
1008 # not commutative operations
1012 "comment" => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
1013 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
1014 "emit" => '. andnp%XSD %binop',
1016 "units" => [ "SSE" ],
1022 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
1023 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
1024 "emit" => '. sub%XXM %binop',
1026 "units" => [ "SSE" ],
1032 "comment" => "construct SSE Div: Div(a, b) = a / b",
1033 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
1034 "outs" => [ "res", "M" ],
1035 "emit" => '. div%XXM %binop',
1037 "units" => [ "SSE" ],
1044 "comment" => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
1045 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
1047 "units" => [ "SSE" ],
1052 "op_flags" => "L|X|Y",
1053 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
1054 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
1055 "outs" => [ "false", "true" ],
1057 "units" => [ "SSE" ],
1063 "comment" => "represents a SSE constant",
1064 "reg_req" => { "out" => [ "xmm" ] },
1065 "emit" => '. mov%XXM $%C, %D1',
1067 "units" => [ "SSE" ],
1074 "op_flags" => "L|F",
1075 "state" => "exc_pinned",
1076 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
1077 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
1078 "emit" => '. mov%XXM %AM, %D1',
1079 "outs" => [ "res", "M" ],
1081 "units" => [ "SSE" ],
1085 "op_flags" => "L|F",
1086 "state" => "exc_pinned",
1087 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
1088 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
1089 "emit" => '. mov%XXM %binop',
1091 "units" => [ "SSE" ],
1096 "op_flags" => "L|F",
1097 "state" => "exc_pinned",
1098 "comment" => "construct Store without index: Store(ptr, val, mem) = ST ptr,val",
1099 "reg_req" => { "in" => [ "gp", "xmm", "none" ] },
1100 "emit" => '. mov%XXM %S2, %AM',
1102 "units" => [ "SSE" ],
1107 "op_flags" => "L|F",
1108 "comment" => "construct: transfer a value from x87 FPU into a SSE register",
1109 "cmp_attr" => "return 1;",
1114 "op_flags" => "L|F",
1115 "comment" => "construct: transfer a value from SSE register to x87 FPU",
1116 "cmp_attr" => "return 1;",
1121 "op_flags" => "L|F",
1123 "state" => "exc_pinned",
1124 "comment" => "store ST0 onto stack",
1125 "reg_req" => { "in" => [ "gp", "gp", "none" ] },
1126 "emit" => '. fstp%XM %AM',
1128 "units" => [ "SSE" ],
1133 "op_flags" => "L|F",
1135 "state" => "exc_pinned",
1136 "comment" => "load ST0 from stack",
1137 "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "vf0", "none" ] },
1138 "emit" => '. fld%M %AM',
1139 "outs" => [ "res", "M" ],
1141 "units" => [ "SSE" ],
1147 "op_flags" => "F|H",
1148 "state" => "pinned",
1149 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
1150 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "edi", "esi", "ecx", "none" ] },
1151 "outs" => [ "DST", "SRC", "CNT", "M" ],
1152 "units" => [ "GP" ],
1156 "op_flags" => "F|H",
1157 "state" => "pinned",
1158 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
1159 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "edi", "esi", "none" ] },
1160 "outs" => [ "DST", "SRC", "M" ],
1161 "units" => [ "GP" ],
1167 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
1168 "comment" => "construct Conv Int -> Int",
1169 "units" => [ "GP" ],
1170 "mode" => "mode_Iu",
1174 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
1175 "comment" => "construct Conv Int -> Int",
1176 "units" => [ "GP" ],
1177 "mode" => "mode_Iu",
1181 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
1182 "comment" => "construct Conv Int -> Floating Point",
1184 "units" => [ "SSE" ],
1189 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
1190 "comment" => "construct Conv Floating Point -> Int",
1192 "units" => [ "SSE" ],
1193 "mode" => "mode_Iu",
1197 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
1198 "comment" => "construct Conv Floating Point -> Floating Point",
1200 "units" => [ "SSE" ],
1206 "comment" => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
1207 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "in_r4" ] },
1209 "units" => [ "GP" ],
1210 "mode" => "mode_Iu",
1215 "comment" => "check if Psi condition tree evaluates to true and move result accordingly",
1216 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r3" ] },
1218 "units" => [ "GP" ],
1219 "mode" => "mode_Iu",
1224 "comment" => "construct Conditional Move: SSE Compare + int CMov ",
1225 "reg_req" => { "in" => [ "xmm", "xmm", "gp", "gp" ], "out" => [ "in_r4" ] },
1227 "units" => [ "SSE" ],
1228 "mode" => "mode_Iu",
1233 "comment" => "construct Conditional Move: x87 Compare + int CMov",
1234 "reg_req" => { "in" => [ "vfp", "vfp", "gp", "gp" ], "out" => [ "in_r4" ] },
1236 "units" => [ "VFP" ],
1237 "mode" => "mode_Iu",
1242 "comment" => "construct Set: Set(sel) == sel ? 1 : 0",
1243 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax ebx ecx edx" ] },
1245 "units" => [ "GP" ],
1246 "mode" => "mode_Iu",
1251 "comment" => "check if Psi condition tree evaluates to true and set result accordingly",
1252 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax ebx ecx edx" ] },
1254 "units" => [ "GP" ],
1255 "mode" => "mode_Iu",
1260 "comment" => "construct Set: SSE Compare + int Set",
1261 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "eax ebx ecx edx" ] },
1263 "units" => [ "SSE" ],
1264 "mode" => "mode_Iu",
1269 "comment" => "construct Set: x87 Compare + int Set",
1270 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "eax ebx ecx edx" ] },
1272 "units" => [ "VFP" ],
1273 "mode" => "mode_Iu",
1278 "comment" => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
1279 "reg_req" => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] },
1281 "units" => [ "VFP" ],
1285 #----------------------------------------------------------#
1287 # (_) | | | | / _| | | | #
1288 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
1289 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
1290 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
1291 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
1293 # _ __ ___ __| | ___ ___ #
1294 # | '_ \ / _ \ / _` |/ _ \/ __| #
1295 # | | | | (_) | (_| | __/\__ \ #
1296 # |_| |_|\___/ \__,_|\___||___/ #
1297 #----------------------------------------------------------#
1301 "comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
1302 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1304 "units" => [ "VFP" ],
1310 "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1311 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1313 "units" => [ "VFP" ],
1319 "cmp_attr" => "return 1;",
1320 "comment" => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1326 "comment" => "virtual fp Sub: Sub(a, b) = a - b",
1327 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1329 "units" => [ "VFP" ],
1334 "cmp_attr" => "return 1;",
1335 "comment" => "lowered virtual fp Sub: Sub(a, b) = a - b",
1340 "comment" => "virtual fp Div: Div(a, b) = a / b",
1341 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1342 "outs" => [ "res", "M" ],
1344 "units" => [ "VFP" ],
1348 "cmp_attr" => "return 1;",
1349 "comment" => "lowered virtual fp Div: Div(a, b) = a / b",
1350 "outs" => [ "res", "M" ],
1355 "comment" => "virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1356 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1358 "units" => [ "VFP" ],
1363 "cmp_attr" => "return 1;",
1364 "comment" => "lowered virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1370 "comment" => "virtual fp Abs: Abs(a) = |a|",
1371 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1373 "units" => [ "VFP" ],
1379 "comment" => "virtual fp Chs: Chs(a) = -a",
1380 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1382 "units" => [ "VFP" ],
1388 "comment" => "virtual fp Sin: Sin(a) = sin(a)",
1389 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1391 "units" => [ "VFP" ],
1397 "comment" => "virtual fp Cos: Cos(a) = cos(a)",
1398 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1400 "units" => [ "VFP" ],
1406 "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
1407 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1409 "units" => [ "VFP" ],
1413 # virtual Load and Store
1416 "op_flags" => "L|F",
1417 "state" => "exc_pinned",
1418 "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
1419 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1420 "outs" => [ "res", "M" ],
1422 "units" => [ "VFP" ],
1426 "op_flags" => "L|F",
1427 "state" => "exc_pinned",
1428 "comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
1429 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1431 "units" => [ "VFP" ],
1438 "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1439 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1440 "outs" => [ "res", "M" ],
1442 "units" => [ "VFP" ],
1446 "cmp_attr" => "return 1;",
1447 "comment" => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1448 "outs" => [ "res", "M" ],
1453 "comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1454 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1456 "units" => [ "VFP" ],
1461 "cmp_attr" => "return 1;",
1462 "comment" => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1472 "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg",
1473 "reg_req" => { "out" => [ "vfp" ] },
1475 "units" => [ "VFP" ],
1481 "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg",
1482 "reg_req" => { "out" => [ "vfp" ] },
1484 "units" => [ "VFP" ],
1490 "comment" => "virtual fp Load pi: Ld pi -> reg",
1491 "reg_req" => { "out" => [ "vfp" ] },
1493 "units" => [ "VFP" ],
1499 "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg",
1500 "reg_req" => { "out" => [ "vfp" ] },
1502 "units" => [ "VFP" ],
1508 "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg",
1509 "reg_req" => { "out" => [ "vfp" ] },
1511 "units" => [ "VFP" ],
1517 "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg",
1518 "reg_req" => { "out" => [ "vfp" ] },
1520 "units" => [ "VFP" ],
1526 "comment" => "virtual fp Load ld e: Ld ld e -> reg",
1527 "reg_req" => { "out" => [ "vfp" ] },
1529 "units" => [ "VFP" ],
1536 # "init_attr" => " set_ia32_ls_mode(res, mode);",
1537 "comment" => "represents a virtual floating point constant",
1538 "reg_req" => { "out" => [ "vfp" ] },
1540 "units" => [ "VFP" ],
1547 "op_flags" => "L|X|Y",
1548 "comment" => "represents a virtual floating point compare",
1549 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] },
1550 "outs" => [ "false", "true", "temp_reg_eax" ],
1552 "units" => [ "VFP" ],
1555 #------------------------------------------------------------------------#
1556 # ___ _____ __ _ _ _ #
1557 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1558 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1559 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1560 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1561 #------------------------------------------------------------------------#
1563 # Note: gas is strangely buggy: fdivrp and fdivp as well as fsubrp and fsubp
1564 # are swapped, we work this around in the emitter...
1568 "rd_constructor" => "NONE",
1569 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1571 "emit" => '. fadd%XM %x87_binop',
1576 "rd_constructor" => "NONE",
1577 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1579 "emit" => '. faddp %x87_binop',
1584 "rd_constructor" => "NONE",
1585 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1587 "emit" => '. fmul%XM %x87_binop',
1592 "rd_constructor" => "NONE",
1593 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1595 "emit" => '. fmulp %x87_binop',,
1600 "rd_constructor" => "NONE",
1601 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1603 "emit" => '. fsub%XM %x87_binop',
1608 "rd_constructor" => "NONE",
1609 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1611 # see note about gas bugs
1612 "emit" => '. fsubrp %x87_binop',
1617 "rd_constructor" => "NONE",
1619 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1621 "emit" => '. fsubr%XM %x87_binop',
1626 "rd_constructor" => "NONE",
1628 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1630 # see note about gas bugs
1631 "emit" => '. fsubp %x87_binop',
1636 "rd_constructor" => "NONE",
1637 "comment" => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1639 "emit" => '. fprem1',
1642 # this node is just here, to keep the simulator running
1643 # we can omit this when a fprem simulation function exists
1646 "rd_constructor" => "NONE",
1647 "comment" => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1649 "emit" => '. fprem1',
1654 "rd_constructor" => "NONE",
1655 "comment" => "x87 fp Div: Div(a, b) = a / b",
1657 "emit" => '. fdiv%XM %x87_binop',
1662 "rd_constructor" => "NONE",
1663 "comment" => "x87 fp Div: Div(a, b) = a / b",
1665 # see note about gas bugs
1666 "emit" => '. fdivrp %x87_binop',
1671 "rd_constructor" => "NONE",
1672 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1674 "emit" => '. fdivr%XM %x87_binop',
1679 "rd_constructor" => "NONE",
1680 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1682 # see note about gas bugs
1683 "emit" => '. fdivp %x87_binop',
1688 "rd_constructor" => "NONE",
1689 "comment" => "x87 fp Abs: Abs(a) = |a|",
1696 "rd_constructor" => "NONE",
1697 "comment" => "x87 fp Chs: Chs(a) = -a",
1704 "rd_constructor" => "NONE",
1705 "comment" => "x87 fp Sin: Sin(a) = sin(a)",
1712 "rd_constructor" => "NONE",
1713 "comment" => "x87 fp Cos: Cos(a) = cos(a)",
1720 "rd_constructor" => "NONE",
1721 "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1723 "emit" => '. fsqrt $',
1726 # x87 Load and Store
1729 "rd_constructor" => "NONE",
1730 "op_flags" => "R|L|F",
1731 "state" => "exc_pinned",
1732 "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1734 "emit" => '. fld%XM %AM',
1738 "rd_constructor" => "NONE",
1739 "op_flags" => "R|L|F",
1740 "state" => "exc_pinned",
1741 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1743 "emit" => '. fst%XM %AM',
1748 "rd_constructor" => "NONE",
1749 "op_flags" => "R|L|F",
1750 "state" => "exc_pinned",
1751 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1753 "emit" => '. fstp%XM %AM',
1761 "rd_constructor" => "NONE",
1762 "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1764 "emit" => '. fild%XM %AM',
1769 "rd_constructor" => "NONE",
1770 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1772 "emit" => '. fist%M %AM',
1778 "rd_constructor" => "NONE",
1779 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1781 "emit" => '. fistp%M %AM',
1788 "op_flags" => "R|c",
1790 "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
1796 "op_flags" => "R|c",
1798 "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
1804 "op_flags" => "R|c",
1806 "comment" => "x87 fp Load pi: Ld pi -> reg",
1808 "emit" => '. fldpi',
1812 "op_flags" => "R|c",
1814 "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
1816 "emit" => '. fldln2',
1820 "op_flags" => "R|c",
1822 "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
1824 "emit" => '. fldlg2',
1828 "op_flags" => "R|c",
1830 "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
1832 "emit" => '. fldll2t',
1836 "op_flags" => "R|c",
1838 "comment" => "x87 fp Load ld e: Ld ld e -> reg",
1840 "emit" => '. fldl2e',
1844 # Note that it is NEVER allowed to do CSE on these nodes
1845 # Moreover, note the virtual register requierements!
1848 "op_flags" => "R|K",
1849 "comment" => "x87 stack exchange",
1851 "cmp_attr" => "return 1;",
1852 "emit" => '. fxch %X1',
1856 "op_flags" => "R|K",
1857 "comment" => "x87 stack push",
1859 "cmp_attr" => "return 1;",
1860 "emit" => '. fld %X1',
1865 "comment" => "x87 stack push",
1866 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1867 "cmp_attr" => "return 1;",
1868 "emit" => '. fld %X1',
1872 "op_flags" => "R|K",
1873 "comment" => "x87 stack pop",
1875 "cmp_attr" => "return 1;",
1876 "emit" => '. fstp %X1',
1882 "op_flags" => "L|X|Y",
1883 "comment" => "floating point compare",
1888 "op_flags" => "L|X|Y",
1889 "comment" => "floating point compare and pop",
1894 "op_flags" => "L|X|Y",
1895 "comment" => "floating point compare and pop twice",
1900 "op_flags" => "L|X|Y",
1901 "comment" => "floating point compare reverse",
1906 "op_flags" => "L|X|Y",
1907 "comment" => "floating point compare reverse and pop",
1912 "op_flags" => "L|X|Y",
1913 "comment" => "floating point compare reverse and pop twice",