3 # This is the specification for the ia32 assembler Firm-operations
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
9 # The node description is done as a perl hash initializer with the
10 # following structure:
15 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
16 # "irn_flags" => "R|N|I"
17 # "arity" => "0|1|2|3 ... |variable|dynamic|all",
18 # "state" => "floats|pinned",
20 # { "type" => "type 1", "name" => "name 1" },
21 # { "type" => "type 2", "name" => "name 2" },
24 # "comment" => "any comment for constructor",
25 # "emit" => "emit code with templates",
26 # "rd_constructor" => "c source code which constructs an ir_node"
29 # ... # (all nodes you need to describe)
31 # ); # close the %nodes initializer
33 # op_flags: flags for the operation, OPTIONAL (default is "N")
34 # the op_flags correspond to the firm irop_flags:
37 # C irop_flag_commutative
38 # X irop_flag_cfopcode
39 # I irop_flag_ip_cfopcode
42 # H irop_flag_highlevel
43 # c irop_flag_constlike
46 # irn_flags: special node flags, OPTIONAL (default is 0)
47 # following irn_flags are supported:
50 # I ignore for register allocation
52 # state: state of the operation, OPTIONAL (default is "pinned")
54 # arity: arity of the operation, MUST NOT BE OMITTED
56 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
57 # are always the first 3 arguments and are always autmatically
59 # If this key is missing the following arguments will be created:
60 # for i = 1 .. arity: ir_node *op_i
63 # comment: OPTIONAL comment for the node constructor
65 # rd_constructor: for every operation there will be a
66 # new_rd_<arch>_<op-name> function with the arguments from above
67 # which creates the ir_node corresponding to the defined operation
68 # you can either put the complete source code of this function here
70 # This key is OPTIONAL. If omitted, the following constructor will
72 # if (!op_<arch>_<op-name>) assert(0);
76 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
79 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
83 # 1 - caller save (register must be saved by the caller of a function)
84 # 2 - callee save (register must be saved by the called function)
85 # 4 - ignore (do not assign this register)
86 # NOTE: Make sure to list the registers returning the call-result before all other
87 # caller save registers and in the correct order, otherwise it will break
89 # Last entry of each class is the largest Firm-Mode a register can hold
92 { "name" => "eax", "type" => 1 },
93 { "name" => "edx", "type" => 1 },
94 { "name" => "ebx", "type" => 2 },
95 { "name" => "ecx", "type" => 1 },
96 { "name" => "esi", "type" => 2 },
97 { "name" => "edi", "type" => 2 },
98 { "name" => "ebp", "type" => 2 },
99 { "name" => "esp", "type" => 6 },
100 { "name" => "xxx", "type" => 6 }, # we need a dummy register for NoReg and Unknown nodes
101 { "mode" => "mode_P" }
104 { "name" => "xmm0", "type" => 1 },
105 { "name" => "xmm1", "type" => 1 },
106 { "name" => "xmm2", "type" => 1 },
107 { "name" => "xmm3", "type" => 1 },
108 { "name" => "xmm4", "type" => 1 },
109 { "name" => "xmm5", "type" => 1 },
110 { "name" => "xmm6", "type" => 1 },
111 { "name" => "xmm7", "type" => 1 },
112 { "name" => "xxxx", "type" => 4 }, # we need a dummy register for NoReg and Unknown nodes
113 { "mode" => "mode_D" }
117 #--------------------------------------------------#
120 # _ __ _____ __ _ _ __ ___ _ __ ___ #
121 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
122 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
123 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
126 #--------------------------------------------------#
130 #-----------------------------------------------------------------#
133 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
134 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
135 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
136 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
139 #-----------------------------------------------------------------#
141 # commutative operations
144 # All nodes supporting Addressmode have 5 INs:
145 # 1 - base r1 == NoReg in case of no AM or no base
146 # 2 - index r2 == NoReg in case of no AM or no index
147 # 3 - op1 r3 == always present
148 # 4 - op2 r4 == NoReg in case of immediate operation
149 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
153 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
154 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
155 "emit" => '. add %ia32_emit_binop\t\t\t/* Add(%A1, %A2) -> %D1 */'
160 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
161 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
162 "emit" => '. imul %ia32_emit_binop\t\t\t/* Mul(%A1, %A2) -> %D1 */'
165 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
167 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
168 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r1", "edx in_r2" ] },
169 "emit" => '. imul %ia32_emit_unop\t\t\t/* Mulh(%A1, %A2) -> %D1 */ '
174 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
175 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
176 "emit" => '. and %ia32_emit_binop\t\t\t/* And(%A1, %A2) -> %D1 */'
181 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
182 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
183 "emit" => '. or %ia32_emit_binop\t\t\t/* Or(%A1, %A2) -> %D1 */'
188 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
189 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
190 "emit" => '. xor %ia32_emit_binop\t\t\t/* Xor(%A1, %A2) -> %D1 */'
195 "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
196 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
198 '2. cmp %S1, %S2\t\t\t/* prepare Max (%S1 - %S2), (%A1, %A2) */
199 if (mode_is_signed(get_irn_mode(n))) {
200 4. cmovl %D1, %S2\t\t\t/* %S1 is less %S2 */
203 4. cmovb %D1, %S2\t\t\t/* %S1 is below %S2 */
210 "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
211 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
213 '2. cmp %S1, %S2\t\t\t/* prepare Min (%S1 - %S2), (%A1, %A2) */
214 if (mode_is_signed(get_irn_mode(n))) {
215 2. cmovg %D1, %S2\t\t\t/* %S1 is greater %S2 */
218 2. cmova %D1, %S2, %D1\t\t\t/* %S1 is above %S2 */
223 # not commutative operations
227 "comment" => "construct Sub: Sub(a, b) = a - b",
228 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
229 "emit" => '. sub %ia32_emit_binop\t\t\t/* Sub(%A1, %A2) -> %D1 */'
234 "state" => "exc_pinned",
235 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "eax in_r1", "edx in_r3" ] },
237 ' if (mode_is_signed(get_irn_mode(n))) {
238 4. idiv %S2\t\t\t/* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
241 4. div %S2\t\t\t/* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
248 "comment" => "construct Shl: Shl(a, b) = a << b",
249 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r1" ] },
250 "emit" => '. shl %ia32_emit_binop\t\t\t/* Shl(%A1, %A2) -> %D1 */'
255 "comment" => "construct Shr: Shr(a, b) = a >> b",
256 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r1" ] },
257 "emit" => '. shr %ia32_emit_binop\t\t\t/* Shr(%A1, %A2) -> %D1 */'
262 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
263 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r1" ] },
264 "emit" => '. sar %ia32_emit_binop\t\t\t/* Shrs(%A1, %A2) -> %D1 */'
269 "comment" => "construct RotR: RotR(a, b) = a ROTR b",
270 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r1" ] },
271 "emit" => '. ror %ia32_emit_binop\t\t\t/* RotR(%A1, %A2) -> %D1 */'
276 "comment" => "construct RotL: RotL(a, b) = a ROTL b",
277 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r1" ] },
278 "emit" => '. rol %ia32_emit_binop\t\t\t/* RotL(%A1, %A2) -> %D1 */'
285 "comment" => "construct Minus: Minus(a) = -a",
286 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
287 "emit" => '. neg %ia32_emit_unop\t\t\t/* Neg(%A1) -> %D1, (%A1) */'
292 "comment" => "construct Increment: Inc(a) = a++",
293 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
294 "emit" => '. inc %ia32_emit_unop\t\t\t/* Inc(%S1) -> %D1, (%A1) */'
299 "comment" => "construct Decrement: Dec(a) = a--",
300 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
301 "emit" => '. dec %ia32_emit_unop\t\t\t/* Dec(%S1) -> %D1, (%A1) */'
306 "comment" => "construct Not: Not(a) = !a",
307 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
308 "emit" => '. not %ia32_emit_unop\t\t\t/* Not(%S1) -> %D1, (%A1) */'
315 "reg_req" => { "in" => [ "gp" ], "out" => [ "in_r1" ] },
316 "comment" => "construct Conv: Conv(a) = (conv)a"
320 "op_flags" => "L|X|Y",
321 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
322 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
326 "op_flags" => "L|X|Y",
327 "comment" => "construct switch",
328 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "none" ] },
334 "comment" => "represents an integer constant",
335 "reg_req" => { "out" => [ "gp" ] },
336 "emit" => '. mov %D1, %C\t\t\t/* Mov Const into register */',
339 if (attr_a->tp == attr_b->tp) {
340 if (attr_a->tp == ia32_SymConst) {
341 if (attr_a->sc == NULL || attr_b->sc == NULL)
344 return strcmp(attr_a->sc, attr_b->sc);
347 if (attr_a->tv == NULL || attr_b->tv == NULL)
350 if (tarval_cmp(attr_a->tv, attr_b->tv) == pn_Cmp_Eq)
363 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
364 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
365 "emit" => '. cdq\t\t\t/* sign extend EAX -> EDX:EAX, (%A1) */'
373 "state" => "exc_pinned",
374 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
375 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
376 "emit" => '. mov %D1, %ia32_emit_am\t\t\t/* Load((%A1)) -> %D1 */'
381 "state" => "exc_pinned",
382 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
383 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
384 "emit" => '. mov %ia32_emit_am, %S3\t\t\t/* Store(%A2) -> (%A1) */'
389 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
390 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
391 "emit" => '. lea %D1, %ia32_emit_am\t\t/* %D1 = %S1 + %S2 << %C + %O, (%A1, %A2) */'
397 "comment" => "constructs a Stack Parameter to retrieve a parameter from Stack",
398 "reg_req" => { "in" => [ "none" ], "out" => [ "gp" ] },
401 return (attr_a->pn_code != attr_b->pn_code);
407 "comment" => "constructs a Stack Argument to pass an argument on Stack",
408 "reg_req" => { "in" => [ "none", "gp" ], "out" => [ "none" ] },
411 return (attr_a->pn_code != attr_b->pn_code);
415 #--------------------------------------------------------#
418 # | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
419 # | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
420 # | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
421 # |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
422 #--------------------------------------------------------#
424 # commutative operations
428 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
429 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r1" ] },
430 "emit" => '. adds%M %ia32_emit_binop\t\t\t/* SSE Add(%A1, %A2) -> %D1 */'
435 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
436 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
437 "emit" => '. muls%M %ia32_emit_binop\t\t\t/* SSE Mul(%A1, %A2) -> %D1 */'
442 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
443 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
444 "emit" => '. maxs%M %ia32_emit_binop\t\t\t/* SSE Max(%A1, %A2) -> %D1 */'
449 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
450 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
451 "emit" => '. mins%M %ia32_emit_binop\t\t\t/* SSE Min(%A1, %A2) -> %D1 */'
456 "comment" => "construct SSE And: And(a, b) = a AND b",
457 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
458 "emit" => '. andp%M %ia32_emit_binop\t\t\t/* SSE And(%A3, %A4) -> %D1 */'
463 "comment" => "construct SSE Or: Or(a, b) = a OR b",
464 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
465 "emit" => '. orp%M %ia32_emit_binop\t\t\t/* SSE Or(%A3, %A4) -> %D1 */'
470 "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
471 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
472 "emit" => '. xorp%M %ia32_emit_binop\t\t\t/* SSE Xor(%A3, %A4) -> %D1 */'
475 # not commutative operations
479 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
480 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r1" ] },
481 "emit" => '. subs%M %ia32_emit_binop\t\t\t/* SSE Sub(%A1, %A2) -> %D1 */'
486 "comment" => "construct SSE Div: Div(a, b) = a / b",
487 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r1" ] },
488 "emit" => '. divs%M %ia32_emit_binop\t\t\t/* SSE Div(%A1, %A2) -> %D1 */'
495 "reg_req" => { "in" => [ "fp" ], "out" => [ "gp" ] },
496 "comment" => "construct Conv: Conv(a) = (conv)a"
500 "op_flags" => "L|X|Y",
501 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
502 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "none", "none" ] },
508 "comment" => "represents a SSE constant",
509 "reg_req" => { "out" => [ "fp" ] },
510 "emit" => '. mov%M %D1, %C\t\t\t/* Load fConst into register */',
513 if (attr_a->tp == attr_b->tp) {
514 if (attr_a->tp == ia32_SymConst) {
515 if (attr_a->sc == NULL || attr_b->sc == NULL)
518 return strcmp(attr_a->sc, attr_b->sc);
521 if (attr_a->tv == NULL || attr_b->tv == NULL)
524 if (tarval_cmp(attr_a->tv, attr_b->tv) == pn_Cmp_Eq)
540 "state" => "exc_pinned",
541 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
542 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "fp" ] },
543 "emit" => '. movs%M %D1, %ia32_emit_am\t\t\t/* Load((%A1)) -> %D1 */'
548 "state" => "exc_pinned",
549 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
550 "reg_req" => { "in" => [ "gp", "gp", "fp", "none" ] },
551 "emit" => '. movs%M %ia32_emit_am, %S3\t\t\t/* Store(%S3) -> (%A1) */'
557 "comment" => "constructs a Stack Parameter to retrieve a SSE parameter from Stack",
558 "reg_req" => { "in" => [ "none" ], "out" => [ "fp" ] },
561 return (attr_a->pn_code != attr_b->pn_code);
567 "comment" => "constructs a Stack Argument to pass an argument on Stack",
568 "reg_req" => { "in" => [ "none", "fp" ], "out" => [ "none" ] },
571 return (attr_a->pn_code != attr_b->pn_code);
579 "state" => "mem_pinned",
580 "arity" => "variable",
581 "comment" => "construct Call: Call(...)",
583 { "type" => "int", "name" => "n" },
584 { "type" => "ir_node **", "name" => "in" }
587 " if (!op_ia32_Call) assert(0);
588 return new_ir_node(db, irg, block, op_ia32_Call, mode_T, n, in);
597 "arity" => "variable",
598 "comment" => "construct Return: Return(...)",
600 { "type" => "int", "name" => "n" },
601 { "type" => "ir_node **", "name" => "in" }
604 " if (!op_ia32_Return) assert(0);
605 return new_ir_node(db, irg, block, op_ia32_Return, mode_X, n, in);
615 "comment" => "construct Alloca: allocate memory on Stack",
616 "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] }