3 # This is the specification for the ia32 assembler Firm-operations
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
8 # this string marks the beginning of a comment in emit
9 $comment_string = "/*";
11 # the number of additional opcodes you want to register
12 #$additional_opcodes = 0;
14 # The node description is done as a perl hash initializer with the
15 # following structure:
20 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
21 # "irn_flags" => "R|N|I|S"
22 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
23 # "state" => "floats|pinned|mem_pinned|exc_pinned",
25 # { "type" => "type 1", "name" => "name 1" },
26 # { "type" => "type 2", "name" => "name 2" },
29 # "comment" => "any comment for constructor",
30 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
31 # "cmp_attr" => "c source code for comparing node attributes",
32 # "emit" => "emit code with templates",
33 # "attr" => "attitional attribute arguments for constructor"
34 # "init_attr" => "emit attribute initialization template"
35 # "rd_constructor" => "c source code which constructs an ir_node"
36 # "latency" => "latency of this operation (can be float)"
39 # ... # (all nodes you need to describe)
41 # ); # close the %nodes initializer
43 # op_flags: flags for the operation, OPTIONAL (default is "N")
44 # the op_flags correspond to the firm irop_flags:
47 # C irop_flag_commutative
48 # X irop_flag_cfopcode
49 # I irop_flag_ip_cfopcode
52 # H irop_flag_highlevel
53 # c irop_flag_constlike
56 # irn_flags: special node flags, OPTIONAL (default is 0)
57 # following irn_flags are supported:
60 # I ignore for register allocation
61 # S modifies stack pointer
63 # state: state of the operation, OPTIONAL (default is "floats")
65 # arity: arity of the operation, MUST NOT BE OMITTED
67 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
68 # are always the first 3 arguments and are always autmatically
70 # If this key is missing the following arguments will be created:
71 # for i = 1 .. arity: ir_node *op_i
74 # outs: if a node defines more than one output, the names of the projections
75 # nodes having outs having automatically the mode mode_T
76 # One can also annotate some flags for each out, additional to irn_flags.
77 # They are separated from name with a colon ':', and concatenated by pipe '|'
78 # Only I and S are available at the moment (same meaning as in irn_flags).
79 # example: [ "frame:I", "stack:I|S", "M" ]
81 # comment: OPTIONAL comment for the node constructor
83 # rd_constructor: for every operation there will be a
84 # new_rd_<arch>_<op-name> function with the arguments from above
85 # which creates the ir_node corresponding to the defined operation
86 # you can either put the complete source code of this function here
88 # This key is OPTIONAL. If omitted, the following constructor will
90 # if (!op_<arch>_<op-name>) assert(0);
94 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
97 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
99 # latency: the latency of the operation, default is 1
103 # 0 - no special type
104 # 1 - caller save (register must be saved by the caller of a function)
105 # 2 - callee save (register must be saved by the called function)
106 # 4 - ignore (do not assign this register)
107 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
110 { "name" => "eax", "type" => 1 },
111 { "name" => "edx", "type" => 1 },
112 { "name" => "ebx", "type" => 2 },
113 { "name" => "ecx", "type" => 1 },
114 { "name" => "esi", "type" => 2 },
115 { "name" => "edi", "type" => 2 },
116 # { "name" => "r11", "type" => 1 },
117 # { "name" => "r12", "type" => 1 },
118 # { "name" => "r13", "type" => 1 },
119 # { "name" => "r14", "type" => 1 },
120 # { "name" => "r15", "type" => 1 },
121 # { "name" => "r16", "type" => 1 },
122 # { "name" => "r17", "type" => 1 },
123 # { "name" => "r18", "type" => 1 },
124 # { "name" => "r19", "type" => 1 },
125 # { "name" => "r20", "type" => 1 },
126 # { "name" => "r21", "type" => 1 },
127 # { "name" => "r22", "type" => 1 },
128 # { "name" => "r23", "type" => 1 },
129 # { "name" => "r24", "type" => 1 },
130 # { "name" => "r25", "type" => 1 },
131 # { "name" => "r26", "type" => 1 },
132 # { "name" => "r27", "type" => 1 },
133 # { "name" => "r28", "type" => 1 },
134 # { "name" => "r29", "type" => 1 },
135 # { "name" => "r30", "type" => 1 },
136 # { "name" => "r31", "type" => 1 },
137 # { "name" => "r32", "type" => 1 },
138 { "name" => "ebp", "type" => 2 },
139 { "name" => "esp", "type" => 4 },
140 { "name" => "gp_NOREG", "type" => 2 | 4 }, # we need a dummy register for NoReg nodes
141 { "name" => "gp_UKNWN", "type" => 2 | 4 | 8 }, # we need a dummy register for Unknown nodes
142 { "mode" => "mode_P" }
145 { "name" => "xmm0", "type" => 1 },
146 { "name" => "xmm1", "type" => 1 },
147 { "name" => "xmm2", "type" => 1 },
148 { "name" => "xmm3", "type" => 1 },
149 { "name" => "xmm4", "type" => 1 },
150 { "name" => "xmm5", "type" => 1 },
151 { "name" => "xmm6", "type" => 1 },
152 { "name" => "xmm7", "type" => 1 },
153 { "name" => "xmm_NOREG", "type" => 2 | 4 }, # we need a dummy register for NoReg nodes
154 { "name" => "xmm_UKNWN", "type" => 2 | 4 | 8 }, # we need a dummy register for Unknown nodes
155 { "mode" => "mode_D" }
158 { "name" => "vf0", "type" => 1 },
159 { "name" => "vf1", "type" => 1 },
160 { "name" => "vf2", "type" => 1 },
161 { "name" => "vf3", "type" => 1 },
162 { "name" => "vf4", "type" => 1 },
163 { "name" => "vf5", "type" => 1 },
164 { "name" => "vf6", "type" => 1 },
165 { "name" => "vf7", "type" => 1 },
166 { "name" => "vfp_NOREG", "type" => 2 | 4 }, # we need a dummy register for NoReg nodes
167 { "name" => "vfp_UKNWN", "type" => 2 | 4 | 8 }, # we need a dummy register for Unknown nodes
168 { "mode" => "mode_E" }
171 { "name" => "st0", "type" => 1 },
172 { "name" => "st1", "type" => 1 },
173 { "name" => "st2", "type" => 1 },
174 { "name" => "st3", "type" => 1 },
175 { "name" => "st4", "type" => 1 },
176 { "name" => "st5", "type" => 1 },
177 { "name" => "st6", "type" => 1 },
178 { "name" => "st7", "type" => 1 },
179 { "mode" => "mode_E" }
183 #--------------------------------------------------#
186 # _ __ _____ __ _ _ __ ___ _ __ ___ #
187 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
188 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
189 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
192 #--------------------------------------------------#
199 #-----------------------------------------------------------------#
202 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
203 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
204 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
205 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
208 #-----------------------------------------------------------------#
210 # commutative operations
213 # All nodes supporting Addressmode have 5 INs:
214 # 1 - base r1 == NoReg in case of no AM or no base
215 # 2 - index r2 == NoReg in case of no AM or no index
216 # 3 - op1 r3 == always present
217 # 4 - op2 r4 == NoReg in case of immediate operation
218 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
222 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
223 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
224 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
225 "emit" => '. add %ia32_emit_binop /* Add(%A3, %A4) -> %D1 */',
226 "outs" => [ "res", "M" ],
230 "comment" => "construct Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
231 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
232 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
233 "emit" => '. adc %ia32_emit_binop /* AddC(%A3, %A4) -> %D1 */',
234 "outs" => [ "res", "M" ],
240 "cmp_attr" => " return 1;\n",
241 "comment" => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
247 "cmp_attr" => " return 1;\n",
248 "comment" => "construct lowered Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
253 # we should not rematrialize this node. It produces 2 results and has
254 # very strict constrains
255 "comment" => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
256 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
257 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] },
258 "emit" => '. mul %ia32_emit_unop /* Mul(%A1, %A2) -> %D1 */',
259 "outs" => [ "EAX", "EDX", "M" ],
264 # we should not rematrialize this node. It produces 2 results and has
265 # very strict constrains
267 "cmp_attr" => " return 1;\n",
268 "comment" => "construct lowered MulS: MulS(a, b) = MulS(b, a) = a * b",
269 "outs" => [ "EAX", "EDX", "M" ],
275 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
276 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
277 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
278 "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */',
279 "outs" => [ "res", "M" ],
285 "cmp_attr" => " return 1;\n",
286 "comment" => "construct lowered Mul: Mul(a, b) = Mul(b, a) = a * b",
290 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
292 # we should not rematrialize this node. It produces 2 results and has
293 # very strict constrains
294 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
295 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
296 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] },
297 "emit" => '. imul %ia32_emit_unop /* Mulh(%A1, %A2) -> %D1 */',
298 "outs" => [ "EAX", "EDX", "M" ],
304 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
305 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
306 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
307 "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */',
308 "outs" => [ "res", "M" ],
313 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
314 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
315 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
316 "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */',
317 "outs" => [ "res", "M" ],
322 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
323 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
324 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
325 "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */',
326 "outs" => [ "res", "M" ],
331 "cmp_attr" => " return 1;\n",
332 "comment" => "construct lowered Eor: Eor(a, b) = Eor(b, a) = a EOR b",
338 "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
339 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
341 '2. cmp %S1, %S2 /* prepare Max (%S1 - %S2), (%A1, %A2) */
342 if (mode_is_signed(get_irn_mode(n))) {
343 4. cmovl %D1, %S2 /* %S1 is less %S2 */
346 4. cmovb %D1, %S2 /* %S1 is below %S2 */
354 "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
355 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
357 '2. cmp %S1, %S2 /* prepare Min (%S1 - %S2), (%A1, %A2) */
358 if (mode_is_signed(get_irn_mode(n))) {
359 2. cmovg %D1, %S2 /* %S1 is greater %S2 */
362 2. cmova %D1, %S2, %D1 /* %S1 is above %S2 */
368 # not commutative operations
372 "comment" => "construct Sub: Sub(a, b) = a - b",
373 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
374 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
375 "emit" => '. sub %ia32_emit_binop /* Sub(%A3, %A4) -> %D1 */',
376 "outs" => [ "res", "M" ],
380 "comment" => "construct Sub with Carry: SubC(a, b) = a - b - carry",
381 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
382 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3 !in_r4" ] },
383 "emit" => '. sbb %ia32_emit_binop /* SubC(%A3, %A4) -> %D1 */',
384 "outs" => [ "res", "M" ],
389 "cmp_attr" => " return 1;\n",
390 "comment" => "construct lowered Sub: Sub(a, b) = a - b",
395 "cmp_attr" => " return 1;\n",
396 "comment" => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
402 "state" => "exc_pinned",
403 "reg_req" => { "in" => [ "eax", "gp", "edx", "none" ], "out" => [ "eax", "edx" ] },
404 "attr" => "ia32_op_flavour_t dm_flav",
405 "init_attr" => " attr->data.op_flav = dm_flav;",
406 "cmp_attr" => " return attr_a->data.op_flav != attr_b->data.op_flav;\n",
408 ' if (mode_is_signed(get_ia32_res_mode(n))) {
409 4. idiv %S2 /* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
412 4. div %S2 /* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
415 "outs" => [ "div_res", "mod_res", "M" ],
421 "comment" => "construct Shl: Shl(a, b) = a << b",
422 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
423 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx gp_NOREG", "none" ], "out" => [ "in_r3 !in_r4" ] },
424 "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */',
425 "outs" => [ "res", "M" ],
429 "cmp_attr" => " return 1;\n",
430 "comment" => "construct lowered Shl: Shl(a, b) = a << b",
436 "comment" => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
437 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
438 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!ecx in_r3 !in_r4" ] },
441 if (get_ia32_immop_type(n) == ia32_ImmNone) {
442 if (get_ia32_op_type(n) == ia32_AddrModeD) {
443 4. shld %ia32_emit_am, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
446 4. shld %S3, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
450 if (get_ia32_op_type(n) == ia32_AddrModeD) {
451 4. shld %ia32_emit_am, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
454 4. shld %S3, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
458 "outs" => [ "res", "M" ],
463 "cmp_attr" => " return 1;\n",
464 "comment" => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
470 "comment" => "construct Shr: Shr(a, b) = a >> b",
471 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
472 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx gp_NOREG", "none" ], "out" => [ "in_r3 !in_r4" ] },
473 "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */',
474 "outs" => [ "res", "M" ],
478 "cmp_attr" => " return 1;\n",
479 "comment" => "construct lowered Shr: Shr(a, b) = a << b",
485 "comment" => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
486 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
487 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!ecx in_r3 !in_r4" ] },
490 if (get_ia32_immop_type(n) == ia32_ImmNone) {
491 if (get_ia32_op_type(n) == ia32_AddrModeD) {
492 4. shrd %ia32_emit_am, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
495 4. shrd %S3, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
499 if (get_ia32_op_type(n) == ia32_AddrModeD) {
500 4. shrd %ia32_emit_am, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
503 4. shrd %S3, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
507 "outs" => [ "res", "M" ],
512 "cmp_attr" => " return 1;\n",
513 "comment" => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
519 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
520 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
521 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx gp_NOREG", "none" ], "out" => [ "in_r3 !in_r4" ] },
522 "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */',
523 "outs" => [ "res", "M" ],
527 "cmp_attr" => " return 1;\n",
528 "comment" => "construct lowered Shrs: Shrs(a, b) = a << b",
534 "comment" => "construct RotR: RotR(a, b) = a ROTR b",
535 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
536 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
537 "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */',
538 "outs" => [ "res", "M" ],
543 "comment" => "construct RotL: RotL(a, b) = a ROTL b",
544 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
545 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
546 "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */',
547 "outs" => [ "res", "M" ],
554 "comment" => "construct Minus: Minus(a) = -a",
555 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
556 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
557 "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */',
558 "outs" => [ "res", "M" ],
562 "cmp_attr" => " return 1;\n",
563 "comment" => "construct lowered Minus: Minus(a) = -a",
569 "comment" => "construct Increment: Inc(a) = a++",
570 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
571 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
572 "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */',
573 "outs" => [ "res", "M" ],
578 "comment" => "construct Decrement: Dec(a) = a--",
579 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
580 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
581 "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */',
582 "outs" => [ "res", "M" ],
587 "comment" => "construct Not: Not(a) = !a",
588 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
589 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
590 "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */',
591 "outs" => [ "res", "M" ],
597 "op_flags" => "L|X|Y",
598 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
599 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
600 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
601 "outs" => [ "false", "true" ],
606 "op_flags" => "L|X|Y",
607 "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
608 "reg_req" => { "in" => [ "gp", "gp" ] },
609 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
610 "outs" => [ "false", "true" ],
615 "op_flags" => "L|X|Y",
616 "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
617 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
618 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
619 "outs" => [ "false", "true" ],
623 "op_flags" => "L|X|Y",
624 "comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
625 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
626 "reg_req" => { "in" => [ "gp", "gp" ] },
630 "op_flags" => "L|X|Y",
631 "comment" => "construct switch",
632 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
633 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
640 "comment" => "represents an integer constant",
641 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
642 "reg_req" => { "in" => [ "none" ], "out" => [ "gp" ] },
646 # we should not rematrialize this node. It produces 2 results and has
647 # very strict constrains
648 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
649 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
650 "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */',
651 "outs" => [ "EAX", "EDX" ],
658 "state" => "exc_pinned",
659 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
660 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
661 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
664 ' if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) {
665 4. mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
668 4. mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
671 "outs" => [ "res", "M" ],
676 "cmp_attr" => " return 1;\n",
677 "comment" => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg",
678 "outs" => [ "res", "M" ],
684 "cmp_attr" => " return 1;\n",
685 "state" => "exc_pinned",
686 "comment" => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val",
693 "state" => "exc_pinned",
694 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
695 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
696 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
697 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
704 "state" => "exc_pinned",
705 "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
706 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
707 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx gp_NOREG", "none" ] },
708 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
715 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
716 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
717 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
718 "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */',
723 "comment" => "push on the stack",
724 "reg_req" => { "in" => [ "gp", "gp", "gp", "esp", "none" ], "out" => [ "esp" ] },
725 "emit" => '. push %ia32_emit_unop /* PUSH(%A1) */',
726 "outs" => [ "stack:I|S", "M" ],
731 # We don't set class modify stack here (but we will do this on proj 1)
732 "comment" => "pop a gp register from the stack",
733 "reg_req" => { "in" => [ "gp", "gp", "esp", "none" ], "out" => [ "gp", "esp" ] },
734 "emit" => '. pop %ia32_emit_unop /* POP(%A1) */',
735 "outs" => [ "res", "stack:I|S", "M" ],
740 "comment" => "create stack frame",
741 "reg_req" => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] },
742 "emit" => '. enter /* Enter */',
743 "outs" => [ "frame:I", "stack:I|S", "M" ],
748 "comment" => "destroy stack frame",
749 "reg_req" => { "in" => [ "esp", "ebp" ], "out" => [ "ebp", "esp" ] },
750 "emit" => '. leave /* Leave */',
751 "outs" => [ "frame:I", "stack:I|S", "M" ],
757 "comment" => "allocate space on stack",
758 "reg_req" => { "in" => [ "esp", "gp" ], "out" => [ "esp", "none" ] },
759 "outs" => [ "stack:S", "M" ],
764 "comment" => "free space on stack",
765 "reg_req" => { "in" => [ "esp", "gp" ], "out" => [ "esp", "none" ] },
766 "outs" => [ "stack:S", "M" ],
771 "comment" => "get the TLS base address",
772 "reg_req" => { "out" => [ "gp" ] },
777 #-----------------------------------------------------------------------------#
778 # _____ _____ ______ __ _ _ _ #
779 # / ____/ ____| ____| / _| | | | | | #
780 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
781 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
782 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
783 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
784 #-----------------------------------------------------------------------------#
786 # commutative operations
790 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
791 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
792 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
793 "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */',
794 "outs" => [ "res", "M" ],
800 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
801 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
802 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
803 "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */',
804 "outs" => [ "res", "M" ],
810 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
811 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
812 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
813 "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */',
814 "outs" => [ "res", "M" ],
820 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
821 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
822 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
823 "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */',
824 "outs" => [ "res", "M" ],
830 "comment" => "construct SSE And: And(a, b) = a AND b",
831 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
832 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
833 "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */',
834 "outs" => [ "res", "M" ],
840 "comment" => "construct SSE Or: Or(a, b) = a OR b",
841 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
842 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
843 "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */',
844 "outs" => [ "res", "M" ],
849 "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
850 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
851 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
852 "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */',
853 "outs" => [ "res", "M" ],
857 # not commutative operations
861 "comment" => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
862 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
863 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
864 "emit" => '. andnp%M %ia32_emit_binop /* SSE AndNot(%A3, %A4) -> %D1 */',
865 "outs" => [ "res", "M" ],
871 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
872 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
873 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
874 "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */',
875 "outs" => [ "res", "M" ],
881 "comment" => "construct SSE Div: Div(a, b) = a / b",
882 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
883 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
884 "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */',
885 "outs" => [ "res", "M" ],
893 "comment" => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
894 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
895 "outs" => [ "res", "M" ],
900 "op_flags" => "L|X|Y",
901 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
902 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
903 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
904 "outs" => [ "false", "true" ],
911 "comment" => "represents a SSE constant",
912 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
913 "reg_req" => { "in" => [ "none" ], "out" => [ "xmm" ] },
914 "emit" => '. movs%M %D1, %C /* Load fConst into register */',
922 "state" => "exc_pinned",
923 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
924 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
925 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm" ] },
926 "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */',
927 "outs" => [ "res", "M" ],
933 "state" => "exc_pinned",
934 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
935 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
936 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
937 "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */',
944 "state" => "exc_pinned",
945 "comment" => "construct Store without index: Store(ptr, val, mem) = ST ptr,val",
946 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
947 "reg_req" => { "in" => [ "gp", "xmm", "none" ] },
948 "emit" => '. movs%M %ia32_emit_am, %S2 /* store XMM0 onto stack */',
955 "comment" => "construct: transfer a value from x87 FPU into a SSE register",
956 "cmp_attr" => " return 1;\n",
962 "comment" => "construct: transfer a value from SSE register to x87 FPU",
963 "cmp_attr" => " return 1;\n",
970 "state" => "exc_pinned",
971 "comment" => "store ST0 onto stack",
972 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
973 "reg_req" => { "in" => [ "gp", "none" ] },
974 "emit" => '. fstp %ia32_emit_am /* store ST0 onto stack */',
982 "state" => "exc_pinned",
983 "comment" => "load ST0 from stack",
984 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
985 "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "vf0", "none" ] },
986 "emit" => '. fld %ia32_emit_am /* load ST0 from stack */',
987 "outs" => [ "res", "M" ],
996 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
997 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "edi", "esi", "ecx", "none" ] },
998 "outs" => [ "DST", "SRC", "CNT", "M" ],
1002 "op_flags" => "F|H",
1003 "state" => "pinned",
1004 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
1005 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1006 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "edi", "esi", "none" ] },
1007 "outs" => [ "DST", "SRC", "M" ],
1013 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
1014 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1015 "comment" => "construct Conv Int -> Int",
1016 "outs" => [ "res", "M" ],
1020 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
1021 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1022 "comment" => "construct Conv Int -> Int",
1023 "outs" => [ "res", "M" ],
1027 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
1028 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1029 "comment" => "construct Conv Int -> Floating Point",
1030 "outs" => [ "res", "M" ],
1035 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
1036 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1037 "comment" => "construct Conv Floating Point -> Int",
1038 "outs" => [ "res", "M" ],
1043 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
1044 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1045 "comment" => "construct Conv Floating Point -> Floating Point",
1046 "outs" => [ "res", "M" ],
1052 "comment" => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
1053 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "in_r4" ] },
1059 "comment" => "check if Psi condition tree evaluates to true and move result accordingly",
1060 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r3" ] },
1066 "comment" => "construct Conditional Move: SSE Compare + int CMov ",
1067 "reg_req" => { "in" => [ "xmm", "xmm", "gp", "gp" ], "out" => [ "in_r4" ] },
1073 "comment" => "construct Conditional Move: x87 Compare + int CMov",
1074 "reg_req" => { "in" => [ "vfp", "vfp", "gp", "gp" ], "out" => [ "in_r4" ] },
1080 "comment" => "construct Set: Set(sel) == sel ? 1 : 0",
1081 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1082 "outs" => [ "res", "M" ],
1088 "comment" => "check if Psi condition tree evaluates to true and set result accordingly",
1089 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax ebx ecx edx" ] },
1095 "comment" => "construct Set: SSE Compare + int Set",
1096 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1097 "outs" => [ "res", "M" ],
1103 "comment" => "construct Set: x87 Compare + int Set",
1104 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1105 "outs" => [ "res", "M" ],
1111 "comment" => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
1112 "reg_req" => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] },
1116 #----------------------------------------------------------#
1118 # (_) | | | | / _| | | | #
1119 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
1120 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
1121 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
1122 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
1124 # _ __ ___ __| | ___ ___ #
1125 # | '_ \ / _ \ / _` |/ _ \/ __| #
1126 # | | | | (_) | (_| | __/\__ \ #
1127 # |_| |_|\___/ \__,_|\___||___/ #
1128 #----------------------------------------------------------#
1132 "comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
1133 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1134 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1135 "outs" => [ "res", "M" ],
1141 "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1142 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1143 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1144 "outs" => [ "res", "M" ],
1150 "cmp_attr" => " return 1;\n",
1151 "comment" => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1157 "comment" => "virtual fp Sub: Sub(a, b) = a - b",
1158 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1159 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1160 "outs" => [ "res", "M" ],
1165 "cmp_attr" => " return 1;\n",
1166 "comment" => "lowered virtual fp Sub: Sub(a, b) = a - b",
1171 "comment" => "virtual fp Div: Div(a, b) = a / b",
1172 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1173 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1174 "outs" => [ "res", "M" ],
1179 "cmp_attr" => " return 1;\n",
1180 "comment" => "lowered virtual fp Div: Div(a, b) = a / b",
1186 "comment" => "virtual fp Abs: Abs(a) = |a|",
1187 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1193 "comment" => "virtual fp Chs: Chs(a) = -a",
1194 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1200 "comment" => "virtual fp Sin: Sin(a) = sin(a)",
1201 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1207 "comment" => "virtual fp Cos: Cos(a) = cos(a)",
1208 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1214 "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
1215 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1219 # virtual Load and Store
1222 "op_flags" => "L|F",
1223 "state" => "exc_pinned",
1224 "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
1225 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1226 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1227 "outs" => [ "res", "M" ],
1232 "op_flags" => "L|F",
1233 "state" => "exc_pinned",
1234 "comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
1235 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1236 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1244 "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1245 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1246 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1247 "outs" => [ "res", "M" ],
1252 "cmp_attr" => " return 1;\n",
1253 "comment" => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1254 "outs" => [ "res", "M" ],
1259 "comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1260 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1261 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1267 "cmp_attr" => " return 1;\n",
1268 "comment" => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1278 "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg",
1279 "reg_req" => { "out" => [ "vfp" ] },
1285 "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg",
1286 "reg_req" => { "out" => [ "vfp" ] },
1292 "comment" => "virtual fp Load pi: Ld pi -> reg",
1293 "reg_req" => { "out" => [ "vfp" ] },
1299 "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg",
1300 "reg_req" => { "out" => [ "vfp" ] },
1306 "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg",
1307 "reg_req" => { "out" => [ "vfp" ] },
1313 "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg",
1314 "reg_req" => { "out" => [ "vfp" ] },
1320 "comment" => "virtual fp Load ld e: Ld ld e -> reg",
1321 "reg_req" => { "out" => [ "vfp" ] },
1328 "init_attr" => " set_ia32_ls_mode(res, mode);",
1329 "comment" => "represents a virtual floating point constant",
1330 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1331 "reg_req" => { "in" => [ "none" ], "out" => [ "vfp" ] },
1338 "op_flags" => "L|X|Y",
1339 "comment" => "represents a virtual floating point compare",
1340 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1341 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] },
1342 "outs" => [ "false", "true", "temp_reg_eax" ],
1346 #------------------------------------------------------------------------#
1347 # ___ _____ __ _ _ _ #
1348 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1349 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1350 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1351 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1352 #------------------------------------------------------------------------#
1356 "rd_constructor" => "NONE",
1357 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1359 "emit" => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A3, %A4) -> %D1 */',
1364 "rd_constructor" => "NONE",
1365 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1367 "emit" => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A3, %A4) -> %D1 */',
1372 "rd_constructor" => "NONE",
1373 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1375 "emit" => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A3, %A4) -> %D1 */',
1380 "rd_constructor" => "NONE",
1381 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1383 "emit" => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A3, %A4) -> %D1 */',,
1388 "rd_constructor" => "NONE",
1389 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1391 "emit" => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A3, %A4) -> %D1 */',
1396 "rd_constructor" => "NONE",
1397 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1399 "emit" => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A3, %A4) -> %D1 */',
1404 "rd_constructor" => "NONE",
1406 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1408 "emit" => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A3, %A4) -> %D1 */',
1413 "rd_constructor" => "NONE",
1415 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1417 "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A3, %A4) -> %D1 */',
1422 "rd_constructor" => "NONE",
1423 "comment" => "x87 fp Div: Div(a, b) = a / b",
1425 "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A3, %A4) -> %D1 */',
1430 "rd_constructor" => "NONE",
1431 "comment" => "x87 fp Div: Div(a, b) = a / b",
1433 "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A3, %A4) -> %D1 */',
1438 "rd_constructor" => "NONE",
1439 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1441 "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A3, %A4) -> %D1 */',
1446 "rd_constructor" => "NONE",
1447 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1449 "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A3, %A4) -> %D1 */',
1454 "rd_constructor" => "NONE",
1455 "comment" => "x87 fp Abs: Abs(a) = |a|",
1457 "emit" => '. fabs /* x87 fabs(%A1) -> %D1 */',
1462 "rd_constructor" => "NONE",
1463 "comment" => "x87 fp Chs: Chs(a) = -a",
1465 "emit" => '. fchs /* x87 fchs(%A1) -> %D1 */',
1470 "rd_constructor" => "NONE",
1471 "comment" => "x87 fp Sin: Sin(a) = sin(a)",
1473 "emit" => '. fsin /* x87 sin(%A1) -> %D1 */',
1478 "rd_constructor" => "NONE",
1479 "comment" => "x87 fp Cos: Cos(a) = cos(a)",
1481 "emit" => '. fcos /* x87 cos(%A1) -> %D1 */',
1486 "rd_constructor" => "NONE",
1487 "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1489 "emit" => '. fsqrt $ /* x87 sqrt(%A1) -> %D1 */',
1492 # x87 Load and Store
1495 "rd_constructor" => "NONE",
1496 "op_flags" => "R|L|F",
1497 "state" => "exc_pinned",
1498 "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1500 "emit" => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */',
1504 "rd_constructor" => "NONE",
1505 "op_flags" => "R|L|F",
1506 "state" => "exc_pinned",
1507 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1509 "emit" => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */',
1513 "rd_constructor" => "NONE",
1514 "op_flags" => "R|L|F",
1515 "state" => "exc_pinned",
1516 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1518 "emit" => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */',
1525 "rd_constructor" => "NONE",
1526 "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1528 "emit" => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */',
1533 "rd_constructor" => "NONE",
1534 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1536 "emit" => '. fist %ia32_emit_am /* integer Store(%A3) -> (%A1) */',
1541 "rd_constructor" => "NONE",
1542 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1544 "emit" => '. fistp %ia32_emit_am /* integer Store(%A3) -> (%A1) and pop */',
1550 "op_flags" => "R|c",
1552 "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
1554 "emit" => '. fldz /* x87 0.0 -> %D1 */',
1558 "op_flags" => "R|c",
1560 "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
1562 "emit" => '. fld1 /* x87 1.0 -> %D1 */',
1566 "op_flags" => "R|c",
1568 "comment" => "x87 fp Load pi: Ld pi -> reg",
1570 "emit" => '. fldpi /* x87 pi -> %D1 */',
1574 "op_flags" => "R|c",
1576 "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
1578 "emit" => '. fldln2 /* x87 ln(2) -> %D1 */',
1582 "op_flags" => "R|c",
1584 "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
1586 "emit" => '. fldlg2 /* x87 log(2) -> %D1 */',
1590 "op_flags" => "R|c",
1592 "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
1594 "emit" => '. fldll2t /* x87 ld(10) -> %D1 */',
1598 "op_flags" => "R|c",
1600 "comment" => "x87 fp Load ld e: Ld ld e -> reg",
1602 "emit" => '. fldl2e /* x87 ld(e) -> %D1 */',
1606 "op_flags" => "R|c",
1608 "rd_constructor" => "NONE",
1609 "comment" => "represents a x87 constant",
1610 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1611 "reg_req" => { "out" => [ "st" ] },
1612 "emit" => '. fld %ia32_emit_adr /* Load fConst into register -> %D1 */',
1616 # Note that it is NEVER allowed to do CSE on these nodes
1619 "op_flags" => "R|K",
1620 "comment" => "x87 stack exchange",
1621 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1622 "cmp_attr" => " return 1;\n",
1623 "emit" => '. fxch %X1 /* x87 swap %X1, %X3 */',
1628 "comment" => "x87 stack push",
1629 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1630 "cmp_attr" => " return 1;\n",
1631 "emit" => '. fld %X1 /* x87 push %X1 */',
1635 "op_flags" => "R|K",
1636 "comment" => "x87 stack pop",
1637 "reg_req" => { "out" => [ "st" ] },
1638 "cmp_attr" => " return 1;\n",
1639 "emit" => '. fstp %X1 /* x87 pop %X1 */',
1645 "op_flags" => "L|X|Y",
1646 "comment" => "floating point compare",
1647 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1652 "op_flags" => "L|X|Y",
1653 "comment" => "floating point compare and pop",
1654 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1659 "op_flags" => "L|X|Y",
1660 "comment" => "floating point compare and pop twice",
1661 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1666 "op_flags" => "L|X|Y",
1667 "comment" => "floating point compare reverse",
1668 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1673 "op_flags" => "L|X|Y",
1674 "comment" => "floating point compare reverse and pop",
1675 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1680 "op_flags" => "L|X|Y",
1681 "comment" => "floating point compare reverse and pop twice",
1682 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",