3 # This is the specification for the ia32 assembler Firm-operations
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
9 # this string marks the beginning of a comment in emit
10 $comment_string = "/*";
12 # The node description is done as a perl hash initializer with the
13 # following structure:
18 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
19 # "irn_flags" => "R|N|I"
20 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
21 # "state" => "floats|pinned|mem_pinned|exc_pinned",
23 # { "type" => "type 1", "name" => "name 1" },
24 # { "type" => "type 2", "name" => "name 2" },
27 # "comment" => "any comment for constructor",
28 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
29 # "cmp_attr" => "c source code for comparing node attributes",
30 # "emit" => "emit code with templates",
31 # "rd_constructor" => "c source code which constructs an ir_node"
34 # ... # (all nodes you need to describe)
36 # ); # close the %nodes initializer
38 # op_flags: flags for the operation, OPTIONAL (default is "N")
39 # the op_flags correspond to the firm irop_flags:
42 # C irop_flag_commutative
43 # X irop_flag_cfopcode
44 # I irop_flag_ip_cfopcode
47 # H irop_flag_highlevel
48 # c irop_flag_constlike
51 # irn_flags: special node flags, OPTIONAL (default is 0)
52 # following irn_flags are supported:
55 # I ignore for register allocation
57 # state: state of the operation, OPTIONAL (default is "floats")
59 # arity: arity of the operation, MUST NOT BE OMITTED
61 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
62 # are always the first 3 arguments and are always autmatically
64 # If this key is missing the following arguments will be created:
65 # for i = 1 .. arity: ir_node *op_i
68 # comment: OPTIONAL comment for the node constructor
70 # rd_constructor: for every operation there will be a
71 # new_rd_<arch>_<op-name> function with the arguments from above
72 # which creates the ir_node corresponding to the defined operation
73 # you can either put the complete source code of this function here
75 # This key is OPTIONAL. If omitted, the following constructor will
77 # if (!op_<arch>_<op-name>) assert(0);
81 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
84 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
88 # 1 - caller save (register must be saved by the caller of a function)
89 # 2 - callee save (register must be saved by the called function)
90 # 4 - ignore (do not assign this register)
91 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
94 { "name" => "eax", "type" => 1 },
95 { "name" => "edx", "type" => 1 },
96 { "name" => "ebx", "type" => 2 },
97 { "name" => "ecx", "type" => 1 },
98 { "name" => "esi", "type" => 2 },
99 { "name" => "edi", "type" => 2 },
100 { "name" => "ebp", "type" => 2 },
101 { "name" => "esp", "type" => 4 },
102 { "name" => "xxx", "type" => 6 }, # we need a dummy register for NoReg and Unknown nodes
103 { "mode" => "mode_P" }
106 { "name" => "xmm0", "type" => 1 },
107 { "name" => "xmm1", "type" => 1 },
108 { "name" => "xmm2", "type" => 1 },
109 { "name" => "xmm3", "type" => 1 },
110 { "name" => "xmm4", "type" => 1 },
111 { "name" => "xmm5", "type" => 1 },
112 { "name" => "xmm6", "type" => 1 },
113 { "name" => "xmm7", "type" => 1 },
114 { "name" => "xxxx", "type" => 6 }, # we need a dummy register for NoReg and Unknown nodes
115 { "mode" => "mode_D" }
119 #--------------------------------------------------#
122 # _ __ _____ __ _ _ __ ___ _ __ ___ #
123 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
124 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
125 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
128 #--------------------------------------------------#
132 #-----------------------------------------------------------------#
135 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
136 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
137 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
138 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
141 #-----------------------------------------------------------------#
143 # commutative operations
146 # All nodes supporting Addressmode have 5 INs:
147 # 1 - base r1 == NoReg in case of no AM or no base
148 # 2 - index r2 == NoReg in case of no AM or no index
149 # 3 - op1 r3 == always present
150 # 4 - op2 r4 == NoReg in case of immediate operation
151 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
155 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
156 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
157 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
158 "emit" => '. add %ia32_emit_binop /* Add(%A1, %A2) -> %D1 */'
163 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
164 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
165 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
166 "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */'
169 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
171 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
172 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
173 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r3", "edx in_r4" ] },
174 "emit" => '. imul %ia32_emit_unop /* Mulh(%A1, %A2) -> %D1 */'
179 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
180 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
181 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
182 "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */'
187 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
188 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
189 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
190 "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */'
195 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
196 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
197 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
198 "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */'
203 "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
204 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
206 '2. cmp %S1, %S2 /* prepare Max (%S1 - %S2), (%A1, %A2) */
207 if (mode_is_signed(get_irn_mode(n))) {
208 4. cmovl %D1, %S2 /* %S1 is less %S2 */
211 4. cmovb %D1, %S2 /* %S1 is below %S2 */
218 "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
219 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
221 '2. cmp %S1, %S2 /* prepare Min (%S1 - %S2), (%A1, %A2) */
222 if (mode_is_signed(get_irn_mode(n))) {
223 2. cmovg %D1, %S2 /* %S1 is greater %S2 */
226 2. cmova %D1, %S2, %D1 /* %S1 is above %S2 */
233 "comment" => "construct Mux: Mux(sel, a, b) == sel ? a : b",
234 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r2" ] },
236 '. cmp %S1, 0 /* compare Sel for CMov (%A2, %A3) */
237 . cmovne %D1, %S3 /* sel == true -> return %S3 */
241 # not commutative operations
245 "comment" => "construct Sub: Sub(a, b) = a - b",
246 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
247 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
248 "emit" => '. sub %ia32_emit_binop /* Sub(%A1, %A2) -> %D1 */'
253 "state" => "exc_pinned",
254 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "eax in_r1", "edx in_r3" ] },
256 ' if (mode_is_signed(get_irn_mode(n))) {
257 4. idiv %S2 /* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
260 4. div %S2 /* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
267 "comment" => "construct Shl: Shl(a, b) = a << b",
268 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
269 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
270 "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */'
275 "comment" => "construct Shr: Shr(a, b) = a >> b",
276 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
277 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
278 "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */'
283 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
284 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
285 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
286 "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */'
291 "comment" => "construct RotR: RotR(a, b) = a ROTR b",
292 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
293 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
294 "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */'
299 "comment" => "construct RotL: RotL(a, b) = a ROTL b",
300 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
301 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
302 "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */'
309 "comment" => "construct Minus: Minus(a) = -a",
310 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
311 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
312 "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */'
317 "comment" => "construct Increment: Inc(a) = a++",
318 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
319 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
320 "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */'
325 "comment" => "construct Decrement: Dec(a) = a--",
326 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
327 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
328 "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */'
333 "comment" => "construct Not: Not(a) = !a",
334 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
335 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
336 "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */'
342 "op_flags" => "L|X|Y",
343 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
344 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
345 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
349 "op_flags" => "L|X|Y",
350 "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
351 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "none", "none" ] },
352 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
356 "op_flags" => "L|X|Y",
357 "comment" => "construct switch",
358 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
359 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
365 "comment" => "represents an integer constant",
366 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
367 "reg_req" => { "out" => [ "gp" ] },
369 ' if (get_ia32_Immop_tarval(n) == get_tarval_null(get_irn_mode(n))) {
370 4. sub %D1, %D1 /* optimized mov 0 to register */
373 if (get_ia32_sc(n)) {
374 6. lea %D1, %C /* Load address of SymConst into register */
377 6. mov %D1, %C /* Mov Const into register */
385 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
386 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
387 "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */'
395 "state" => "exc_pinned",
396 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
397 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
398 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
400 ' if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) {
401 4. mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
404 4. mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
411 "state" => "exc_pinned",
412 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
413 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
414 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
415 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */'
420 "state" => "exc_pinned",
421 "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
422 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
423 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
424 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */'
429 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
430 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
431 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
432 "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */'
435 #--------------------------------------------------------#
438 # | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
439 # | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
440 # | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
441 # |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
442 #--------------------------------------------------------#
444 # commutative operations
448 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
449 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
450 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
451 "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */'
456 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
457 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
458 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
459 "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */'
464 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
465 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
466 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
467 "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */'
472 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
473 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
474 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
475 "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */'
480 "comment" => "construct SSE And: And(a, b) = a AND b",
481 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
482 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
483 "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */'
488 "comment" => "construct SSE Or: Or(a, b) = a OR b",
489 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
490 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
491 "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */'
496 "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
497 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
498 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
499 "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */'
502 # not commutative operations
506 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
507 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
508 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
509 "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */'
514 "comment" => "construct SSE Div: Div(a, b) = a / b",
515 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
516 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3 !in_r4" ] },
517 "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */'
523 "op_flags" => "L|X|Y",
524 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
525 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
526 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "none", "none" ] },
532 "comment" => "represents a SSE constant",
533 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
534 "reg_req" => { "out" => [ "fp" ] },
535 "emit" => '. mov%M %D1, %C /* Load fConst into register */',
543 "state" => "exc_pinned",
544 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
545 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
546 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "fp" ] },
547 "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */'
552 "state" => "exc_pinned",
553 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
554 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
555 "reg_req" => { "in" => [ "gp", "gp", "fp", "none" ] },
556 "emit" => '. movs%M %ia32_emit_am, %S3 /* Store(%S3) -> (%A1) */'
564 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
565 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "none" ] },
571 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
572 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
573 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "none" ] },
579 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "fp", "none" ] },
580 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
581 "comment" => "construct Conv Int -> Floating Point"
585 "reg_req" => { "in" => [ "gp", "gp", "fp", "none" ], "out" => [ "gp", "none" ] },
586 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
587 "comment" => "construct Conv Floating Point -> Int"
591 "reg_req" => { "in" => [ "gp", "gp", "fp", "none" ], "out" => [ "fp", "none" ] },
592 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
593 "comment" => "construct Conv Floating Point -> Floating Point",