3 # This is the specification for the ia32 assembler Firm-operations
10 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
13 # The node description is done as a perl hash initializer with the
14 # following structure:
19 # op_flags => "N|L|C|X|I|F|Y|H|c|K",
20 # irn_flags => "R|N|I|S"
21 # arity => "0|1|2|3 ... |variable|dynamic|any",
22 # state => "floats|pinned|mem_pinned|exc_pinned",
24 # { type => "type 1", name => "name 1" },
25 # { type => "type 2", name => "name 2" },
28 # comment => "any comment for constructor",
29 # reg_req => { in => [ "reg_class|register" ], out => [ "reg_class|register|in_rX" ] },
30 # cmp_attr => "c source code for comparing node attributes",
31 # emit => "emit code with templates",
32 # attr => "attitional attribute arguments for constructor"
33 # init_attr => "emit attribute initialization template"
34 # rd_constructor => "c source code which constructs an ir_node"
35 # latency => "latency of this operation (can be float)"
38 # ... # (all nodes you need to describe)
40 # ); # close the %nodes initializer
42 # op_flags: flags for the operation, OPTIONAL (default is "N")
43 # the op_flags correspond to the firm irop_flags:
46 # C irop_flag_commutative
47 # X irop_flag_cfopcode
48 # I irop_flag_ip_cfopcode
51 # H irop_flag_highlevel
52 # c irop_flag_constlike
55 # irn_flags: special node flags, OPTIONAL (default is 0)
56 # following irn_flags are supported:
59 # I ignore for register allocation
60 # S modifies stack pointer
62 # state: state of the operation, OPTIONAL (default is "floats")
64 # arity: arity of the operation, MUST NOT BE OMITTED
66 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
67 # are always the first 3 arguments and are always autmatically
69 # If this key is missing the following arguments will be created:
70 # for i = 1 .. arity: ir_node *op_i
73 # outs: if a node defines more than one output, the names of the projections
74 # nodes having outs having automatically the mode mode_T
75 # One can also annotate some flags for each out, additional to irn_flags.
76 # They are separated from name with a colon ':', and concatenated by pipe '|'
77 # Only I and S are available at the moment (same meaning as in irn_flags).
78 # example: [ "frame:I", "stack:I|S", "M" ]
80 # comment: OPTIONAL comment for the node constructor
82 # rd_constructor: for every operation there will be a
83 # new_rd_<arch>_<op-name> function with the arguments from above
84 # which creates the ir_node corresponding to the defined operation
85 # you can either put the complete source code of this function here
87 # This key is OPTIONAL. If omitted, the following constructor will
89 # if (!op_<arch>_<op-name>) assert(0);
93 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
96 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
98 # latency: the latency of the operation, default is 1
102 # 0 - no special type
103 # 1 - caller save (register must be saved by the caller of a function)
104 # 2 - callee save (register must be saved by the called function)
105 # 4 - ignore (do not assign this register)
106 # 8 - emitter can choose an arbitrary register of this class
107 # 16 - the register is a virtual one
108 # 32 - register represents a state
109 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
112 { name => "eax", type => 1 },
113 { name => "edx", type => 1 },
114 { name => "ebx", type => 2 },
115 { name => "ecx", type => 1 },
116 { name => "esi", type => 2 },
117 { name => "edi", type => 2 },
118 { name => "ebp", type => 2 },
119 { name => "esp", type => 4 },
120 { name => "gp_NOREG", type => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
121 { name => "gp_UKNWN", type => 4 | 8 | 16 }, # we need a dummy register for Unknown nodes
122 { mode => "mode_Iu" }
125 { name => "xmm0", type => 1 },
126 { name => "xmm1", type => 1 },
127 { name => "xmm2", type => 1 },
128 { name => "xmm3", type => 1 },
129 { name => "xmm4", type => 1 },
130 { name => "xmm5", type => 1 },
131 { name => "xmm6", type => 1 },
132 { name => "xmm7", type => 1 },
133 { name => "xmm_NOREG", type => 4 | 16 }, # we need a dummy register for NoReg nodes
134 { name => "xmm_UKNWN", type => 4 | 8 | 16}, # we need a dummy register for Unknown nodes
138 { name => "vf0", type => 1 | 16 },
139 { name => "vf1", type => 1 | 16 },
140 { name => "vf2", type => 1 | 16 },
141 { name => "vf3", type => 1 | 16 },
142 { name => "vf4", type => 1 | 16 },
143 { name => "vf5", type => 1 | 16 },
144 { name => "vf6", type => 1 | 16 },
145 { name => "vf7", type => 1 | 16 },
146 { name => "vfp_NOREG", type => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
147 { name => "vfp_UKNWN", type => 4 | 8 | 16 }, # we need a dummy register for Unknown nodes
151 { name => "st0", realname => "st", type => 4 },
152 { name => "st1", realname => "st(1)", type => 4 },
153 { name => "st2", realname => "st(2)", type => 4 },
154 { name => "st3", realname => "st(3)", type => 4 },
155 { name => "st4", realname => "st(4)", type => 4 },
156 { name => "st5", realname => "st(5)", type => 4 },
157 { name => "st6", realname => "st(6)", type => 4 },
158 { name => "st7", realname => "st(7)", type => 4 },
161 fp_cw => [ # the floating point control word
162 { name => "fpcw", type => 4 | 32},
163 { mode => "mode_fpcw" }
166 { name => "eflags", type => 4 },
167 { mode => "mode_Iu" }
170 { name => "fpsw", type => 4 },
171 { mode => "mode_Hu" }
176 CF => { reg => "eflags", bit => 0 },
177 PF => { reg => "eflags", bit => 2 },
178 AF => { reg => "eflags", bit => 4 },
179 ZF => { reg => "eflags", bit => 6 },
180 SF => { reg => "eflags", bit => 7 },
181 TF => { reg => "eflags", bit => 8 },
182 IF => { reg => "eflags", bit => 9 },
183 DF => { reg => "eflags", bit => 10 },
184 OF => { reg => "eflags", bit => 11 },
185 IOPL0 => { reg => "eflags", bit => 12 },
186 IOPL1 => { reg => "eflags", bit => 13 },
187 NT => { reg => "eflags", bit => 14 },
188 RF => { reg => "eflags", bit => 16 },
189 VM => { reg => "eflags", bit => 17 },
190 AC => { reg => "eflags", bit => 18 },
191 VIF => { reg => "eflags", bit => 19 },
192 VIP => { reg => "eflags", bit => 20 },
193 ID => { reg => "eflags", bit => 21 },
195 FP_IE => { reg => "fpsw", bit => 0 },
196 FP_DE => { reg => "fpsw", bit => 1 },
197 FP_ZE => { reg => "fpsw", bit => 2 },
198 FP_OE => { reg => "fpsw", bit => 3 },
199 FP_UE => { reg => "fpsw", bit => 4 },
200 FP_PE => { reg => "fpsw", bit => 5 },
201 FP_SF => { reg => "fpsw", bit => 6 },
202 FP_ES => { reg => "fpsw", bit => 7 },
203 FP_C0 => { reg => "fpsw", bit => 8 },
204 FP_C1 => { reg => "fpsw", bit => 9 },
205 FP_C2 => { reg => "fpsw", bit => 10 },
206 FP_TOP0 => { reg => "fpsw", bit => 11 },
207 FP_TOP1 => { reg => "fpsw", bit => 12 },
208 FP_TOP2 => { reg => "fpsw", bit => 13 },
209 FP_C3 => { reg => "fpsw", bit => 14 },
210 FP_B => { reg => "fpsw", bit => 15 },
212 FP_IM => { reg => "fpcw", bit => 0 },
213 FP_DM => { reg => "fpcw", bit => 1 },
214 FP_ZM => { reg => "fpcw", bit => 2 },
215 FP_OM => { reg => "fpcw", bit => 3 },
216 FP_UM => { reg => "fpcw", bit => 4 },
217 FP_PM => { reg => "fpcw", bit => 5 },
218 FP_PC0 => { reg => "fpcw", bit => 8 },
219 FP_PC1 => { reg => "fpcw", bit => 9 },
220 FP_RC0 => { reg => "fpcw", bit => 10 },
221 FP_RC1 => { reg => "fpcw", bit => 11 },
222 FP_X => { reg => "fpcw", bit => 12 }
226 GP => [ 1, "GP_EAX", "GP_EBX", "GP_ECX", "GP_EDX", "GP_ESI", "GP_EDI", "GP_EBP" ],
227 SSE => [ 1, "SSE_XMM0", "SSE_XMM1", "SSE_XMM2", "SSE_XMM3", "SSE_XMM4", "SSE_XMM5", "SSE_XMM6", "SSE_XMM7" ],
228 VFP => [ 1, "VFP_VF0", "VFP_VF1", "VFP_VF2", "VFP_VF3", "VFP_VF4", "VFP_VF5", "VFP_VF6", "VFP_VF7" ],
229 BRANCH => [ 1, "BRANCH1", "BRANCH2" ],
234 bundels_per_cycle => 1
238 S0 => "${arch}_emit_source_register(env, node, 0);",
239 S1 => "${arch}_emit_source_register(env, node, 1);",
240 S2 => "${arch}_emit_source_register(env, node, 2);",
241 S3 => "${arch}_emit_source_register(env, node, 3);",
242 S4 => "${arch}_emit_source_register(env, node, 4);",
243 S5 => "${arch}_emit_source_register(env, node, 5);",
244 D0 => "${arch}_emit_dest_register(env, node, 0);",
245 D1 => "${arch}_emit_dest_register(env, node, 1);",
246 D2 => "${arch}_emit_dest_register(env, node, 2);",
247 D3 => "${arch}_emit_dest_register(env, node, 3);",
248 D4 => "${arch}_emit_dest_register(env, node, 4);",
249 D5 => "${arch}_emit_dest_register(env, node, 5);",
250 X0 => "${arch}_emit_x87_name(env, node, 0);",
251 X1 => "${arch}_emit_x87_name(env, node, 1);",
252 X2 => "${arch}_emit_x87_name(env, node, 2);",
253 C => "${arch}_emit_immediate(env, node);",
254 SE => "${arch}_emit_extend_suffix(env, get_ia32_ls_mode(node));",
255 ME => "if(get_mode_size_bits(get_ia32_ls_mode(node)) != 32)\n
256 ia32_emit_mode_suffix(env, node);",
257 M => "${arch}_emit_mode_suffix(env, node);",
258 XM => "${arch}_emit_x87_mode_suffix(env, node);",
259 XXM => "${arch}_emit_xmm_mode_suffix(env, node);",
260 XSD => "${arch}_emit_xmm_mode_suffix_s(env, node);",
261 AM => "${arch}_emit_am(env, node);",
262 unop => "${arch}_emit_unop(env, node);",
263 binop => "${arch}_emit_binop(env, node);",
264 x87_binop => "${arch}_emit_x87_binop(env, node);",
267 #--------------------------------------------------#
270 # _ __ _____ __ _ _ __ ___ _ __ ___ #
271 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
272 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
273 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
276 #--------------------------------------------------#
278 $default_cmp_attr = "return ia32_compare_attr(attr_a, attr_b);";
279 $default_attr_type = "ia32_attr_t";
284 $mode_xmm = "mode_E";
285 $mode_gp = "mode_Iu";
286 $mode_fpcw = "mode_fpcw";
287 $status_flags = [ "CF", "PF", "AF", "ZF", "SF", "OF" ];
288 $fpcw_flags = [ "FP_IM", "FP_DM", "FP_ZM", "FP_OM", "FP_UM", "FP_PM",
289 "FP_PC0", "FP_PC1", "FP_RC0", "FP_RC1", "FP_X" ];
295 # reg_req => { out => [ "NoReg_GP" ] },
297 # attr_type => "ia32_imm_t",
300 #-----------------------------------------------------------------#
303 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
304 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
305 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
306 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
309 #-----------------------------------------------------------------#
311 # commutative operations
314 # All nodes supporting Addressmode have 5 INs:
315 # 1 - base r1 == NoReg in case of no AM or no base
316 # 2 - index r2 == NoReg in case of no AM or no index
317 # 3 - op1 r3 == always present
318 # 4 - op2 r4 == NoReg in case of immediate operation
319 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
323 comment => "construct Add: Add(a, b) = Add(b, a) = a + b",
324 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
325 ins => [ "base", "index", "left", "right", "mem" ],
326 emit => '. add%M %binop',
329 modified_flags => $status_flags
333 comment => "construct Add with Carry: Adc(a, b) = Add(b, a) = a + b + carry",
334 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
335 emit => '. adc%M %binop',
338 modified_flags => $status_flags
343 comment => "construct 64Bit Add: Add(a_l, a_h, b_l, b_h) = a_l + b_l; a_h + b_h + carry",
345 reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
352 outs => [ "low_res", "high_res" ],
354 modified_flags => $status_flags
360 cmp_attr => "return 1;",
361 comment => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
367 cmp_attr => "return 1;",
368 comment => "construct lowered Add with Carry: Adc(a, b) = Adc(b, a) = a + b + carry",
373 # we should not rematrialize this node. It produces 2 results and has
374 # very strict constrains
375 comment => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
376 reg_req => { in => [ "gp", "gp", "eax", "gp", "none" ], out => [ "eax", "edx", "none" ] },
377 emit => '. mul%M %unop',
378 outs => [ "EAX", "EDX", "M" ],
381 modified_flags => $status_flags
385 # we should not rematrialize this node. It produces 2 results and has
386 # very strict constrains
388 cmp_attr => "return 1;",
389 comment => "construct lowered MulS: Mul(a, b) = Mul(b, a) = a * b",
390 outs => [ "EAX", "EDX", "M" ],
396 comment => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
397 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
398 emit => '. imul%M %binop',
402 modified_flags => $status_flags
407 comment => "construct Mul (1 operand format): Mul(a, b) = Mul(b, a) = a * b",
408 reg_req => { in => [ "gp", "gp", "eax", "gp", "none" ], out => [ "eax", "edx", "none" ] },
409 emit => '. imul%M %unop',
410 outs => [ "EAX", "EDX", "M" ],
413 modified_flags => $status_flags
418 cmp_attr => "return 1;",
419 comment => "construct lowered IMul: IMul(a, b) = IMul(b, a) = a * b",
425 comment => "construct And: And(a, b) = And(b, a) = a AND b",
426 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
427 emit => '. and%M %binop',
430 modified_flags => $status_flags
435 comment => "construct Or: Or(a, b) = Or(b, a) = a OR b",
436 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
437 emit => '. or%M %binop',
440 modified_flags => $status_flags
445 comment => "construct Xor: Xor(a, b) = Xor(b, a) = a EOR b",
446 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
447 emit => '. xor%M %binop',
450 modified_flags => $status_flags
455 cmp_attr => "return 1;",
456 comment => "construct lowered Xor: Xor(a, b) = Xor(b, a) = a XOR b",
458 modified_flags => $status_flags
461 # not commutative operations
465 comment => "construct Sub: Sub(a, b) = a - b",
466 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
467 emit => '. sub%M %binop',
470 modified_flags => $status_flags
474 comment => "construct Sub with Carry: SubC(a, b) = a - b - carry",
475 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3 !in_r4" ] },
476 emit => '. sbb%M %binop',
479 modified_flags => $status_flags
484 comment => "construct 64Bit Sub: Sub(a_l, a_h, b_l, b_h) = a_l - b_l; a_h - b_h - borrow",
486 reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
493 outs => [ "low_res", "high_res" ],
495 modified_flags => $status_flags
500 cmp_attr => "return 1;",
501 comment => "construct lowered Sub: Sub(a, b) = a - b",
506 cmp_attr => "return 1;",
507 comment => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
513 state => "exc_pinned",
514 reg_req => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ], out => [ "eax", "edx", "none" ] },
515 attr => "ia32_op_flavour_t dm_flav",
516 init_attr => "attr->data.op_flav = dm_flav;",
517 emit => ". idiv%M %unop",
518 outs => [ "div_res", "mod_res", "M" ],
521 modified_flags => $status_flags
526 state => "exc_pinned",
527 reg_req => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ], out => [ "eax", "edx", "none" ] },
528 attr => "ia32_op_flavour_t dm_flav",
529 init_attr => "attr->data.op_flav = dm_flav;",
530 emit => ". div%M %unop",
531 outs => [ "div_res", "mod_res", "M" ],
534 modified_flags => $status_flags
539 comment => "construct Shl: Shl(a, b) = a << b",
540 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
541 ins => [ "base", "index", "left", "right", "mem" ],
542 emit => '. shl%M %binop',
545 modified_flags => $status_flags
549 cmp_attr => "return 1;",
550 comment => "construct lowered Shl: Shl(a, b) = a << b",
556 comment => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
557 # Out requirements is: different from all in
558 # This is because, out must be different from LowPart and ShiftCount.
559 # We could say "!ecx !in_r4" but it can occur, that all values live through
560 # this Shift and the only value dying is the ShiftCount. Then there would be a
561 # register missing, as result must not be ecx and all other registers are
562 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
563 # (and probably never will). So we create artificial interferences of the result
564 # with all inputs, so the spiller can always assure a free register.
565 reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
568 if (get_ia32_immop_type(node) == ia32_ImmNone) {
569 if (get_ia32_op_type(node) == ia32_AddrModeD) {
570 . shld%M %%cl, %S3, %AM
572 . shld%M %%cl, %S3, %S2
575 if (get_ia32_op_type(node) == ia32_AddrModeD) {
576 . shld%M %C, %S3, %AM
578 . shld%M %C, %S3, %S2
585 modified_flags => $status_flags
589 cmp_attr => "return 1;",
590 comment => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
596 comment => "construct Shr: Shr(a, b) = a >> b",
597 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
598 emit => '. shr%M %binop',
601 modified_flags => $status_flags
605 cmp_attr => "return 1;",
606 comment => "construct lowered Shr: Shr(a, b) = a << b",
612 comment => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
613 # Out requirements is: different from all in
614 # This is because, out must be different from LowPart and ShiftCount.
615 # We could say "!ecx !in_r4" but it can occur, that all values live through
616 # this Shift and the only value dying is the ShiftCount. Then there would be a
617 # register missing, as result must not be ecx and all other registers are
618 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
619 # (and probably never will). So we create artificial interferences of the result
620 # with all inputs, so the spiller can always assure a free register.
621 reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
623 if (get_ia32_immop_type(node) == ia32_ImmNone) {
624 if (get_ia32_op_type(node) == ia32_AddrModeD) {
625 . shrd%M %%cl, %S3, %AM
627 . shrd%M %%cl, %S3, %S2
630 if (get_ia32_op_type(node) == ia32_AddrModeD) {
631 . shrd%M %C, %S3, %AM
633 . shrd%M %C, %S3, %S2
640 modified_flags => $status_flags
644 cmp_attr => "return 1;",
645 comment => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
651 comment => "construct Shrs: Shrs(a, b) = a >> b",
652 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
653 emit => '. sar%M %binop',
656 modified_flags => $status_flags
660 cmp_attr => "return 1;",
661 comment => "construct lowered Sar: Sar(a, b) = a << b",
667 comment => "construct Ror: Ror(a, b) = a ROR b",
668 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
669 emit => '. ror%M %binop',
672 modified_flags => $status_flags
677 comment => "construct Rol: Rol(a, b) = a ROL b",
678 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
679 emit => '. rol%M %binop',
682 modified_flags => $status_flags
689 comment => "construct Minus: Minus(a) = -a",
690 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
691 emit => '. neg%M %unop',
694 modified_flags => $status_flags
699 comment => "construct 64Bit Minus: Minus(a_l, a_h, 0) = 0 - a_l; 0 - a_h - borrow",
701 reg_req => { in => [ "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
708 outs => [ "low_res", "high_res" ],
710 modified_flags => $status_flags
715 cmp_attr => "return 1;",
716 comment => "construct lowered Minus: Minus(a) = -a",
722 comment => "construct Increment: Inc(a) = a++",
723 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
724 emit => '. inc%M %unop',
727 modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
732 comment => "construct Decrement: Dec(a) = a--",
733 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
734 emit => '. dec%M %unop',
737 modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
742 comment => "construct Not: Not(a) = !a",
743 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
744 emit => '. not%M %unop',
755 comment => "construct conditional jump: CMP A, B && JMPxx LABEL",
756 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ] },
757 outs => [ "false", "true" ],
759 units => [ "BRANCH" ],
765 comment => "construct conditional jump: TEST A, B && JMPxx LABEL",
766 reg_req => { in => [ "gp", "gp" ] },
767 outs => [ "false", "true" ],
769 units => [ "BRANCH" ],
775 comment => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
776 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "none", "none" ] },
777 outs => [ "false", "true" ],
778 units => [ "BRANCH" ],
784 comment => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
785 reg_req => { in => [ "gp", "gp" ] },
786 units => [ "BRANCH" ],
792 comment => "construct switch",
793 reg_req => { in => [ "gp" ], out => [ "none" ] },
795 units => [ "BRANCH" ],
801 comment => "represents an integer constant",
802 reg_req => { out => [ "gp" ] },
811 comment => "unknown value",
812 reg_req => { out => [ "gp_UKNWN" ] },
822 comment => "unknown value",
823 reg_req => { out => [ "vfp_UKNWN" ] },
833 comment => "unknown value",
834 reg_req => { out => [ "xmm_UKNWN" ] },
844 comment => "noreg GP value",
845 reg_req => { out => [ "gp_NOREG" ] },
855 comment => "noreg VFP value",
856 reg_req => { out => [ "vfp_NOREG" ] },
866 comment => "noreg XMM value",
867 reg_req => { out => [ "xmm_NOREG" ] },
877 comment => "change floating point control word",
878 reg_req => { out => [ "fp_cw" ] },
882 modified_flags => $fpcw_flags
887 state => "exc_pinned",
888 comment => "load floating point control word FldCW(ptr, mem) = LD ptr -> reg",
889 reg_req => { in => [ "gp", "gp", "none" ], out => [ "fp_cw" ] },
891 emit => ". fldcw %AM",
894 modified_flags => $fpcw_flags
899 state => "exc_pinned",
900 comment => "store floating point control word: FstCW(ptr, mem) = ST ptr -> reg",
901 reg_req => { in => [ "gp", "gp", "fp_cw", "none" ], out => [ "none" ] },
903 emit => ". fnstcw %AM",
909 # we should not rematrialize this node. It produces 2 results and has
910 # very strict constrains
911 comment => "construct CDQ: sign extend EAX -> EDX:EAX",
912 reg_req => { in => [ "gp" ], out => [ "eax in_r1", "edx" ] },
914 outs => [ "EAX", "EDX" ],
922 state => "exc_pinned",
923 comment => "construct Load: Load(ptr, mem) = LD ptr -> reg",
924 reg_req => { in => [ "gp", "gp", "none" ], out => [ "gp", "none" ] },
926 emit => ". mov%SE%ME%.l %AM, %D0",
927 outs => [ "res", "M" ],
933 cmp_attr => "return 1;",
934 comment => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg",
935 outs => [ "res", "M" ],
941 cmp_attr => "return 1;",
942 state => "exc_pinned",
943 comment => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val",
950 state => "exc_pinned",
951 comment => "construct Store: Store(ptr, val, mem) = ST ptr,val",
952 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "none" ] },
953 emit => '. mov%M %binop',
961 state => "exc_pinned",
962 comment => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
963 reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => ["none" ] },
964 emit => '. mov%M %binop',
972 comment => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
973 reg_req => { in => [ "gp", "gp" ], out => [ "in_r1" ] },
974 emit => '. leal %AM, %D0',
978 modified_flags => [],
982 comment => "push on the stack",
983 reg_req => { in => [ "gp", "gp", "gp", "esp", "none" ], out => [ "esp", "none" ] },
984 emit => '. push%M %unop',
985 outs => [ "stack:I|S", "M" ],
988 modified_flags => [],
992 comment => "pop a gp register from the stack",
993 reg_req => { in => [ "gp", "gp", "esp", "none" ], out => [ "esp", "gp", "none" ] },
994 emit => '. pop%M %unop',
995 outs => [ "stack:I|S", "res", "M" ],
998 modified_flags => [],
1002 comment => "create stack frame",
1003 reg_req => { in => [ "esp" ], out => [ "ebp", "esp" ] },
1005 outs => [ "frame:I", "stack:I|S", "M" ],
1011 comment => "destroy stack frame",
1012 reg_req => { in => [ "esp", "ebp" ], out => [ "ebp", "esp" ] },
1014 outs => [ "frame:I", "stack:I|S" ],
1021 comment => "allocate space on stack",
1022 reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "none" ] },
1023 emit => '. addl %binop',
1024 outs => [ "stack:S", "M" ],
1026 modified_flags => $status_flags
1031 comment => "free space on stack",
1032 reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "none" ] },
1033 emit => '. subl %binop',
1034 outs => [ "stack:S", "M" ],
1036 modified_flags => $status_flags
1041 comment => "get the TLS base address",
1042 reg_req => { out => [ "gp" ] },
1046 # the int instruction
1048 reg_req => { in => [ "none" ], out => [ "none" ] },
1049 comment => "software interrupt",
1051 attr => "tarval *tv",
1052 init_attr => "\tset_ia32_Immop_tarval(res, tv);",
1055 cmp_attr => "return 1;",
1059 #-----------------------------------------------------------------------------#
1060 # _____ _____ ______ __ _ _ _ #
1061 # / ____/ ____| ____| / _| | | | | | #
1062 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1063 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1064 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1065 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1066 #-----------------------------------------------------------------------------#
1068 # commutative operations
1072 comment => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
1073 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1074 emit => '. add%XXM %binop',
1082 comment => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
1083 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1084 emit => '. mul%XXM %binop',
1092 comment => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
1093 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1094 emit => '. max%XXM %binop',
1102 comment => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
1103 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1104 emit => '. min%XXM %binop',
1112 comment => "construct SSE And: And(a, b) = a AND b",
1113 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1114 emit => '. andp%XSD %binop',
1122 comment => "construct SSE Or: Or(a, b) = a OR b",
1123 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1124 emit => '. orp%XSD %binop',
1131 comment => "construct SSE Xor: Xor(a, b) = a XOR b",
1132 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1133 emit => '. xorp%XSD %binop',
1139 # not commutative operations
1143 comment => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
1144 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] },
1145 emit => '. andnp%XSD %binop',
1153 comment => "construct SSE Sub: Sub(a, b) = a - b",
1154 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1155 emit => '. sub%XXM %binop',
1163 comment => "construct SSE Div: Div(a, b) = a / b",
1164 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] },
1165 outs => [ "res", "M" ],
1166 emit => '. div%XXM %binop',
1175 comment => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
1176 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] },
1184 op_flags => "L|X|Y",
1185 comment => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
1186 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "none", "none" ] },
1187 outs => [ "false", "true" ],
1195 comment => "represents a SSE constant",
1196 reg_req => { out => [ "xmm" ] },
1197 emit => '. mov%XXM %C, %D0',
1207 state => "exc_pinned",
1208 comment => "construct SSE Load: Load(ptr, mem) = LD ptr",
1209 reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none" ] },
1210 emit => '. mov%XXM %AM, %D0',
1211 outs => [ "res", "M" ],
1218 state => "exc_pinned",
1219 comment => "construct Store: Store(ptr, val, mem) = ST ptr,val",
1220 reg_req => { in => [ "gp", "gp", "xmm", "none" ] },
1221 emit => '. mov%XXM %binop',
1229 state => "exc_pinned",
1230 comment => "construct Store without index: Store(ptr, val, mem) = ST ptr,val",
1231 reg_req => { in => [ "gp", "gp", "xmm", "none" ] },
1232 ins => [ "base", "index", "val", "mem" ],
1233 emit => '. mov%XXM %S2, %AM',
1241 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm" ] },
1242 emit => '. cvtsi2ss %D0, %AM',
1250 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm" ] },
1251 emit => '. cvtsi2sd %unop',
1260 comment => "construct: transfer a value from x87 FPU into a SSE register",
1261 cmp_attr => "return 1;",
1267 comment => "construct: transfer a value from SSE register to x87 FPU",
1268 cmp_attr => "return 1;",
1275 state => "exc_pinned",
1276 comment => "store ST0 onto stack",
1277 reg_req => { in => [ "gp", "gp", "none" ] },
1278 emit => '. fstp%XM %AM',
1287 state => "exc_pinned",
1288 comment => "load ST0 from stack",
1289 reg_req => { in => [ "gp", "gp", "none" ], out => [ "vf0", "none" ] },
1290 ins => [ "base", "index", "mem" ],
1291 emit => '. fld%XM %AM',
1292 outs => [ "res", "M" ],
1302 comment => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
1303 reg_req => { in => [ "edi", "esi", "ecx", "none" ], out => [ "edi", "esi", "ecx", "none" ] },
1304 outs => [ "DST", "SRC", "CNT", "M" ],
1306 modified_flags => [ "DF" ]
1312 comment => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
1313 reg_req => { in => [ "edi", "esi", "none" ], out => [ "edi", "esi", "none" ] },
1314 outs => [ "DST", "SRC", "M" ],
1316 modified_flags => [ "DF" ]
1322 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3", "none" ] },
1323 comment => "construct Conv Int -> Int",
1326 modified_flags => $status_flags
1330 reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => [ "in_r3", "none" ] },
1331 comment => "construct Conv Int -> Int",
1334 modified_flags => $status_flags
1338 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm", "none" ] },
1339 comment => "construct Conv Int -> Floating Point",
1346 reg_req => { in => [ "gp", "gp", "xmm", "none" ], out => [ "gp", "none" ] },
1347 comment => "construct Conv Floating Point -> Int",
1354 reg_req => { in => [ "gp", "gp", "xmm", "none" ], out => [ "xmm", "none" ] },
1355 comment => "construct Conv Floating Point -> Floating Point",
1363 comment => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
1364 reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "in_r4" ] },
1372 comment => "check if Psi condition tree evaluates to true and move result accordingly",
1373 reg_req => { in => [ "gp", "gp", "gp" ], out => [ "in_r3" ] },
1381 comment => "construct Conditional Move: SSE Compare + int CMov ",
1382 reg_req => { in => [ "xmm", "xmm", "gp", "gp" ], out => [ "in_r4" ] },
1390 comment => "construct Conditional Move: x87 Compare + int CMov",
1391 reg_req => { in => [ "vfp", "vfp", "gp", "gp" ], out => [ "in_r4" ] },
1399 comment => "construct Set: Set(sel) == sel ? 1 : 0",
1400 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "eax ebx ecx edx" ] },
1408 comment => "check if Psi condition tree evaluates to true and set result accordingly",
1409 reg_req => { in => [ "gp" ], out => [ "eax ebx ecx edx" ] },
1417 comment => "construct Set: SSE Compare + int Set",
1418 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "eax ebx ecx edx" ] },
1426 comment => "construct Set: x87 Compare + int Set",
1427 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "eax ebx ecx edx" ] },
1435 comment => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
1436 reg_req => { in => [ "vfp", "vfp", "vfp", "vfp" ], out => [ "vfp" ] },
1442 #----------------------------------------------------------#
1444 # (_) | | | | / _| | | | #
1445 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
1446 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
1447 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
1448 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
1450 # _ __ ___ __| | ___ ___ #
1451 # | '_ \ / _ \ / _` |/ _ \/ __| #
1452 # | | | | (_) | (_| | __/\__ \ #
1453 # |_| |_|\___/ \__,_|\___||___/ #
1454 #----------------------------------------------------------#
1458 comment => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
1459 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1467 comment => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1468 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1476 cmp_attr => "return 1;",
1477 comment => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1483 comment => "virtual fp Sub: Sub(a, b) = a - b",
1484 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1491 cmp_attr => "return 1;",
1492 comment => "lowered virtual fp Sub: Sub(a, b) = a - b",
1497 comment => "virtual fp Div: Div(a, b) = a / b",
1498 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1499 outs => [ "res", "M" ],
1505 cmp_attr => "return 1;",
1506 comment => "lowered virtual fp Div: Div(a, b) = a / b",
1507 outs => [ "res", "M" ],
1512 comment => "virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1513 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1520 cmp_attr => "return 1;",
1521 comment => "lowered virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1527 comment => "virtual fp Abs: Abs(a) = |a|",
1528 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1536 comment => "virtual fp Chs: Chs(a) = -a",
1537 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1545 comment => "virtual fp Sin: Sin(a) = sin(a)",
1546 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1554 comment => "virtual fp Cos: Cos(a) = cos(a)",
1555 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1563 comment => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
1564 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1570 # virtual Load and Store
1574 state => "exc_pinned",
1575 comment => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
1576 reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] },
1577 outs => [ "res", "M" ],
1584 state => "exc_pinned",
1585 comment => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
1586 reg_req => { in => [ "gp", "gp", "vfp", "none" ] },
1595 comment => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1596 reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] },
1597 outs => [ "res", "M" ],
1603 cmp_attr => "return 1;",
1604 comment => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1605 outs => [ "res", "M" ],
1610 comment => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1611 reg_req => { in => [ "gp", "gp", "vfp", "fpcw", "none" ] },
1618 cmp_attr => "return 1;",
1619 comment => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1629 comment => "virtual fp Load 0.0: Ld 0.0 -> reg",
1630 reg_req => { out => [ "vfp" ] },
1638 comment => "virtual fp Load 1.0: Ld 1.0 -> reg",
1639 reg_req => { out => [ "vfp" ] },
1647 comment => "virtual fp Load pi: Ld pi -> reg",
1648 reg_req => { out => [ "vfp" ] },
1656 comment => "virtual fp Load ln 2: Ld ln 2 -> reg",
1657 reg_req => { out => [ "vfp" ] },
1665 comment => "virtual fp Load lg 2: Ld lg 2 -> reg",
1666 reg_req => { out => [ "vfp" ] },
1674 comment => "virtual fp Load ld 10: Ld ld 10 -> reg",
1675 reg_req => { out => [ "vfp" ] },
1683 comment => "virtual fp Load ld e: Ld ld e -> reg",
1684 reg_req => { out => [ "vfp" ] },
1693 # init_attr => " set_ia32_ls_mode(res, mode);",
1694 comment => "represents a virtual floating point constant",
1695 reg_req => { out => [ "vfp" ] },
1705 op_flags => "L|X|Y",
1706 comment => "represents a virtual floating point compare",
1707 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "none", "none", "eax" ] },
1708 outs => [ "false", "true", "temp_reg_eax" ],
1713 #------------------------------------------------------------------------#
1714 # ___ _____ __ _ _ _ #
1715 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1716 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1717 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1718 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1719 #------------------------------------------------------------------------#
1721 # Note: gas is strangely buggy: fdivrp and fdivp as well as fsubrp and fsubp
1722 # are swapped, we work this around in the emitter...
1726 rd_constructor => "NONE",
1727 comment => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1729 emit => '. fadd%XM %x87_binop',
1734 rd_constructor => "NONE",
1735 comment => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1737 emit => '. faddp %x87_binop',
1742 rd_constructor => "NONE",
1743 comment => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1745 emit => '. fmul%XM %x87_binop',
1750 rd_constructor => "NONE",
1751 comment => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1753 emit => '. fmulp %x87_binop',,
1758 rd_constructor => "NONE",
1759 comment => "x87 fp Sub: Sub(a, b) = a - b",
1761 emit => '. fsub%XM %x87_binop',
1766 rd_constructor => "NONE",
1767 comment => "x87 fp Sub: Sub(a, b) = a - b",
1769 # see note about gas bugs
1770 emit => '. fsubrp %x87_binop',
1775 rd_constructor => "NONE",
1777 comment => "x87 fp SubR: SubR(a, b) = b - a",
1779 emit => '. fsubr%XM %x87_binop',
1784 rd_constructor => "NONE",
1786 comment => "x87 fp SubR: SubR(a, b) = b - a",
1788 # see note about gas bugs
1789 emit => '. fsubp %x87_binop',
1794 rd_constructor => "NONE",
1795 comment => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1800 # this node is just here, to keep the simulator running
1801 # we can omit this when a fprem simulation function exists
1804 rd_constructor => "NONE",
1805 comment => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1812 rd_constructor => "NONE",
1813 comment => "x87 fp Div: Div(a, b) = a / b",
1815 emit => '. fdiv%XM %x87_binop',
1820 rd_constructor => "NONE",
1821 comment => "x87 fp Div: Div(a, b) = a / b",
1823 # see note about gas bugs
1824 emit => '. fdivrp %x87_binop',
1829 rd_constructor => "NONE",
1830 comment => "x87 fp DivR: DivR(a, b) = b / a",
1832 emit => '. fdivr%XM %x87_binop',
1837 rd_constructor => "NONE",
1838 comment => "x87 fp DivR: DivR(a, b) = b / a",
1840 # see note about gas bugs
1841 emit => '. fdivp %x87_binop',
1846 rd_constructor => "NONE",
1847 comment => "x87 fp Abs: Abs(a) = |a|",
1854 rd_constructor => "NONE",
1855 comment => "x87 fp Chs: Chs(a) = -a",
1862 rd_constructor => "NONE",
1863 comment => "x87 fp Sin: Sin(a) = sin(a)",
1870 rd_constructor => "NONE",
1871 comment => "x87 fp Cos: Cos(a) = cos(a)",
1878 rd_constructor => "NONE",
1879 comment => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1881 emit => '. fsqrt $',
1884 # x87 Load and Store
1887 rd_constructor => "NONE",
1888 op_flags => "R|L|F",
1889 state => "exc_pinned",
1890 comment => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1892 emit => '. fld%XM %AM',
1896 rd_constructor => "NONE",
1897 op_flags => "R|L|F",
1898 state => "exc_pinned",
1899 comment => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1901 emit => '. fst%XM %AM',
1906 rd_constructor => "NONE",
1907 op_flags => "R|L|F",
1908 state => "exc_pinned",
1909 comment => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1911 emit => '. fstp%XM %AM',
1919 rd_constructor => "NONE",
1920 comment => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1922 emit => '. fild%XM %AM',
1927 rd_constructor => "NONE",
1928 comment => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1930 emit => '. fist%XM %AM',
1936 rd_constructor => "NONE",
1937 comment => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1939 emit => '. fistp%XM %AM',
1946 op_flags => "R|c|K",
1948 comment => "x87 fp Load 0.0: Ld 0.0 -> reg",
1954 op_flags => "R|c|K",
1956 comment => "x87 fp Load 1.0: Ld 1.0 -> reg",
1962 op_flags => "R|c|K",
1964 comment => "x87 fp Load pi: Ld pi -> reg",
1970 op_flags => "R|c|K",
1972 comment => "x87 fp Load ln 2: Ld ln 2 -> reg",
1978 op_flags => "R|c|K",
1980 comment => "x87 fp Load lg 2: Ld lg 2 -> reg",
1986 op_flags => "R|c|K",
1988 comment => "x87 fp Load ld 10: Ld ld 10 -> reg",
1990 emit => '. fldll2t',
1994 op_flags => "R|c|K",
1996 comment => "x87 fp Load ld e: Ld ld e -> reg",
2002 # Note that it is NEVER allowed to do CSE on these nodes
2003 # Moreover, note the virtual register requierements!
2007 comment => "x87 stack exchange",
2009 cmp_attr => "return 1;",
2010 emit => '. fxch %X0',
2015 comment => "x87 stack push",
2017 cmp_attr => "return 1;",
2018 emit => '. fld %X0',
2023 comment => "x87 stack push",
2024 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
2025 cmp_attr => "return 1;",
2026 emit => '. fld %X0',
2031 comment => "x87 stack pop",
2033 cmp_attr => "return 1;",
2034 emit => '. fstp %X0',
2040 op_flags => "L|X|Y",
2041 comment => "floating point compare",
2046 op_flags => "L|X|Y",
2047 comment => "floating point compare and pop",
2052 op_flags => "L|X|Y",
2053 comment => "floating point compare and pop twice",
2058 op_flags => "L|X|Y",
2059 comment => "floating point compare reverse",
2064 op_flags => "L|X|Y",
2065 comment => "floating point compare reverse and pop",
2070 op_flags => "L|X|Y",
2071 comment => "floating point compare reverse and pop twice",
2076 # -------------------------------------------------------------------------------- #
2077 # ____ ____ _____ _ _ #
2078 # / ___/ ___|| ____| __ _____ ___| |_ ___ _ __ _ __ ___ __| | ___ ___ #
2079 # \___ \___ \| _| \ \ / / _ \/ __| __/ _ \| '__| | '_ \ / _ \ / _` |/ _ \/ __| #
2080 # ___) |__) | |___ \ V / __/ (__| || (_) | | | | | | (_) | (_| | __/\__ \ #
2081 # |____/____/|_____| \_/ \___|\___|\__\___/|_| |_| |_|\___/ \__,_|\___||___/ #
2083 # -------------------------------------------------------------------------------- #
2086 # Spilling and reloading of SSE registers, hardcoded, not generated #
2090 state => "exc_pinned",
2091 comment => "construct SSE Load: Load(ptr, mem) = LD ptr",
2092 reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none" ] },
2093 emit => '. movdqu %D0, %AM',
2094 outs => [ "res", "M" ],
2100 state => "exc_pinned",
2101 comment => "construct Store: Store(ptr, val, mem) = ST ptr,val",
2102 reg_req => { in => [ "gp", "gp", "xmm", "none" ] },
2103 emit => '. movdqu %binop',
2110 # Include the generated SIMD node specification written by the SIMD optimization
2111 $my_script_name = dirname($myname) . "/../ia32/ia32_simd_spec.pl";
2112 unless ($return = do $my_script_name) {
2113 warn "couldn't parse $my_script_name: $@" if $@;
2114 warn "couldn't do $my_script_name: $!" unless defined $return;
2115 warn "couldn't run $my_script_name" unless $return;