3 # This is the specification for the ia32 assembler Firm-operations
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
8 # this string marks the beginning of a comment in emit
9 $comment_string = "/*";
11 # the number of additional opcodes you want to register
12 #$additional_opcodes = 0;
14 # The node description is done as a perl hash initializer with the
15 # following structure:
20 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
21 # "irn_flags" => "R|N|I"
22 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
23 # "state" => "floats|pinned|mem_pinned|exc_pinned",
25 # { "type" => "type 1", "name" => "name 1" },
26 # { "type" => "type 2", "name" => "name 2" },
29 # "comment" => "any comment for constructor",
30 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
31 # "cmp_attr" => "c source code for comparing node attributes",
32 # "emit" => "emit code with templates",
33 # "attr" => "attitional attribute arguments for constructor"
34 # "init_attr" => "emit attribute initialization template"
35 # "rd_constructor" => "c source code which constructs an ir_node"
38 # ... # (all nodes you need to describe)
40 # ); # close the %nodes initializer
42 # op_flags: flags for the operation, OPTIONAL (default is "N")
43 # the op_flags correspond to the firm irop_flags:
46 # C irop_flag_commutative
47 # X irop_flag_cfopcode
48 # I irop_flag_ip_cfopcode
51 # H irop_flag_highlevel
52 # c irop_flag_constlike
55 # irn_flags: special node flags, OPTIONAL (default is 0)
56 # following irn_flags are supported:
59 # I ignore for register allocation
61 # state: state of the operation, OPTIONAL (default is "floats")
63 # arity: arity of the operation, MUST NOT BE OMITTED
65 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
66 # are always the first 3 arguments and are always autmatically
68 # If this key is missing the following arguments will be created:
69 # for i = 1 .. arity: ir_node *op_i
72 # outs: if a node defines more than one output, the names of the projections
73 # nodes having outs having automatically the mode mode_T
75 # comment: OPTIONAL comment for the node constructor
77 # rd_constructor: for every operation there will be a
78 # new_rd_<arch>_<op-name> function with the arguments from above
79 # which creates the ir_node corresponding to the defined operation
80 # you can either put the complete source code of this function here
82 # This key is OPTIONAL. If omitted, the following constructor will
84 # if (!op_<arch>_<op-name>) assert(0);
88 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
91 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
95 # 1 - caller save (register must be saved by the caller of a function)
96 # 2 - callee save (register must be saved by the called function)
97 # 4 - ignore (do not assign this register)
98 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
101 { "name" => "eax", "type" => 1 },
102 { "name" => "edx", "type" => 1 },
103 { "name" => "ebx", "type" => 2 },
104 { "name" => "ecx", "type" => 1 },
105 { "name" => "esi", "type" => 2 },
106 { "name" => "edi", "type" => 2 },
107 # { "name" => "r11", "type" => 1 },
108 # { "name" => "r12", "type" => 1 },
109 # { "name" => "r13", "type" => 1 },
110 # { "name" => "r14", "type" => 1 },
111 # { "name" => "r15", "type" => 1 },
112 # { "name" => "r16", "type" => 1 },
113 # { "name" => "r17", "type" => 1 },
114 # { "name" => "r18", "type" => 1 },
115 # { "name" => "r19", "type" => 1 },
116 # { "name" => "r20", "type" => 1 },
117 # { "name" => "r21", "type" => 1 },
118 # { "name" => "r22", "type" => 1 },
119 # { "name" => "r23", "type" => 1 },
120 # { "name" => "r24", "type" => 1 },
121 # { "name" => "r25", "type" => 1 },
122 # { "name" => "r26", "type" => 1 },
123 # { "name" => "r27", "type" => 1 },
124 # { "name" => "r28", "type" => 1 },
125 # { "name" => "r29", "type" => 1 },
126 # { "name" => "r30", "type" => 1 },
127 # { "name" => "r31", "type" => 1 },
128 # { "name" => "r32", "type" => 1 },
129 { "name" => "ebp", "type" => 2 },
130 { "name" => "esp", "type" => 4 },
131 { "name" => "gp_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
132 { "name" => "gp_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
133 { "mode" => "mode_P" }
136 { "name" => "xmm0", "type" => 1 },
137 { "name" => "xmm1", "type" => 1 },
138 { "name" => "xmm2", "type" => 1 },
139 { "name" => "xmm3", "type" => 1 },
140 { "name" => "xmm4", "type" => 1 },
141 { "name" => "xmm5", "type" => 1 },
142 { "name" => "xmm6", "type" => 1 },
143 { "name" => "xmm7", "type" => 1 },
144 { "name" => "xmm_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
145 { "name" => "xmm_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
146 { "mode" => "mode_D" }
149 { "name" => "vf0", "type" => 1 },
150 { "name" => "vf1", "type" => 1 },
151 { "name" => "vf2", "type" => 1 },
152 { "name" => "vf3", "type" => 1 },
153 { "name" => "vf4", "type" => 1 },
154 { "name" => "vf5", "type" => 1 },
155 { "name" => "vf6", "type" => 1 },
156 { "name" => "vf7", "type" => 1 },
157 { "name" => "vfp_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
158 { "name" => "vfp_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
159 { "mode" => "mode_E" }
162 { "name" => "st0", "type" => 1 },
163 { "name" => "st1", "type" => 1 },
164 { "name" => "st2", "type" => 1 },
165 { "name" => "st3", "type" => 1 },
166 { "name" => "st4", "type" => 1 },
167 { "name" => "st5", "type" => 1 },
168 { "name" => "st6", "type" => 1 },
169 { "name" => "st7", "type" => 1 },
170 { "mode" => "mode_E" }
174 #--------------------------------------------------#
177 # _ __ _____ __ _ _ __ ___ _ __ ___ #
178 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
179 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
180 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
183 #--------------------------------------------------#
190 #-----------------------------------------------------------------#
193 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
194 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
195 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
196 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
199 #-----------------------------------------------------------------#
201 # commutative operations
204 # All nodes supporting Addressmode have 5 INs:
205 # 1 - base r1 == NoReg in case of no AM or no base
206 # 2 - index r2 == NoReg in case of no AM or no index
207 # 3 - op1 r3 == always present
208 # 4 - op2 r4 == NoReg in case of immediate operation
209 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
213 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
214 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
215 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
216 "emit" => '. add %ia32_emit_binop /* Add(%A1, %A2) -> %D1 */',
217 "outs" => [ "res", "M" ],
222 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
223 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
224 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
225 "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */',
226 "outs" => [ "res", "M" ],
229 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
231 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
232 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
233 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r3", "edx in_r4" ] },
234 "emit" => '. imul %ia32_emit_binop /* Mulh(%A1, %A2) -> %D1 */',
235 "outs" => [ "EAX", "EDX", "M" ],
240 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
241 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
242 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
243 "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */',
244 "outs" => [ "res", "M" ],
249 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
250 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
251 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
252 "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */',
253 "outs" => [ "res", "M" ],
258 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
259 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
260 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
261 "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */',
262 "outs" => [ "res", "M" ],
267 "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
268 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
270 '2. cmp %S1, %S2 /* prepare Max (%S1 - %S2), (%A1, %A2) */
271 if (mode_is_signed(get_irn_mode(n))) {
272 4. cmovl %D1, %S2 /* %S1 is less %S2 */
275 4. cmovb %D1, %S2 /* %S1 is below %S2 */
282 "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
283 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
285 '2. cmp %S1, %S2 /* prepare Min (%S1 - %S2), (%A1, %A2) */
286 if (mode_is_signed(get_irn_mode(n))) {
287 2. cmovg %D1, %S2 /* %S1 is greater %S2 */
290 2. cmova %D1, %S2, %D1 /* %S1 is above %S2 */
297 "comment" => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
298 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "in_r4" ] }
303 "comment" => "construct Set: Set(sel) == sel ? 1 : 0",
304 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "eax ebx ecx edx" ] },
307 # not commutative operations
311 "comment" => "construct Sub: Sub(a, b) = a - b",
312 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
313 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
314 "emit" => '. sub %ia32_emit_binop /* Sub(%A1, %A2) -> %D1 */',
315 "outs" => [ "res", "M" ],
320 "state" => "exc_pinned",
321 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "eax in_r1", "edx in_r3" ] },
322 "attr" => "ia32_op_flavour_t dm_flav",
323 "init_attr" => " attr->data.op_flav = dm_flav;",
324 "cmp_attr" => " return attr_a->data.op_flav != attr_b->data.op_flav;\n",
326 ' if (mode_is_signed(get_irn_mode(n))) {
327 4. idiv %S2 /* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
330 4. div %S2 /* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
333 "outs" => [ "div_res", "mod_res", "M" ],
338 "comment" => "construct Shl: Shl(a, b) = a << b",
339 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
340 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
341 "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */',
342 "outs" => [ "res", "M" ],
347 "comment" => "construct Shr: Shr(a, b) = a >> b",
348 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
349 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
350 "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */',
351 "outs" => [ "res", "M" ],
356 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
357 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
358 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
359 "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */',
360 "outs" => [ "res", "M" ],
365 "comment" => "construct RotR: RotR(a, b) = a ROTR b",
366 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
367 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
368 "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */',
369 "outs" => [ "res", "M" ],
374 "comment" => "construct RotL: RotL(a, b) = a ROTL b",
375 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
376 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
377 "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */',
378 "outs" => [ "res", "M" ],
385 "comment" => "construct Minus: Minus(a) = -a",
386 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
387 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
388 "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */',
389 "outs" => [ "res", "M" ],
394 "comment" => "construct Increment: Inc(a) = a++",
395 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
396 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
397 "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */',
398 "outs" => [ "res", "M" ],
403 "comment" => "construct Decrement: Dec(a) = a--",
404 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
405 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
406 "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */',
407 "outs" => [ "res", "M" ],
412 "comment" => "construct Not: Not(a) = !a",
413 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
414 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
415 "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */',
416 "outs" => [ "res", "M" ],
422 "op_flags" => "L|X|Y",
423 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
424 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
425 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
426 "outs" => [ "false", "true" ],
430 "op_flags" => "L|X|Y",
431 "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
432 "reg_req" => { "in" => [ "gp", "gp" ] },
433 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
434 "outs" => [ "false", "true" ],
438 "op_flags" => "L|X|Y",
439 "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
440 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
441 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
442 "outs" => [ "false", "true" ],
446 "op_flags" => "L|X|Y",
447 "comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
448 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
449 "reg_req" => { "in" => [ "gp", "gp" ] },
453 "op_flags" => "L|X|Y",
454 "comment" => "construct switch",
455 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
456 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
462 "comment" => "represents an integer constant",
463 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
464 "reg_req" => { "in" => [ "none" ], "out" => [ "gp" ] },
469 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
470 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
471 "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */',
472 "outs" => [ "EAX", "EDX" ],
480 "state" => "exc_pinned",
481 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
482 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
483 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
485 ' if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) {
486 4. mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
489 4. mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
492 "outs" => [ "res", "M" ],
497 "state" => "exc_pinned",
498 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
499 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
500 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
501 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
507 "state" => "exc_pinned",
508 "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
509 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
510 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
511 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
517 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
518 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
519 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
520 "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */'
524 "comment" => "push a gp register on the stack",
525 "reg_req" => { "in" => [ "esp", "gp", "none" ], "out" => [ "esp" ] },
527 if (get_ia32_id_cnst(n)) {
528 if (get_ia32_immop_type(n) == ia32_ImmConst) {
529 . push %C /* Push(%A2) */
531 . push OFFSET FLAT:%C /* Push(%A2) */
535 . push %S2 /* Push(%A2) */
538 "outs" => [ "stack", "M" ],
542 "comment" => "pop a gp register from the stack",
543 "reg_req" => { "in" => [ "esp", "none" ], "out" => [ "gp", "esp" ] },
544 "emit" => '. pop %D1 /* Pop -> %D1 */',
545 "outs" => [ "res", "stack", "M" ],
549 "comment" => "create stack frame",
550 "reg_req" => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] },
551 "emit" => '. enter /* Enter */',
552 "outs" => [ "frame", "stack", "M" ],
556 "comment" => "destroy stack frame",
557 "reg_req" => { "in" => [ "esp", "ebp" ], "out" => [ "ebp", "esp" ] },
558 "emit" => '. leave /* Leave */',
559 "outs" => [ "frame", "stack", "M" ],
562 #-----------------------------------------------------------------------------#
563 # _____ _____ ______ __ _ _ _ #
564 # / ____/ ____| ____| / _| | | | | | #
565 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
566 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
567 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
568 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
569 #-----------------------------------------------------------------------------#
571 # commutative operations
575 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
576 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
577 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
578 "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */',
579 "outs" => [ "res", "M" ],
584 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
585 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
586 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
587 "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */',
588 "outs" => [ "res", "M" ],
593 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
594 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
595 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
596 "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */',
597 "outs" => [ "res", "M" ],
602 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
603 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
604 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
605 "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */',
606 "outs" => [ "res", "M" ],
611 "comment" => "construct SSE And: And(a, b) = a AND b",
612 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
613 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
614 "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */',
615 "outs" => [ "res", "M" ],
620 "comment" => "construct SSE Or: Or(a, b) = a OR b",
621 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
622 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
623 "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */',
624 "outs" => [ "res", "M" ],
629 "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
630 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
631 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
632 "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */',
633 "outs" => [ "res", "M" ],
636 # not commutative operations
640 "comment" => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
641 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
642 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
643 "emit" => '. andnp%M %ia32_emit_binop /* SSE AndNot(%A3, %A4) -> %D1 */',
644 "outs" => [ "res", "M" ],
649 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
650 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
651 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
652 "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */',
653 "outs" => [ "res", "M" ],
658 "comment" => "construct SSE Div: Div(a, b) = a / b",
659 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
660 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
661 "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */',
662 "outs" => [ "res", "M" ],
669 "comment" => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
670 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
671 "outs" => [ "res", "M" ],
675 "op_flags" => "L|X|Y",
676 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
677 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
678 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
679 "outs" => [ "false", "true" ],
685 "comment" => "represents a SSE constant",
686 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
687 "reg_req" => { "in" => [ "none" ], "out" => [ "xmm" ] },
688 "emit" => '. movs%M %D1, %C /* Load fConst into register */',
696 "state" => "exc_pinned",
697 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
698 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
699 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm" ] },
700 "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */',
701 "outs" => [ "res", "M" ],
706 "state" => "exc_pinned",
707 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
708 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
709 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
710 "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */',
719 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
720 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "none" ] },
726 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
727 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
728 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "none" ] },
734 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
735 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
736 "comment" => "construct Conv Int -> Int",
737 "outs" => [ "res", "M" ],
741 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
742 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
743 "comment" => "construct Conv Int -> Int",
744 "outs" => [ "res", "M" ],
748 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
749 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
750 "comment" => "construct Conv Int -> Floating Point",
751 "outs" => [ "res", "M" ],
755 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
756 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
757 "comment" => "construct Conv Floating Point -> Int",
758 "outs" => [ "res", "M" ],
762 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
763 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
764 "comment" => "construct Conv Floating Point -> Floating Point",
765 "outs" => [ "res", "M" ],
768 #----------------------------------------------------------#
770 # (_) | | | | / _| | | | #
771 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
772 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
773 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
774 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
776 # _ __ ___ __| | ___ ___ #
777 # | '_ \ / _ \ / _` |/ _ \/ __| #
778 # | | | | (_) | (_| | __/\__ \ #
779 # |_| |_|\___/ \__,_|\___||___/ #
780 #----------------------------------------------------------#
784 "comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
785 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
786 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
787 "outs" => [ "res", "M" ],
792 "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a + b",
793 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
794 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
795 "outs" => [ "res", "M" ],
800 "comment" => "virtual fp Sub: Sub(a, b) = a - b",
801 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
802 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
803 "outs" => [ "res", "M" ],
807 "comment" => "virtual fp Div: Div(a, b) = a / b",
808 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
809 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
810 "outs" => [ "res", "M" ],
815 "comment" => "virtual fp Abs: Abs(a) = |a|",
816 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
821 "comment" => "virtual fp Chs: Chs(a) = -a",
822 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
827 "comment" => "virtual fp Sin: Sin(a) = sin(a)",
828 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
833 "comment" => "virtual fp Cos: Cos(a) = cos(a)",
834 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
839 "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
840 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
843 # virtual Load and Store
848 "state" => "exc_pinned",
849 "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
850 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
851 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
852 "outs" => [ "res", "M" ],
857 "state" => "exc_pinned",
858 "comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
859 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
860 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
868 "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
869 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
870 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
871 "outs" => [ "res", "M" ],
875 "comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
876 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
877 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
885 "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg",
886 "reg_req" => { "out" => [ "vfp" ] },
891 "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg",
892 "reg_req" => { "out" => [ "vfp" ] },
897 "comment" => "virtual fp Load pi: Ld pi -> reg",
898 "reg_req" => { "out" => [ "vfp" ] },
903 "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg",
904 "reg_req" => { "out" => [ "vfp" ] },
909 "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg",
910 "reg_req" => { "out" => [ "vfp" ] },
915 "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg",
916 "reg_req" => { "out" => [ "vfp" ] },
921 "comment" => "virtual fp Load ld e: Ld ld e -> reg",
922 "reg_req" => { "out" => [ "vfp" ] },
928 "init_attr" => " set_ia32_ls_mode(res, mode);",
929 "comment" => "represents a virtual floating point constant",
930 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
931 "reg_req" => { "in" => [ "none" ], "out" => [ "vfp" ] },
937 "op_flags" => "L|X|Y",
938 "comment" => "represents a virtual floating point compare",
939 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
940 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] },
941 "outs" => [ "false", "true", "temp_reg_eax" ],
944 #------------------------------------------------------------------------#
945 # ___ _____ __ _ _ _ #
946 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
947 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
948 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
949 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
950 #------------------------------------------------------------------------#
954 "rd_constructor" => "NONE",
955 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
957 "emit" => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */',
962 "rd_constructor" => "NONE",
963 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
965 "emit" => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */',
970 "rd_constructor" => "NONE",
971 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
973 "emit" => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */',
978 "rd_constructor" => "NONE",
979 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
981 "emit" => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */',,
986 "rd_constructor" => "NONE",
987 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
989 "emit" => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */',
994 "rd_constructor" => "NONE",
995 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
997 "emit" => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */',
1002 "rd_constructor" => "NONE",
1004 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1006 "emit" => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */',
1011 "rd_constructor" => "NONE",
1013 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1015 "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */',
1020 "rd_constructor" => "NONE",
1021 "comment" => "x87 fp Div: Div(a, b) = a / b",
1023 "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */',
1028 "rd_constructor" => "NONE",
1029 "comment" => "x87 fp Div: Div(a, b) = a / b",
1031 "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */',
1036 "rd_constructor" => "NONE",
1037 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1039 "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */',
1044 "rd_constructor" => "NONE",
1045 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1047 "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */',
1052 "rd_constructor" => "NONE",
1053 "comment" => "x87 fp Abs: Abs(a) = |a|",
1055 "emit" => '. fabs /* x87 fabs(%S1) -> %D1 */',
1060 "rd_constructor" => "NONE",
1061 "comment" => "x87 fp Chs: Chs(a) = -a",
1063 "emit" => '. fchs /* x87 fchs(%S1) -> %D1 */',
1068 "rd_constructor" => "NONE",
1069 "comment" => "x87 fp Sin: Sin(a) = sin(a)",
1071 "emit" => '. fsin /* x87 sin(%S1) -> %D1 */',
1076 "rd_constructor" => "NONE",
1077 "comment" => "x87 fp Cos: Cos(a) = cos(a)",
1079 "emit" => '. fcos /* x87 cos(%S1) -> %D1 */',
1084 "rd_constructor" => "NONE",
1085 "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1087 "emit" => '. fsqrt $ /* x87 sqrt(%S1) -> %D1 */',
1090 # x87 Load and Store
1093 "rd_constructor" => "NONE",
1094 "op_flags" => "R|L|F",
1095 "state" => "exc_pinned",
1096 "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1098 "emit" => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */',
1102 "rd_constructor" => "NONE",
1103 "op_flags" => "R|L|F",
1104 "state" => "exc_pinned",
1105 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1107 "emit" => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */',
1111 "rd_constructor" => "NONE",
1112 "op_flags" => "R|L|F",
1113 "state" => "exc_pinned",
1114 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1116 "emit" => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */',
1124 "rd_constructor" => "NONE",
1125 "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1127 "emit" => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */',
1132 "rd_constructor" => "NONE",
1133 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1135 "emit" => '. fist %ia32_emit_am /* integer Store(%A3) -> (%A1) */',
1140 "rd_constructor" => "NONE",
1141 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1143 "emit" => '. fistp %ia32_emit_am /* integer Store(%A3) -> (%A1) and pop */',
1150 "rd_constructor" => "NONE",
1151 "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
1153 "emit" => '. fldz /* x87 0.0 -> %D1 */',
1158 "rd_constructor" => "NONE",
1159 "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
1161 "emit" => '. fld1 /* x87 1.0 -> %D1 */',
1166 "rd_constructor" => "NONE",
1167 "comment" => "x87 fp Load pi: Ld pi -> reg",
1169 "emit" => '. fldpi /* x87 pi -> %D1 */',
1174 "rd_constructor" => "NONE",
1175 "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
1177 "emit" => '. fldln2 /* x87 ln(2) -> %D1 */',
1182 "rd_constructor" => "NONE",
1183 "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
1185 "emit" => '. fldlg2 /* x87 log(2) -> %D1 */',
1190 "rd_constructor" => "NONE",
1191 "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
1193 "emit" => '. fldll2t /* x87 ld(10) -> %D1 */',
1198 "rd_constructor" => "NONE",
1199 "comment" => "x87 fp Load ld e: Ld ld e -> reg",
1201 "emit" => '. fldl2e /* x87 ld(e) -> %D1 */',
1205 "op_flags" => "R|c",
1207 "rd_constructor" => "NONE",
1208 "comment" => "represents a x87 constant",
1209 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1210 "reg_req" => { "out" => [ "st" ] },
1211 "emit" => '. fld %ia32_emit_adr /* Load fConst into register -> %D1 */',
1215 # Note that it is NEVER allowed to do CSE on these nodes
1218 "op_flags" => "R|K",
1219 "comment" => "x87 stack exchange",
1220 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1221 "cmp_attr" => " return 1;\n",
1222 "emit" => '. fxch %X1 /* x87 swap %X1, %X3 */',
1227 "comment" => "x87 stack push",
1228 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1229 "cmp_attr" => " return 1;\n",
1230 "emit" => '. fld %X1 /* x87 push %X1 */',
1234 "op_flags" => "R|K",
1235 "comment" => "x87 stack pop",
1236 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1237 "cmp_attr" => " return 1;\n",
1238 "emit" => '. fstp %X1 /* x87 pop %X1 */',
1244 "op_flags" => "L|X|Y",
1245 "comment" => "floating point compare",
1246 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1251 "op_flags" => "L|X|Y",
1252 "comment" => "floating point compare and pop",
1253 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1258 "op_flags" => "L|X|Y",
1259 "comment" => "floating point compare and pop twice",
1260 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1265 "op_flags" => "L|X|Y",
1266 "comment" => "floating point compare reverse",
1267 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1272 "op_flags" => "L|X|Y",
1273 "comment" => "floating point compare reverse and pop",
1274 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1279 "op_flags" => "L|X|Y",
1280 "comment" => "floating point compare reverse and pop twice",
1281 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",