3 # This is the specification for the ia32 assembler Firm-operations
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
8 # this string marks the beginning of a comment in emit
9 $comment_string = "/*";
11 # the number of additional opcodes you want to register
12 #$additional_opcodes = 0;
14 # The node description is done as a perl hash initializer with the
15 # following structure:
20 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
21 # "irn_flags" => "R|N|I|S"
22 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
23 # "state" => "floats|pinned|mem_pinned|exc_pinned",
25 # { "type" => "type 1", "name" => "name 1" },
26 # { "type" => "type 2", "name" => "name 2" },
29 # "comment" => "any comment for constructor",
30 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
31 # "cmp_attr" => "c source code for comparing node attributes",
32 # "emit" => "emit code with templates",
33 # "attr" => "attitional attribute arguments for constructor"
34 # "init_attr" => "emit attribute initialization template"
35 # "rd_constructor" => "c source code which constructs an ir_node"
38 # ... # (all nodes you need to describe)
40 # ); # close the %nodes initializer
42 # op_flags: flags for the operation, OPTIONAL (default is "N")
43 # the op_flags correspond to the firm irop_flags:
46 # C irop_flag_commutative
47 # X irop_flag_cfopcode
48 # I irop_flag_ip_cfopcode
51 # H irop_flag_highlevel
52 # c irop_flag_constlike
55 # irn_flags: special node flags, OPTIONAL (default is 0)
56 # following irn_flags are supported:
59 # I ignore for register allocation
60 # S modifies stack pointer
62 # state: state of the operation, OPTIONAL (default is "floats")
64 # arity: arity of the operation, MUST NOT BE OMITTED
66 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
67 # are always the first 3 arguments and are always autmatically
69 # If this key is missing the following arguments will be created:
70 # for i = 1 .. arity: ir_node *op_i
73 # outs: if a node defines more than one output, the names of the projections
74 # nodes having outs having automatically the mode mode_T
76 # comment: OPTIONAL comment for the node constructor
78 # rd_constructor: for every operation there will be a
79 # new_rd_<arch>_<op-name> function with the arguments from above
80 # which creates the ir_node corresponding to the defined operation
81 # you can either put the complete source code of this function here
83 # This key is OPTIONAL. If omitted, the following constructor will
85 # if (!op_<arch>_<op-name>) assert(0);
89 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
92 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
96 # 1 - caller save (register must be saved by the caller of a function)
97 # 2 - callee save (register must be saved by the called function)
98 # 4 - ignore (do not assign this register)
99 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
102 { "name" => "eax", "type" => 1 },
103 { "name" => "edx", "type" => 1 },
104 { "name" => "ebx", "type" => 2 },
105 { "name" => "ecx", "type" => 1 },
106 { "name" => "esi", "type" => 2 },
107 { "name" => "edi", "type" => 2 },
108 # { "name" => "r11", "type" => 1 },
109 # { "name" => "r12", "type" => 1 },
110 # { "name" => "r13", "type" => 1 },
111 # { "name" => "r14", "type" => 1 },
112 # { "name" => "r15", "type" => 1 },
113 # { "name" => "r16", "type" => 1 },
114 # { "name" => "r17", "type" => 1 },
115 # { "name" => "r18", "type" => 1 },
116 # { "name" => "r19", "type" => 1 },
117 # { "name" => "r20", "type" => 1 },
118 # { "name" => "r21", "type" => 1 },
119 # { "name" => "r22", "type" => 1 },
120 # { "name" => "r23", "type" => 1 },
121 # { "name" => "r24", "type" => 1 },
122 # { "name" => "r25", "type" => 1 },
123 # { "name" => "r26", "type" => 1 },
124 # { "name" => "r27", "type" => 1 },
125 # { "name" => "r28", "type" => 1 },
126 # { "name" => "r29", "type" => 1 },
127 # { "name" => "r30", "type" => 1 },
128 # { "name" => "r31", "type" => 1 },
129 # { "name" => "r32", "type" => 1 },
130 { "name" => "ebp", "type" => 2 },
131 { "name" => "esp", "type" => 4 },
132 { "name" => "gp_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
133 { "name" => "gp_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
134 { "mode" => "mode_P" }
137 { "name" => "xmm0", "type" => 1 },
138 { "name" => "xmm1", "type" => 1 },
139 { "name" => "xmm2", "type" => 1 },
140 { "name" => "xmm3", "type" => 1 },
141 { "name" => "xmm4", "type" => 1 },
142 { "name" => "xmm5", "type" => 1 },
143 { "name" => "xmm6", "type" => 1 },
144 { "name" => "xmm7", "type" => 1 },
145 { "name" => "xmm_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
146 { "name" => "xmm_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
147 { "mode" => "mode_D" }
150 { "name" => "vf0", "type" => 1 },
151 { "name" => "vf1", "type" => 1 },
152 { "name" => "vf2", "type" => 1 },
153 { "name" => "vf3", "type" => 1 },
154 { "name" => "vf4", "type" => 1 },
155 { "name" => "vf5", "type" => 1 },
156 { "name" => "vf6", "type" => 1 },
157 { "name" => "vf7", "type" => 1 },
158 { "name" => "vfp_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
159 { "name" => "vfp_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
160 { "mode" => "mode_E" }
163 { "name" => "st0", "type" => 1 },
164 { "name" => "st1", "type" => 1 },
165 { "name" => "st2", "type" => 1 },
166 { "name" => "st3", "type" => 1 },
167 { "name" => "st4", "type" => 1 },
168 { "name" => "st5", "type" => 1 },
169 { "name" => "st6", "type" => 1 },
170 { "name" => "st7", "type" => 1 },
171 { "mode" => "mode_E" }
175 #--------------------------------------------------#
178 # _ __ _____ __ _ _ __ ___ _ __ ___ #
179 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
180 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
181 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
184 #--------------------------------------------------#
191 #-----------------------------------------------------------------#
194 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
195 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
196 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
197 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
200 #-----------------------------------------------------------------#
202 # commutative operations
205 # All nodes supporting Addressmode have 5 INs:
206 # 1 - base r1 == NoReg in case of no AM or no base
207 # 2 - index r2 == NoReg in case of no AM or no index
208 # 3 - op1 r3 == always present
209 # 4 - op2 r4 == NoReg in case of immediate operation
210 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
214 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
215 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
216 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
217 "emit" => '. add %ia32_emit_binop /* Add(%A3, %A4) -> %D1 */',
218 "outs" => [ "res", "M" ],
222 "comment" => "construct Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
223 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
224 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
225 "emit" => '. adc %ia32_emit_binop /* AddC(%A3, %A4) -> %D1 */',
226 "outs" => [ "res", "M" ],
232 "cmp_attr" => " return 1;\n",
233 "comment" => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
239 "cmp_attr" => " return 1;\n",
240 "comment" => "construct lowered Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
245 "comment" => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
246 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
247 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] },
248 "emit" => '. mul %ia32_emit_unop /* Mul(%A1, %A2) -> %D1 */',
249 "outs" => [ "EAX", "EDX", "M" ],
254 "cmp_attr" => " return 1;\n",
255 "comment" => "construct lowered MulS: MulS(a, b) = MulS(b, a) = a * b",
256 "outs" => [ "EAX", "EDX", "M" ],
262 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
263 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
264 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
265 "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */',
266 "outs" => [ "res", "M" ],
271 "cmp_attr" => " return 1;\n",
272 "comment" => "construct lowered Mul: Mul(a, b) = Mul(b, a) = a * b",
276 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
278 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
279 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
280 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] },
281 "emit" => '. imul %ia32_emit_unop /* Mulh(%A1, %A2) -> %D1 */',
282 "outs" => [ "EAX", "EDX", "M" ],
287 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
288 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
289 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
290 "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */',
291 "outs" => [ "res", "M" ],
296 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
297 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
298 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
299 "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */',
300 "outs" => [ "res", "M" ],
305 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
306 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
307 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
308 "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */',
309 "outs" => [ "res", "M" ],
314 "cmp_attr" => " return 1;\n",
315 "comment" => "construct lowered Eor: Eor(a, b) = Eor(b, a) = a EOR b",
321 "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
322 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
324 '2. cmp %S1, %S2 /* prepare Max (%S1 - %S2), (%A1, %A2) */
325 if (mode_is_signed(get_irn_mode(n))) {
326 4. cmovl %D1, %S2 /* %S1 is less %S2 */
329 4. cmovb %D1, %S2 /* %S1 is below %S2 */
336 "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
337 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
339 '2. cmp %S1, %S2 /* prepare Min (%S1 - %S2), (%A1, %A2) */
340 if (mode_is_signed(get_irn_mode(n))) {
341 2. cmovg %D1, %S2 /* %S1 is greater %S2 */
344 2. cmova %D1, %S2, %D1 /* %S1 is above %S2 */
349 # not commutative operations
353 "comment" => "construct Sub: Sub(a, b) = a - b",
354 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
355 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
356 "emit" => '. sub %ia32_emit_binop /* Sub(%A3, %A4) -> %D1 */',
357 "outs" => [ "res", "M" ],
361 "comment" => "construct Sub with Carry: SubC(a, b) = a - b - carry",
362 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
363 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
364 "emit" => '. sbb %ia32_emit_binop /* SubC(%A3, %A4) -> %D1 */',
365 "outs" => [ "res", "M" ],
370 "cmp_attr" => " return 1;\n",
371 "comment" => "construct lowered Sub: Sub(a, b) = a - b",
376 "cmp_attr" => " return 1;\n",
377 "comment" => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
383 "state" => "exc_pinned",
384 "reg_req" => { "in" => [ "eax", "gp", "edx", "none" ], "out" => [ "eax", "edx" ] },
385 "attr" => "ia32_op_flavour_t dm_flav",
386 "init_attr" => " attr->data.op_flav = dm_flav;",
387 "cmp_attr" => " return attr_a->data.op_flav != attr_b->data.op_flav;\n",
389 ' if (mode_is_signed(get_ia32_res_mode(n))) {
390 4. idiv %S2 /* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
393 4. div %S2 /* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
396 "outs" => [ "div_res", "mod_res", "M" ],
401 "comment" => "construct Shl: Shl(a, b) = a << b",
402 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
403 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
404 "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */',
405 "outs" => [ "res", "M" ],
409 "cmp_attr" => " return 1;\n",
410 "comment" => "construct lowered Shl: Shl(a, b) = a << b",
416 "comment" => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
417 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
418 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r5" ] },
421 if (get_ia32_immop_type(n) == ia32_ImmNone) {
422 if (get_ia32_op_type(n) == ia32_AddrModeD) {
423 4. shld %ia32_emit_am, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
426 4. shld %S3, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
430 if (get_ia32_op_type(n) == ia32_AddrModeD) {
431 4. shld %ia32_emit_am, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
434 4. shld %S3, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
438 "outs" => [ "res", "M" ],
442 "cmp_attr" => " return 1;\n",
443 "comment" => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
449 "comment" => "construct Shr: Shr(a, b) = a >> b",
450 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
451 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
452 "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */',
453 "outs" => [ "res", "M" ],
457 "cmp_attr" => " return 1;\n",
458 "comment" => "construct lowered Shr: Shr(a, b) = a << b",
464 "comment" => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
465 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
466 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r5" ] },
469 if (get_ia32_immop_type(n) == ia32_ImmNone) {
470 if (get_ia32_op_type(n) == ia32_AddrModeD) {
471 4. shrd %ia32_emit_am, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
474 4. shrd %S3, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
478 if (get_ia32_op_type(n) == ia32_AddrModeD) {
479 4. shrd %ia32_emit_am, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
482 4. shrd %S3, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
486 "outs" => [ "res", "M" ],
490 "cmp_attr" => " return 1;\n",
491 "comment" => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
497 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
498 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
499 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
500 "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */',
501 "outs" => [ "res", "M" ],
505 "cmp_attr" => " return 1;\n",
506 "comment" => "construct lowered Shrs: Shrs(a, b) = a << b",
512 "comment" => "construct RotR: RotR(a, b) = a ROTR b",
513 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
514 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
515 "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */',
516 "outs" => [ "res", "M" ],
521 "comment" => "construct RotL: RotL(a, b) = a ROTL b",
522 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
523 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
524 "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */',
525 "outs" => [ "res", "M" ],
532 "comment" => "construct Minus: Minus(a) = -a",
533 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
534 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
535 "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */',
536 "outs" => [ "res", "M" ],
540 "cmp_attr" => " return 1;\n",
541 "comment" => "construct lowered Minus: Minus(a) = -a",
547 "comment" => "construct Increment: Inc(a) = a++",
548 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
549 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
550 "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */',
551 "outs" => [ "res", "M" ],
556 "comment" => "construct Decrement: Dec(a) = a--",
557 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
558 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
559 "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */',
560 "outs" => [ "res", "M" ],
565 "comment" => "construct Not: Not(a) = !a",
566 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
567 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
568 "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */',
569 "outs" => [ "res", "M" ],
575 "op_flags" => "L|X|Y",
576 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
577 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
578 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
579 "outs" => [ "false", "true" ],
583 "op_flags" => "L|X|Y",
584 "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
585 "reg_req" => { "in" => [ "gp", "gp" ] },
586 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
587 "outs" => [ "false", "true" ],
591 "op_flags" => "L|X|Y",
592 "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
593 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
594 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
595 "outs" => [ "false", "true" ],
599 "op_flags" => "L|X|Y",
600 "comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
601 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
602 "reg_req" => { "in" => [ "gp", "gp" ] },
606 "op_flags" => "L|X|Y",
607 "comment" => "construct switch",
608 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
609 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
615 "comment" => "represents an integer constant",
616 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
617 "reg_req" => { "in" => [ "none" ], "out" => [ "gp" ] },
622 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
623 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
624 "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */',
625 "outs" => [ "EAX", "EDX" ],
632 "state" => "exc_pinned",
633 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
634 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
635 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
637 ' if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) {
638 4. mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
641 4. mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
644 "outs" => [ "res", "M" ],
649 "cmp_attr" => " return 1;\n",
650 "comment" => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg",
651 "outs" => [ "res", "M" ],
657 "cmp_attr" => " return 1;\n",
658 "state" => "exc_pinned",
659 "comment" => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val",
666 "state" => "exc_pinned",
667 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
668 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
669 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
670 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
676 "state" => "exc_pinned",
677 "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
678 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
679 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
680 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
686 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
687 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
688 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
689 "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */'
693 "comment" => "push a gp register on the stack",
694 "reg_req" => { "in" => [ "esp", "gp", "none" ], "out" => [ "esp" ] },
696 if (get_ia32_id_cnst(n)) {
697 if (get_ia32_immop_type(n) == ia32_ImmConst) {
698 4. push %C /* Push const on stack */
700 4. push OFFSET FLAT:%C /* Push symconst on stack */
703 else if (get_ia32_op_type(n) == ia32_Normal) {
704 2. push %S2 /* Push(%A2) */
707 2. push %ia32_emit_am /* Push memory to stack */
710 "outs" => [ "stack", "M" ],
714 "comment" => "pop a gp register from the stack",
715 "reg_req" => { "in" => [ "esp", "none" ], "out" => [ "gp", "esp" ] },
717 if (get_ia32_op_type(n) == ia32_Normal) {
718 2. pop %D1 /* Pop from stack into %D1 */
721 2. pop %ia32_emit_am /* Pop from stack into memory */
724 "outs" => [ "res", "stack", "M" ],
728 "comment" => "create stack frame",
729 "reg_req" => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] },
730 "emit" => '. enter /* Enter */',
731 "outs" => [ "frame", "stack", "M" ],
735 "comment" => "destroy stack frame",
736 "reg_req" => { "in" => [ "esp", "ebp" ], "out" => [ "ebp", "esp" ] },
737 "emit" => '. leave /* Leave */',
738 "outs" => [ "frame", "stack", "M" ],
742 "irn_flags" => "S|I",
743 "comment" => "allocate space on stack",
744 "reg_req" => { "in" => [ "esp", "gp" ], "out" => [ "esp", "none" ] },
745 "outs" => [ "stack", "M" ],
748 #-----------------------------------------------------------------------------#
749 # _____ _____ ______ __ _ _ _ #
750 # / ____/ ____| ____| / _| | | | | | #
751 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
752 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
753 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
754 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
755 #-----------------------------------------------------------------------------#
757 # commutative operations
761 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
762 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
763 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
764 "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */',
765 "outs" => [ "res", "M" ],
770 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
771 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
772 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
773 "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */',
774 "outs" => [ "res", "M" ],
779 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
780 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
781 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
782 "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */',
783 "outs" => [ "res", "M" ],
788 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
789 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
790 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
791 "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */',
792 "outs" => [ "res", "M" ],
797 "comment" => "construct SSE And: And(a, b) = a AND b",
798 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
799 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
800 "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */',
801 "outs" => [ "res", "M" ],
806 "comment" => "construct SSE Or: Or(a, b) = a OR b",
807 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
808 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
809 "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */',
810 "outs" => [ "res", "M" ],
815 "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
816 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
817 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
818 "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */',
819 "outs" => [ "res", "M" ],
822 # not commutative operations
826 "comment" => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
827 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
828 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
829 "emit" => '. andnp%M %ia32_emit_binop /* SSE AndNot(%A3, %A4) -> %D1 */',
830 "outs" => [ "res", "M" ],
835 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
836 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
837 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
838 "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */',
839 "outs" => [ "res", "M" ],
844 "comment" => "construct SSE Div: Div(a, b) = a / b",
845 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
846 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
847 "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */',
848 "outs" => [ "res", "M" ],
855 "comment" => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
856 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
857 "outs" => [ "res", "M" ],
861 "op_flags" => "L|X|Y",
862 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
863 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
864 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
865 "outs" => [ "false", "true" ],
871 "comment" => "represents a SSE constant",
872 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
873 "reg_req" => { "in" => [ "none" ], "out" => [ "xmm" ] },
874 "emit" => '. movs%M %D1, %C /* Load fConst into register */',
881 "state" => "exc_pinned",
882 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
883 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
884 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm" ] },
885 "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */',
886 "outs" => [ "res", "M" ],
891 "state" => "exc_pinned",
892 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
893 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
894 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
895 "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */',
901 "state" => "exc_pinned",
902 "comment" => "construct Store without index: Store(ptr, val, mem) = ST ptr,val",
903 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
904 "reg_req" => { "in" => [ "gp", "xmm", "none" ] },
905 "emit" => '. movs%M %ia32_emit_am, %S2 /* store XMM0 onto stack */',
911 "comment" => "construct: transfer a value from x87 FPU into a SSE register",
912 "cmp_attr" => " return 1;\n",
918 "comment" => "construct: transfer a value from SSE register to x87 FPU",
919 "cmp_attr" => " return 1;\n",
926 "state" => "exc_pinned",
927 "comment" => "store ST0 onto stack",
928 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
929 "reg_req" => { "in" => [ "gp", "none" ] },
930 "emit" => '. fstp %ia32_emit_am /* store ST0 onto stack */',
937 "state" => "exc_pinned",
938 "comment" => "load ST0 from stack",
939 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
940 "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "st0", "none" ] },
941 "emit" => '. fld %ia32_emit_am /* load ST0 from stack */',
942 "outs" => [ "res", "M" ],
950 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
951 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "edi", "esi", "ecx", "none" ] },
952 "outs" => [ "DST", "SRC", "CNT", "M" ],
958 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
959 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
960 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "edi", "esi", "none" ] },
961 "outs" => [ "DST", "SRC", "M" ],
967 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
968 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
969 "comment" => "construct Conv Int -> Int",
970 "outs" => [ "res", "M" ],
974 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
975 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
976 "comment" => "construct Conv Int -> Int",
977 "outs" => [ "res", "M" ],
981 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
982 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
983 "comment" => "construct Conv Int -> Floating Point",
984 "outs" => [ "res", "M" ],
988 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
989 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
990 "comment" => "construct Conv Floating Point -> Int",
991 "outs" => [ "res", "M" ],
995 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
996 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
997 "comment" => "construct Conv Floating Point -> Floating Point",
998 "outs" => [ "res", "M" ],
1003 "comment" => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
1004 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "in_r4" ] }
1009 "comment" => "check if Psi condition tree evaluates to true and move result accordingly",
1010 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r3" ] }
1015 "comment" => "construct Conditional Move: SSE Compare + int CMov ",
1016 "reg_req" => { "in" => [ "xmm", "xmm", "gp", "gp" ], "out" => [ "in_r4" ] }
1021 "comment" => "construct Conditional Move: x87 Compare + int CMov",
1022 "reg_req" => { "in" => [ "vfp", "vfp", "gp", "gp" ], "out" => [ "in_r4" ] }
1027 "comment" => "construct Set: Set(sel) == sel ? 1 : 0",
1028 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1029 "outs" => [ "res", "M" ],
1034 "comment" => "check if Psi condition tree evaluates to true and set result accordingly",
1035 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax ebx ecx edx" ] },
1040 "comment" => "construct Set: SSE Compare + int Set",
1041 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1042 "outs" => [ "res", "M" ],
1047 "comment" => "construct Set: x87 Compare + int Set",
1048 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1049 "outs" => [ "res", "M" ],
1054 "comment" => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
1055 "reg_req" => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] }
1058 #----------------------------------------------------------#
1060 # (_) | | | | / _| | | | #
1061 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
1062 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
1063 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
1064 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
1066 # _ __ ___ __| | ___ ___ #
1067 # | '_ \ / _ \ / _` |/ _ \/ __| #
1068 # | | | | (_) | (_| | __/\__ \ #
1069 # |_| |_|\___/ \__,_|\___||___/ #
1070 #----------------------------------------------------------#
1074 "comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
1075 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1076 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1077 "outs" => [ "res", "M" ],
1082 "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1083 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1084 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1085 "outs" => [ "res", "M" ],
1090 "cmp_attr" => " return 1;\n",
1091 "comment" => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1097 "comment" => "virtual fp Sub: Sub(a, b) = a - b",
1098 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1099 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1100 "outs" => [ "res", "M" ],
1104 "cmp_attr" => " return 1;\n",
1105 "comment" => "lowered virtual fp Sub: Sub(a, b) = a - b",
1110 "comment" => "virtual fp Div: Div(a, b) = a / b",
1111 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1112 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1113 "outs" => [ "res", "M" ],
1117 "cmp_attr" => " return 1;\n",
1118 "comment" => "lowered virtual fp Div: Div(a, b) = a / b",
1124 "comment" => "virtual fp Abs: Abs(a) = |a|",
1125 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1130 "comment" => "virtual fp Chs: Chs(a) = -a",
1131 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1136 "comment" => "virtual fp Sin: Sin(a) = sin(a)",
1137 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1142 "comment" => "virtual fp Cos: Cos(a) = cos(a)",
1143 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1148 "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
1149 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1152 # virtual Load and Store
1155 "op_flags" => "L|F",
1156 "state" => "exc_pinned",
1157 "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
1158 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1159 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1160 "outs" => [ "res", "M" ],
1164 "op_flags" => "L|F",
1165 "state" => "exc_pinned",
1166 "comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
1167 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1168 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1175 "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1176 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1177 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1178 "outs" => [ "res", "M" ],
1182 "cmp_attr" => " return 1;\n",
1183 "comment" => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1184 "outs" => [ "res", "M" ],
1189 "comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1190 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1191 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1196 "cmp_attr" => " return 1;\n",
1197 "comment" => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1207 "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg",
1208 "reg_req" => { "out" => [ "vfp" ] },
1213 "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg",
1214 "reg_req" => { "out" => [ "vfp" ] },
1219 "comment" => "virtual fp Load pi: Ld pi -> reg",
1220 "reg_req" => { "out" => [ "vfp" ] },
1225 "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg",
1226 "reg_req" => { "out" => [ "vfp" ] },
1231 "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg",
1232 "reg_req" => { "out" => [ "vfp" ] },
1237 "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg",
1238 "reg_req" => { "out" => [ "vfp" ] },
1243 "comment" => "virtual fp Load ld e: Ld ld e -> reg",
1244 "reg_req" => { "out" => [ "vfp" ] },
1250 "init_attr" => " set_ia32_ls_mode(res, mode);",
1251 "comment" => "represents a virtual floating point constant",
1252 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1253 "reg_req" => { "in" => [ "none" ], "out" => [ "vfp" ] },
1259 "op_flags" => "L|X|Y",
1260 "comment" => "represents a virtual floating point compare",
1261 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1262 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] },
1263 "outs" => [ "false", "true", "temp_reg_eax" ],
1266 #------------------------------------------------------------------------#
1267 # ___ _____ __ _ _ _ #
1268 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1269 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1270 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1271 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1272 #------------------------------------------------------------------------#
1276 "rd_constructor" => "NONE",
1277 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1279 "emit" => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */',
1284 "rd_constructor" => "NONE",
1285 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1287 "emit" => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */',
1292 "rd_constructor" => "NONE",
1293 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1295 "emit" => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */',
1300 "rd_constructor" => "NONE",
1301 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1303 "emit" => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */',,
1308 "rd_constructor" => "NONE",
1309 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1311 "emit" => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */',
1316 "rd_constructor" => "NONE",
1317 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1319 "emit" => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */',
1324 "rd_constructor" => "NONE",
1326 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1328 "emit" => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */',
1333 "rd_constructor" => "NONE",
1335 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1337 "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */',
1342 "rd_constructor" => "NONE",
1343 "comment" => "x87 fp Div: Div(a, b) = a / b",
1345 "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */',
1350 "rd_constructor" => "NONE",
1351 "comment" => "x87 fp Div: Div(a, b) = a / b",
1353 "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */',
1358 "rd_constructor" => "NONE",
1359 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1361 "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */',
1366 "rd_constructor" => "NONE",
1367 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1369 "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */',
1374 "rd_constructor" => "NONE",
1375 "comment" => "x87 fp Abs: Abs(a) = |a|",
1377 "emit" => '. fabs /* x87 fabs(%S1) -> %D1 */',
1382 "rd_constructor" => "NONE",
1383 "comment" => "x87 fp Chs: Chs(a) = -a",
1385 "emit" => '. fchs /* x87 fchs(%S1) -> %D1 */',
1390 "rd_constructor" => "NONE",
1391 "comment" => "x87 fp Sin: Sin(a) = sin(a)",
1393 "emit" => '. fsin /* x87 sin(%S1) -> %D1 */',
1398 "rd_constructor" => "NONE",
1399 "comment" => "x87 fp Cos: Cos(a) = cos(a)",
1401 "emit" => '. fcos /* x87 cos(%S1) -> %D1 */',
1406 "rd_constructor" => "NONE",
1407 "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1409 "emit" => '. fsqrt $ /* x87 sqrt(%S1) -> %D1 */',
1412 # x87 Load and Store
1415 "rd_constructor" => "NONE",
1416 "op_flags" => "R|L|F",
1417 "state" => "exc_pinned",
1418 "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1420 "emit" => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */',
1424 "rd_constructor" => "NONE",
1425 "op_flags" => "R|L|F",
1426 "state" => "exc_pinned",
1427 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1429 "emit" => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */',
1433 "rd_constructor" => "NONE",
1434 "op_flags" => "R|L|F",
1435 "state" => "exc_pinned",
1436 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1438 "emit" => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */',
1445 "rd_constructor" => "NONE",
1446 "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1448 "emit" => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */',
1453 "rd_constructor" => "NONE",
1454 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1456 "emit" => '. fist %ia32_emit_am /* integer Store(%A3) -> (%A1) */',
1461 "rd_constructor" => "NONE",
1462 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1464 "emit" => '. fistp %ia32_emit_am /* integer Store(%A3) -> (%A1) and pop */',
1472 "rd_constructor" => "NONE",
1473 "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
1475 "emit" => '. fldz /* x87 0.0 -> %D1 */',
1481 "rd_constructor" => "NONE",
1482 "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
1484 "emit" => '. fld1 /* x87 1.0 -> %D1 */',
1490 "rd_constructor" => "NONE",
1491 "comment" => "x87 fp Load pi: Ld pi -> reg",
1493 "emit" => '. fldpi /* x87 pi -> %D1 */',
1499 "rd_constructor" => "NONE",
1500 "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
1502 "emit" => '. fldln2 /* x87 ln(2) -> %D1 */',
1508 "rd_constructor" => "NONE",
1509 "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
1511 "emit" => '. fldlg2 /* x87 log(2) -> %D1 */',
1517 "rd_constructor" => "NONE",
1518 "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
1520 "emit" => '. fldll2t /* x87 ld(10) -> %D1 */',
1526 "rd_constructor" => "NONE",
1527 "comment" => "x87 fp Load ld e: Ld ld e -> reg",
1529 "emit" => '. fldl2e /* x87 ld(e) -> %D1 */',
1533 "op_flags" => "R|c",
1535 "rd_constructor" => "NONE",
1536 "comment" => "represents a x87 constant",
1537 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1538 "reg_req" => { "out" => [ "st" ] },
1539 "emit" => '. fld %ia32_emit_adr /* Load fConst into register -> %D1 */',
1543 # Note that it is NEVER allowed to do CSE on these nodes
1546 "op_flags" => "R|K",
1547 "comment" => "x87 stack exchange",
1548 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1549 "cmp_attr" => " return 1;\n",
1550 "emit" => '. fxch %X1 /* x87 swap %X1, %X3 */',
1555 "comment" => "x87 stack push",
1556 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1557 "cmp_attr" => " return 1;\n",
1558 "emit" => '. fld %X1 /* x87 push %X1 */',
1562 "op_flags" => "R|K",
1563 "comment" => "x87 stack pop",
1564 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1565 "cmp_attr" => " return 1;\n",
1566 "emit" => '. fstp %X1 /* x87 pop %X1 */',
1572 "op_flags" => "L|X|Y",
1573 "comment" => "floating point compare",
1574 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1579 "op_flags" => "L|X|Y",
1580 "comment" => "floating point compare and pop",
1581 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1586 "op_flags" => "L|X|Y",
1587 "comment" => "floating point compare and pop twice",
1588 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1593 "op_flags" => "L|X|Y",
1594 "comment" => "floating point compare reverse",
1595 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1600 "op_flags" => "L|X|Y",
1601 "comment" => "floating point compare reverse and pop",
1602 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1607 "op_flags" => "L|X|Y",
1608 "comment" => "floating point compare reverse and pop twice",
1609 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",