3 # This is the specification for the ia32 assembler Firm-operations
10 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
13 # The node description is done as a perl hash initializer with the
14 # following structure:
19 # op_flags => "N|L|C|X|I|F|Y|H|c|K",
20 # irn_flags => "R|N|I|S"
21 # arity => "0|1|2|3 ... |variable|dynamic|any",
22 # state => "floats|pinned|mem_pinned|exc_pinned",
24 # { type => "type 1", name => "name 1" },
25 # { type => "type 2", name => "name 2" },
28 # comment => "any comment for constructor",
29 # reg_req => { in => [ "reg_class|register" ], out => [ "reg_class|register|in_rX" ] },
30 # cmp_attr => "c source code for comparing node attributes",
31 # emit => "emit code with templates",
32 # attr => "attitional attribute arguments for constructor"
33 # init_attr => "emit attribute initialization template"
34 # rd_constructor => "c source code which constructs an ir_node"
35 # latency => "latency of this operation (can be float)"
36 # attr_type => "name of the attribute struct",
39 # ... # (all nodes you need to describe)
41 # ); # close the %nodes initializer
43 # op_flags: flags for the operation, OPTIONAL (default is "N")
44 # the op_flags correspond to the firm irop_flags:
47 # C irop_flag_commutative
48 # X irop_flag_cfopcode
49 # I irop_flag_ip_cfopcode
52 # H irop_flag_highlevel
53 # c irop_flag_constlike
56 # irn_flags: special node flags, OPTIONAL (default is 0)
57 # following irn_flags are supported:
60 # I ignore for register allocation
61 # S modifies stack pointer
63 # state: state of the operation, OPTIONAL (default is "floats")
65 # arity: arity of the operation, MUST NOT BE OMITTED
67 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
68 # are always the first 3 arguments and are always autmatically
70 # If this key is missing the following arguments will be created:
71 # for i = 1 .. arity: ir_node *op_i
74 # outs: if a node defines more than one output, the names of the projections
75 # nodes having outs having automatically the mode mode_T
76 # One can also annotate some flags for each out, additional to irn_flags.
77 # They are separated from name with a colon ':', and concatenated by pipe '|'
78 # Only I and S are available at the moment (same meaning as in irn_flags).
79 # example: [ "frame:I", "stack:I|S", "M" ]
81 # comment: OPTIONAL comment for the node constructor
83 # rd_constructor: for every operation there will be a
84 # new_rd_<arch>_<op-name> function with the arguments from above
85 # which creates the ir_node corresponding to the defined operation
86 # you can either put the complete source code of this function here
88 # This key is OPTIONAL. If omitted, the following constructor will
90 # if (!op_<arch>_<op-name>) assert(0);
94 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
97 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
99 # latency: the latency of the operation, default is 1
103 # 0 - no special type
104 # 1 - caller save (register must be saved by the caller of a function)
105 # 2 - callee save (register must be saved by the called function)
106 # 4 - ignore (do not assign this register)
107 # 8 - emitter can choose an arbitrary register of this class
108 # 16 - the register is a virtual one
109 # 32 - register represents a state
110 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
113 { name => "eax", type => 1 },
114 { name => "edx", type => 1 },
115 { name => "ebx", type => 2 },
116 { name => "ecx", type => 1 },
117 { name => "esi", type => 2 },
118 { name => "edi", type => 2 },
119 { name => "ebp", type => 2 },
120 { name => "esp", type => 4 },
121 { name => "gp_NOREG", type => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
122 { name => "gp_UKNWN", type => 4 | 8 | 16 }, # we need a dummy register for Unknown nodes
123 { mode => "mode_Iu" }
126 { name => "mm0", type => 4 },
127 { name => "mm1", type => 4 },
128 { name => "mm2", type => 4 },
129 { name => "mm3", type => 4 },
130 { name => "mm4", type => 4 },
131 { name => "mm5", type => 4 },
132 { name => "mm6", type => 4 },
133 { name => "mm7", type => 4 },
137 { name => "xmm0", type => 1 },
138 { name => "xmm1", type => 1 },
139 { name => "xmm2", type => 1 },
140 { name => "xmm3", type => 1 },
141 { name => "xmm4", type => 1 },
142 { name => "xmm5", type => 1 },
143 { name => "xmm6", type => 1 },
144 { name => "xmm7", type => 1 },
145 { name => "xmm_NOREG", type => 4 | 16 }, # we need a dummy register for NoReg nodes
146 { name => "xmm_UKNWN", type => 4 | 8 | 16}, # we need a dummy register for Unknown nodes
150 { name => "vf0", type => 1 | 16 },
151 { name => "vf1", type => 1 | 16 },
152 { name => "vf2", type => 1 | 16 },
153 { name => "vf3", type => 1 | 16 },
154 { name => "vf4", type => 1 | 16 },
155 { name => "vf5", type => 1 | 16 },
156 { name => "vf6", type => 1 | 16 },
157 { name => "vf7", type => 1 | 16 },
158 { name => "vfp_NOREG", type => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
159 { name => "vfp_UKNWN", type => 4 | 8 | 16 }, # we need a dummy register for Unknown nodes
163 { name => "st0", realname => "st", type => 4 },
164 { name => "st1", realname => "st(1)", type => 4 },
165 { name => "st2", realname => "st(2)", type => 4 },
166 { name => "st3", realname => "st(3)", type => 4 },
167 { name => "st4", realname => "st(4)", type => 4 },
168 { name => "st5", realname => "st(5)", type => 4 },
169 { name => "st6", realname => "st(6)", type => 4 },
170 { name => "st7", realname => "st(7)", type => 4 },
173 fp_cw => [ # the floating point control word
174 { name => "fpcw", type => 4 | 32},
175 { mode => "mode_fpcw" }
178 { name => "eflags", type => 4 },
179 { mode => "mode_Iu" }
182 { name => "fpsw", type => 4 },
183 { mode => "mode_Hu" }
188 CF => { reg => "eflags", bit => 0 },
189 PF => { reg => "eflags", bit => 2 },
190 AF => { reg => "eflags", bit => 4 },
191 ZF => { reg => "eflags", bit => 6 },
192 SF => { reg => "eflags", bit => 7 },
193 TF => { reg => "eflags", bit => 8 },
194 IF => { reg => "eflags", bit => 9 },
195 DF => { reg => "eflags", bit => 10 },
196 OF => { reg => "eflags", bit => 11 },
197 IOPL0 => { reg => "eflags", bit => 12 },
198 IOPL1 => { reg => "eflags", bit => 13 },
199 NT => { reg => "eflags", bit => 14 },
200 RF => { reg => "eflags", bit => 16 },
201 VM => { reg => "eflags", bit => 17 },
202 AC => { reg => "eflags", bit => 18 },
203 VIF => { reg => "eflags", bit => 19 },
204 VIP => { reg => "eflags", bit => 20 },
205 ID => { reg => "eflags", bit => 21 },
207 FP_IE => { reg => "fpsw", bit => 0 },
208 FP_DE => { reg => "fpsw", bit => 1 },
209 FP_ZE => { reg => "fpsw", bit => 2 },
210 FP_OE => { reg => "fpsw", bit => 3 },
211 FP_UE => { reg => "fpsw", bit => 4 },
212 FP_PE => { reg => "fpsw", bit => 5 },
213 FP_SF => { reg => "fpsw", bit => 6 },
214 FP_ES => { reg => "fpsw", bit => 7 },
215 FP_C0 => { reg => "fpsw", bit => 8 },
216 FP_C1 => { reg => "fpsw", bit => 9 },
217 FP_C2 => { reg => "fpsw", bit => 10 },
218 FP_TOP0 => { reg => "fpsw", bit => 11 },
219 FP_TOP1 => { reg => "fpsw", bit => 12 },
220 FP_TOP2 => { reg => "fpsw", bit => 13 },
221 FP_C3 => { reg => "fpsw", bit => 14 },
222 FP_B => { reg => "fpsw", bit => 15 },
224 FP_IM => { reg => "fpcw", bit => 0 },
225 FP_DM => { reg => "fpcw", bit => 1 },
226 FP_ZM => { reg => "fpcw", bit => 2 },
227 FP_OM => { reg => "fpcw", bit => 3 },
228 FP_UM => { reg => "fpcw", bit => 4 },
229 FP_PM => { reg => "fpcw", bit => 5 },
230 FP_PC0 => { reg => "fpcw", bit => 8 },
231 FP_PC1 => { reg => "fpcw", bit => 9 },
232 FP_RC0 => { reg => "fpcw", bit => 10 },
233 FP_RC1 => { reg => "fpcw", bit => 11 },
234 FP_X => { reg => "fpcw", bit => 12 }
238 GP => [ 1, "GP_EAX", "GP_EBX", "GP_ECX", "GP_EDX", "GP_ESI", "GP_EDI", "GP_EBP" ],
239 SSE => [ 1, "SSE_XMM0", "SSE_XMM1", "SSE_XMM2", "SSE_XMM3", "SSE_XMM4", "SSE_XMM5", "SSE_XMM6", "SSE_XMM7" ],
240 VFP => [ 1, "VFP_VF0", "VFP_VF1", "VFP_VF2", "VFP_VF3", "VFP_VF4", "VFP_VF5", "VFP_VF6", "VFP_VF7" ],
241 BRANCH => [ 1, "BRANCH1", "BRANCH2" ],
246 bundels_per_cycle => 1
250 S0 => "${arch}_emit_source_register(env, node, 0);",
251 S1 => "${arch}_emit_source_register(env, node, 1);",
252 S2 => "${arch}_emit_source_register(env, node, 2);",
253 S3 => "${arch}_emit_source_register(env, node, 3);",
254 S4 => "${arch}_emit_source_register(env, node, 4);",
255 S5 => "${arch}_emit_source_register(env, node, 5);",
256 D0 => "${arch}_emit_dest_register(env, node, 0);",
257 D1 => "${arch}_emit_dest_register(env, node, 1);",
258 D2 => "${arch}_emit_dest_register(env, node, 2);",
259 D3 => "${arch}_emit_dest_register(env, node, 3);",
260 D4 => "${arch}_emit_dest_register(env, node, 4);",
261 D5 => "${arch}_emit_dest_register(env, node, 5);",
262 X0 => "${arch}_emit_x87_name(env, node, 0);",
263 X1 => "${arch}_emit_x87_name(env, node, 1);",
264 X2 => "${arch}_emit_x87_name(env, node, 2);",
265 C => "${arch}_emit_immediate(env, node);",
266 SE => "${arch}_emit_extend_suffix(env, get_ia32_ls_mode(node));",
267 ME => "if(get_mode_size_bits(get_ia32_ls_mode(node)) != 32)\n
268 ia32_emit_mode_suffix(env, node);",
269 M => "${arch}_emit_mode_suffix(env, node);",
270 XM => "${arch}_emit_x87_mode_suffix(env, node);",
271 XXM => "${arch}_emit_xmm_mode_suffix(env, node);",
272 XSD => "${arch}_emit_xmm_mode_suffix_s(env, node);",
273 AM => "${arch}_emit_am(env, node);",
274 unop0 => "${arch}_emit_unop(env, node, 0);",
275 unop1 => "${arch}_emit_unop(env, node, 1);",
276 unop2 => "${arch}_emit_unop(env, node, 2);",
277 unop3 => "${arch}_emit_unop(env, node, 3);",
278 unop4 => "${arch}_emit_unop(env, node, 4);",
279 DAM0 => "${arch}_emit_am_or_dest_register(env, node, 0);",
280 DAM1 => "${arch}_emit_am_or_dest_register(env, node, 0);",
281 binop => "${arch}_emit_binop(env, node);",
282 x87_binop => "${arch}_emit_x87_binop(env, node);",
285 #--------------------------------------------------#
288 # _ __ _____ __ _ _ __ ___ _ __ ___ #
289 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
290 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
291 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
294 #--------------------------------------------------#
296 $default_attr_type = "ia32_attr_t";
297 $default_copy_attr = "ia32_copy_attr";
300 ia32_attr_t => "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);",
302 "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);\n".
303 "\tinit_ia32_x87_attributes(res);",
305 "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);\n".
306 "\tinit_ia32_x87_attributes(res);".
307 "\tinit_ia32_asm_attributes(res);",
308 ia32_immediate_attr_t =>
309 "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);\n".
310 "\tinit_ia32_immediate_attributes(res, symconst, symconst_sign, offset);"
314 ia32_attr_t => "ia32_compare_nodes_attr",
315 ia32_x87_attr_t => "ia32_compare_x87_attr",
316 ia32_asm_attr_t => "ia32_compare_asm_attr",
317 ia32_immediate_attr_t => "ia32_compare_immediate_attr",
323 $mode_xmm = "mode_E";
324 $mode_gp = "mode_Iu";
325 $mode_fpcw = "mode_fpcw";
326 $status_flags = [ "CF", "PF", "AF", "ZF", "SF", "OF" ];
327 $fpcw_flags = [ "FP_IM", "FP_DM", "FP_ZM", "FP_OM", "FP_UM", "FP_PM",
328 "FP_PC0", "FP_PC1", "FP_RC0", "FP_RC1", "FP_X" ];
336 reg_req => { out => [ "gp_NOREG" ] },
337 attr => "ir_entity *symconst, int symconst_sign, long offset",
338 attr_type => "ia32_immediate_attr_t",
345 out_arity => "variable",
346 attr_type => "ia32_asm_attr_t",
349 #-----------------------------------------------------------------#
352 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
353 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
354 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
355 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
358 #-----------------------------------------------------------------#
360 # commutative operations
363 # All nodes supporting Addressmode have 5 INs:
364 # 1 - base r1 == NoReg in case of no AM or no base
365 # 2 - index r2 == NoReg in case of no AM or no index
366 # 3 - op1 r3 == always present
367 # 4 - op2 r4 == NoReg in case of immediate operation
368 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
372 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
373 ins => [ "base", "index", "left", "right", "mem" ],
374 emit => '. add%M %binop',
377 modified_flags => $status_flags
381 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
382 emit => '. adc%M %binop',
385 modified_flags => $status_flags
391 reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
398 outs => [ "low_res", "high_res" ],
400 modified_flags => $status_flags
406 cmp_attr => "return 1;",
412 cmp_attr => "return 1;",
417 # we should not rematrialize this node. It produces 2 results and has
418 # very strict constrains
419 reg_req => { in => [ "gp", "gp", "eax", "gp", "none" ], out => [ "eax", "edx", "none" ] },
420 emit => '. mul%M %unop3',
421 outs => [ "EAX", "EDX", "M" ],
422 ins => [ "base", "index", "val_high", "val_low", "mem" ],
425 modified_flags => $status_flags
429 # we should not rematrialize this node. It produces 2 results and has
430 # very strict constrains
432 cmp_attr => "return 1;",
433 outs => [ "EAX", "EDX", "M" ],
439 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
440 emit => '. imul%M %binop',
444 modified_flags => $status_flags
449 reg_req => { in => [ "gp", "gp", "eax", "gp", "none" ], out => [ "eax", "edx", "none" ] },
450 emit => '. imul%M %unop3',
451 outs => [ "EAX", "EDX", "M" ],
452 ins => [ "base", "index", "val_high", "val_low", "mem" ],
455 modified_flags => $status_flags
460 cmp_attr => "return 1;",
466 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
467 emit => '. and%M %binop',
470 modified_flags => $status_flags
475 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
476 emit => '. or%M %binop',
479 modified_flags => $status_flags
484 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
485 emit => '. xor%M %binop',
488 modified_flags => $status_flags
493 cmp_attr => "return 1;",
495 modified_flags => $status_flags
498 # not commutative operations
502 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
503 emit => '. sub%M %binop',
506 modified_flags => $status_flags
510 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3 !in_r4" ] },
511 emit => '. sbb%M %binop',
514 modified_flags => $status_flags
520 reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
527 outs => [ "low_res", "high_res" ],
529 modified_flags => $status_flags
534 cmp_attr => "return 1;",
539 cmp_attr => "return 1;",
545 state => "exc_pinned",
546 reg_req => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ], out => [ "eax", "edx", "none" ] },
547 attr => "ia32_op_flavour_t dm_flav",
548 init_attr => "attr->data.op_flav = dm_flav;",
549 emit => ". idiv%M %unop4",
550 outs => [ "div_res", "mod_res", "M" ],
553 modified_flags => $status_flags
558 state => "exc_pinned",
559 reg_req => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ], out => [ "eax", "edx", "none" ] },
560 attr => "ia32_op_flavour_t dm_flav",
561 init_attr => "attr->data.op_flav = dm_flav;",
562 emit => ". div%M %unop4",
563 outs => [ "div_res", "mod_res", "M" ],
566 modified_flags => $status_flags
571 # "in_r3" would be enough as out requirement, but the register allocator
572 # does strange things then and doesn't respect the constraint for in4
573 # if the same value is attached to in3 and in4 (if you have "i << i" in C)
574 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
575 ins => [ "base", "index", "left", "right", "mem" ],
576 emit => '. shl%M %binop',
579 modified_flags => $status_flags
583 cmp_attr => "return 1;",
589 # Out requirements is: different from all in
590 # This is because, out must be different from LowPart and ShiftCount.
591 # We could say "!ecx !in_r4" but it can occur, that all values live through
592 # this Shift and the only value dying is the ShiftCount. Then there would be
593 # a register missing, as result must not be ecx and all other registers are
594 # occupied. What we should write is "!in_r4 !in_r5", but this is not
595 # supported (and probably never will). So we create artificial interferences
596 # of the result with all inputs, so the spiller can always assure a free
598 reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
601 if (get_ia32_immop_type(node) == ia32_ImmNone) {
602 if (get_ia32_op_type(node) == ia32_AddrModeD) {
603 . shld%M %%cl, %S3, %AM
605 . shld%M %%cl, %S3, %S2
608 if (get_ia32_op_type(node) == ia32_AddrModeD) {
609 . shld%M %C, %S3, %AM
611 . shld%M %C, %S3, %S2
618 modified_flags => $status_flags
622 cmp_attr => "return 1;",
628 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
629 emit => '. shr%M %binop',
632 modified_flags => $status_flags
636 cmp_attr => "return 1;",
642 # Out requirements is: different from all in
643 # This is because, out must be different from LowPart and ShiftCount.
644 # We could say "!ecx !in_r4" but it can occur, that all values live through
645 # this Shift and the only value dying is the ShiftCount. Then there would be a
646 # register missing, as result must not be ecx and all other registers are
647 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
648 # (and probably never will). So we create artificial interferences of the result
649 # with all inputs, so the spiller can always assure a free register.
650 reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
652 if (get_ia32_immop_type(node) == ia32_ImmNone) {
653 if (get_ia32_op_type(node) == ia32_AddrModeD) {
654 . shrd%M %%cl, %S3, %AM
656 . shrd%M %%cl, %S3, %S2
659 if (get_ia32_op_type(node) == ia32_AddrModeD) {
660 . shrd%M %C, %S3, %AM
662 . shrd%M %C, %S3, %S2
669 modified_flags => $status_flags
673 cmp_attr => "return 1;",
679 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
680 emit => '. sar%M %binop',
683 modified_flags => $status_flags
687 cmp_attr => "return 1;",
693 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
694 emit => '. ror%M %binop',
697 modified_flags => $status_flags
702 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
703 emit => '. rol%M %binop',
706 modified_flags => $status_flags
713 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
714 emit => '. neg%M %unop2',
715 ins => [ "base", "index", "val", "mem" ],
718 modified_flags => $status_flags
723 reg_req => { in => [ "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
730 outs => [ "low_res", "high_res" ],
732 modified_flags => $status_flags
737 cmp_attr => "return 1;",
743 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
744 emit => '. inc%M %unop2',
747 modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
752 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
753 emit => '. dec%M %unop2',
756 modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
761 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
762 ins => [ "base", "index", "val", "mem" ],
763 emit => '. not%M %unop2',
774 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ],
775 out => [ "none", "none"] },
776 ins => [ "base", "index", "left", "right", "mem" ],
777 outs => [ "false", "true" ],
779 init_attr => "attr->pn_code = pnc;",
781 units => [ "BRANCH" ],
787 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ],
788 out => [ "none", "none" ] },
789 ins => [ "base", "index", "left", "right", "mem" ],
790 outs => [ "false", "true" ],
792 init_attr => "attr->pn_code = pnc;",
794 units => [ "BRANCH" ],
800 reg_req => { in => [ "gp" ], out => [ "none" ] },
802 units => [ "BRANCH" ],
809 reg_req => { out => [ "gp" ] },
818 reg_req => { out => [ "gp_UKNWN" ] },
828 reg_req => { out => [ "vfp_UKNWN" ] },
832 attr_type => "ia32_x87_attr_t",
839 reg_req => { out => [ "xmm_UKNWN" ] },
849 reg_req => { out => [ "gp_NOREG" ] },
859 reg_req => { out => [ "vfp_NOREG" ] },
863 attr_type => "ia32_x87_attr_t",
870 reg_req => { out => [ "xmm_NOREG" ] },
880 reg_req => { out => [ "fp_cw" ] },
884 modified_flags => $fpcw_flags
890 reg_req => { in => [ "gp", "gp", "none" ], out => [ "fp_cw" ] },
892 emit => ". fldcw %AM",
895 modified_flags => $fpcw_flags
901 reg_req => { in => [ "gp", "gp", "fp_cw", "none" ], out => [ "none" ] },
903 emit => ". fnstcw %AM",
909 # we should not rematrialize this node. It produces 2 results and has
910 # very strict constrains
911 reg_req => { in => [ "eax" ], out => [ "edx" ] },
920 # Note that we add additional latency values depending on address mode, so a
921 # lateny of 0 for load is correct
925 state => "exc_pinned",
926 reg_req => { in => [ "gp", "gp", "none" ], out => [ "gp", "none" ] },
927 ins => [ "base", "index", "mem" ],
928 outs => [ "res", "M" ],
930 emit => ". mov%SE%ME%.l %AM, %D0",
936 cmp_attr => "return 1;",
937 outs => [ "res", "M" ],
943 cmp_attr => "return 1;",
944 state => "exc_pinned",
951 state => "exc_pinned",
952 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "none" ] },
953 ins => [ "base", "index", "val", "mem" ],
954 emit => '. mov%M %binop',
962 state => "exc_pinned",
963 reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => ["none" ] },
964 emit => '. mov%M %binop',
972 reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
973 emit => '. leal %AM, %D0',
977 modified_flags => [],
981 reg_req => { in => [ "gp", "gp", "gp", "esp", "none" ], out => [ "esp", "none" ] },
982 emit => '. push%M %unop2',
983 ins => [ "base", "index", "val", "stack", "mem" ],
984 outs => [ "stack:I|S", "M" ],
987 modified_flags => [],
991 reg_req => { in => [ "gp", "gp", "esp", "none" ], out => [ "esp", "gp", "none" ] },
992 emit => '. pop%M %DAM1',
993 outs => [ "stack:I|S", "res", "M" ],
994 ins => [ "base", "index", "stack", "mem" ],
995 latency => 3, # Pop is more expensive than Push on Athlon
997 modified_flags => [],
1001 reg_req => { in => [ "esp" ], out => [ "ebp", "esp", "none" ] },
1003 outs => [ "frame:I", "stack:I|S", "M" ],
1009 reg_req => { in => [ "esp", "ebp" ], out => [ "ebp", "esp" ] },
1011 outs => [ "frame:I", "stack:I|S" ],
1018 reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "none" ] },
1019 emit => '. addl %binop',
1020 outs => [ "stack:S", "M" ],
1022 modified_flags => $status_flags
1027 reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "gp", "none" ] },
1028 emit => ". subl %binop\n".
1029 ". movl %%esp, %D1",
1030 outs => [ "stack:I|S", "addr", "M" ],
1032 modified_flags => $status_flags
1037 reg_req => { out => [ "gp" ] },
1041 # the int instruction
1043 reg_req => { in => [ "none" ], out => [ "none" ] },
1045 attr => "tarval *tv",
1046 init_attr => "\tset_ia32_Immop_tarval(res, tv);",
1049 cmp_attr => "return 1;",
1053 #-----------------------------------------------------------------------------#
1054 # _____ _____ ______ __ _ _ _ #
1055 # / ____/ ____| ____| / _| | | | | | #
1056 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1057 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1058 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1059 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1060 #-----------------------------------------------------------------------------#
1062 # commutative operations
1066 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1067 emit => '. add%XXM %binop',
1075 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1076 emit => '. mul%XXM %binop',
1084 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1085 emit => '. max%XXM %binop',
1093 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1094 emit => '. min%XXM %binop',
1102 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1103 emit => '. andp%XSD %binop',
1111 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1112 emit => '. orp%XSD %binop',
1119 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1120 emit => '. xorp%XSD %binop',
1126 # not commutative operations
1130 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] },
1131 emit => '. andnp%XSD %binop',
1139 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1140 emit => '. sub%XXM %binop',
1148 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4", "none" ] },
1149 outs => [ "res", "M" ],
1150 emit => '. div%XXM %binop',
1159 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] },
1167 op_flags => "L|X|Y",
1168 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "none", "none" ] },
1169 ins => [ "base", "index", "left", "right", "mem" ],
1170 outs => [ "false", "true" ],
1172 init_attr => "attr->pn_code = pnc;",
1180 reg_req => { out => [ "xmm" ] },
1181 emit => '. mov%XXM %C, %D0',
1191 state => "exc_pinned",
1192 reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none" ] },
1193 emit => '. mov%XXM %AM, %D0',
1194 outs => [ "res", "M" ],
1201 state => "exc_pinned",
1202 reg_req => { in => [ "gp", "gp", "xmm", "none" ] },
1203 emit => '. mov%XXM %binop',
1211 state => "exc_pinned",
1212 reg_req => { in => [ "gp", "gp", "xmm", "none" ] },
1213 ins => [ "base", "index", "val", "mem" ],
1214 emit => '. mov%XXM %S2, %AM',
1222 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm" ] },
1223 emit => '. cvtsi2ss %D0, %AM',
1231 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm" ] },
1232 emit => '. cvtsi2sd %unop2',
1241 cmp_attr => "return 1;",
1247 cmp_attr => "return 1;",
1255 reg_req => { in => [ "gp", "gp", "none" ] },
1256 emit => '. fstp%XM %AM',
1266 reg_req => { in => [ "gp", "gp", "none" ], out => [ "vf0", "none" ] },
1267 ins => [ "base", "index", "mem" ],
1268 emit => '. fld%XM %AM',
1269 outs => [ "res", "M" ],
1279 reg_req => { in => [ "edi", "esi", "ecx", "none" ], out => [ "edi", "esi", "ecx", "none" ] },
1280 outs => [ "DST", "SRC", "CNT", "M" ],
1282 modified_flags => [ "DF" ]
1288 reg_req => { in => [ "edi", "esi", "none" ], out => [ "edi", "esi", "none" ] },
1289 outs => [ "DST", "SRC", "M" ],
1291 modified_flags => [ "DF" ]
1297 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3", "none" ] },
1299 ins => [ "base", "index", "val", "mem" ],
1301 modified_flags => $status_flags
1305 reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => [ "in_r3", "none" ] },
1306 ins => [ "base", "index", "val", "mem" ],
1309 modified_flags => $status_flags
1313 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm", "none" ] },
1320 reg_req => { in => [ "gp", "gp", "xmm", "none" ], out => [ "gp", "none" ] },
1327 reg_req => { in => [ "gp", "gp", "xmm", "none" ], out => [ "xmm", "none" ] },
1335 reg_req => { in => [ "gp", "gp", "gp", "gp", "none", "gp", "gp" ], out => [ "in_r7" ] },
1336 ins => [ "base", "index", "cmp_left", "cmp_right", "mem", "val_true", "val_false" ],
1337 attr => "pn_Cmp pn_code",
1338 init_attr => "attr->pn_code = pn_code;",
1346 reg_req => { in => [ "gp", "gp", "gp", "gp", "none", "gp", "gp" ], out => [ "in_r7" ] },
1347 ins => [ "base", "index", "cmp_left", "cmp_right", "mem", "val_true", "val_false" ],
1348 attr => "pn_Cmp pn_code",
1349 init_attr => "attr->pn_code = pn_code;",
1357 reg_req => { in => [ "xmm", "xmm", "gp", "gp" ], out => [ "in_r4" ] },
1365 reg_req => { in => [ "vfp", "vfp", "gp", "gp" ], out => [ "in_r4" ] },
1369 attr_type => "ia32_x87_attr_t",
1374 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "eax ebx ecx edx" ] },
1375 ins => [ "base", "index", "cmp_left", "cmp_right", "mem" ],
1376 attr => "pn_Cmp pn_code",
1377 init_attr => "attr->pn_code = pn_code;",
1385 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "eax ebx ecx edx" ] },
1386 ins => [ "base", "index", "cmp_left", "cmp_right", "mem" ],
1387 attr => "pn_Cmp pn_code",
1388 init_attr => "attr->pn_code = pn_code;",
1396 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "eax ebx ecx edx" ] },
1404 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "eax ebx ecx edx" ] },
1408 attr_type => "ia32_x87_attr_t",
1413 reg_req => { in => [ "vfp", "vfp", "vfp", "vfp" ], out => [ "vfp" ] },
1417 attr_type => "ia32_x87_attr_t",
1420 #----------------------------------------------------------#
1422 # (_) | | | | / _| | | | #
1423 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
1424 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
1425 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
1426 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
1428 # _ __ ___ __| | ___ ___ #
1429 # | '_ \ / _ \ / _` |/ _ \/ __| #
1430 # | | | | (_) | (_| | __/\__ \ #
1431 # |_| |_|\___/ \__,_|\___||___/ #
1432 #----------------------------------------------------------#
1436 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp" ] },
1437 ins => [ "base", "index", "left", "right", "mem", "fpcw" ],
1441 attr_type => "ia32_x87_attr_t",
1446 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp" ] },
1447 ins => [ "base", "index", "left", "right", "mem", "fpcw" ],
1451 attr_type => "ia32_x87_attr_t",
1456 cmp_attr => "return 1;",
1462 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp" ] },
1463 ins => [ "base", "index", "left", "right", "mem", "fpcw" ],
1467 attr_type => "ia32_x87_attr_t",
1471 cmp_attr => "return 1;",
1476 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp", "none" ] },
1477 ins => [ "base", "index", "left", "right", "mem", "fpcw" ],
1478 outs => [ "res", "M" ],
1481 attr_type => "ia32_x87_attr_t",
1485 cmp_attr => "return 1;",
1486 outs => [ "res", "M" ],
1491 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp" ] },
1492 ins => [ "base", "index", "left", "right", "mem", "fpcw" ],
1496 attr_type => "ia32_x87_attr_t",
1500 cmp_attr => "return 1;",
1506 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1511 attr_type => "ia32_x87_attr_t",
1516 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1521 attr_type => "ia32_x87_attr_t",
1524 # virtual Load and Store
1528 state => "exc_pinned",
1529 reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] },
1530 ins => [ "base", "index", "mem" ],
1531 outs => [ "res", "M" ],
1532 attr => "ir_mode *store_mode",
1533 init_attr => "attr->attr.ls_mode = store_mode;",
1536 attr_type => "ia32_x87_attr_t",
1541 state => "exc_pinned",
1542 reg_req => { in => [ "gp", "gp", "vfp", "none" ] },
1543 ins => [ "base", "index", "val", "mem" ],
1544 attr => "ir_mode *store_mode",
1545 init_attr => "attr->attr.ls_mode = store_mode;",
1549 attr_type => "ia32_x87_attr_t",
1555 state => "exc_pinned",
1556 reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] },
1557 outs => [ "res", "M" ],
1558 ins => [ "base", "index", "mem" ],
1561 attr_type => "ia32_x87_attr_t",
1565 cmp_attr => "return 1;",
1566 outs => [ "res", "M" ],
1571 state => "exc_pinned",
1572 reg_req => { in => [ "gp", "gp", "vfp", "fpcw", "none" ] },
1573 ins => [ "base", "index", "val", "fpcw", "mem" ],
1577 attr_type => "ia32_x87_attr_t",
1581 cmp_attr => "return 1;",
1582 state => "exc_pinned",
1592 reg_req => { out => [ "vfp" ] },
1596 attr_type => "ia32_x87_attr_t",
1601 reg_req => { out => [ "vfp" ] },
1605 attr_type => "ia32_x87_attr_t",
1610 reg_req => { out => [ "vfp" ] },
1614 attr_type => "ia32_x87_attr_t",
1619 reg_req => { out => [ "vfp" ] },
1623 attr_type => "ia32_x87_attr_t",
1628 reg_req => { out => [ "vfp" ] },
1632 attr_type => "ia32_x87_attr_t",
1637 reg_req => { out => [ "vfp" ] },
1641 attr_type => "ia32_x87_attr_t",
1646 reg_req => { out => [ "vfp" ] },
1650 attr_type => "ia32_x87_attr_t",
1656 reg_req => { out => [ "vfp" ] },
1660 attr_type => "ia32_x87_attr_t",
1667 op_flags => "L|X|Y",
1668 reg_req => { in => [ "vfp", "vfp" ], out => [ "none", "none", "eax" ] },
1669 ins => [ "left", "right" ],
1670 outs => [ "false", "true", "temp_reg_eax" ],
1672 init_attr => "attr->attr.pn_code = pnc;",
1675 attr_type => "ia32_x87_attr_t",
1678 #------------------------------------------------------------------------#
1679 # ___ _____ __ _ _ _ #
1680 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1681 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1682 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1683 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1684 #------------------------------------------------------------------------#
1686 # Note: gas is strangely buggy: fdivrp and fdivp as well as fsubrp and fsubp
1687 # are swapped, we work this around in the emitter...
1691 rd_constructor => "NONE",
1693 emit => '. fadd%XM %x87_binop',
1694 attr_type => "ia32_x87_attr_t",
1699 rd_constructor => "NONE",
1701 emit => '. faddp%XM %x87_binop',
1702 attr_type => "ia32_x87_attr_t",
1707 rd_constructor => "NONE",
1709 emit => '. fmul%XM %x87_binop',
1710 attr_type => "ia32_x87_attr_t",
1715 rd_constructor => "NONE",
1717 emit => '. fmulp%XM %x87_binop',,
1718 attr_type => "ia32_x87_attr_t",
1723 rd_constructor => "NONE",
1725 emit => '. fsub%XM %x87_binop',
1726 attr_type => "ia32_x87_attr_t",
1731 rd_constructor => "NONE",
1733 # see note about gas bugs
1734 emit => '. fsubrp%XM %x87_binop',
1735 attr_type => "ia32_x87_attr_t",
1740 rd_constructor => "NONE",
1743 emit => '. fsubr%XM %x87_binop',
1744 attr_type => "ia32_x87_attr_t",
1749 rd_constructor => "NONE",
1752 # see note about gas bugs
1753 emit => '. fsubp%XM %x87_binop',
1754 attr_type => "ia32_x87_attr_t",
1759 rd_constructor => "NONE",
1762 attr_type => "ia32_x87_attr_t",
1765 # this node is just here, to keep the simulator running
1766 # we can omit this when a fprem simulation function exists
1769 rd_constructor => "NONE",
1772 attr_type => "ia32_x87_attr_t",
1777 rd_constructor => "NONE",
1779 emit => '. fdiv%XM %x87_binop',
1780 attr_type => "ia32_x87_attr_t",
1785 rd_constructor => "NONE",
1787 # see note about gas bugs
1788 emit => '. fdivrp%XM %x87_binop',
1789 attr_type => "ia32_x87_attr_t",
1794 rd_constructor => "NONE",
1796 emit => '. fdivr%XM %x87_binop',
1797 attr_type => "ia32_x87_attr_t",
1802 rd_constructor => "NONE",
1804 # see note about gas bugs
1805 emit => '. fdivp%XM %x87_binop',
1806 attr_type => "ia32_x87_attr_t",
1811 rd_constructor => "NONE",
1814 attr_type => "ia32_x87_attr_t",
1819 rd_constructor => "NONE",
1822 attr_type => "ia32_x87_attr_t",
1825 # x87 Load and Store
1828 rd_constructor => "NONE",
1829 op_flags => "R|L|F",
1830 state => "exc_pinned",
1832 emit => '. fld%XM %AM',
1833 attr_type => "ia32_x87_attr_t",
1837 rd_constructor => "NONE",
1838 op_flags => "R|L|F",
1839 state => "exc_pinned",
1841 emit => '. fst%XM %AM',
1843 attr_type => "ia32_x87_attr_t",
1847 rd_constructor => "NONE",
1848 op_flags => "R|L|F",
1849 state => "exc_pinned",
1851 emit => '. fstp%XM %AM',
1853 attr_type => "ia32_x87_attr_t",
1860 rd_constructor => "NONE",
1862 emit => '. fild%XM %AM',
1863 attr_type => "ia32_x87_attr_t",
1868 state => "exc_pinned",
1869 rd_constructor => "NONE",
1871 emit => '. fist%XM %AM',
1873 attr_type => "ia32_x87_attr_t",
1878 state => "exc_pinned",
1879 rd_constructor => "NONE",
1881 emit => '. fistp%XM %AM',
1883 attr_type => "ia32_x87_attr_t",
1889 op_flags => "R|c|K",
1893 attr_type => "ia32_x87_attr_t",
1897 op_flags => "R|c|K",
1901 attr_type => "ia32_x87_attr_t",
1905 op_flags => "R|c|K",
1909 attr_type => "ia32_x87_attr_t",
1913 op_flags => "R|c|K",
1917 attr_type => "ia32_x87_attr_t",
1921 op_flags => "R|c|K",
1925 attr_type => "ia32_x87_attr_t",
1929 op_flags => "R|c|K",
1932 emit => '. fldll2t',
1933 attr_type => "ia32_x87_attr_t",
1937 op_flags => "R|c|K",
1941 attr_type => "ia32_x87_attr_t",
1945 # Note that it is NEVER allowed to do CSE on these nodes
1946 # Moreover, note the virtual register requierements!
1951 cmp_attr => "return 1;",
1952 emit => '. fxch %X0',
1953 attr_type => "ia32_x87_attr_t",
1959 cmp_attr => "return 1;",
1960 emit => '. fld %X0',
1961 attr_type => "ia32_x87_attr_t",
1966 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1967 cmp_attr => "return 1;",
1968 emit => '. fld %X0',
1969 attr_type => "ia32_x87_attr_t",
1975 cmp_attr => "return 1;",
1976 emit => '. fstp %X0',
1977 attr_type => "ia32_x87_attr_t",
1983 op_flags => "L|X|Y",
1985 attr_type => "ia32_x87_attr_t",
1989 op_flags => "L|X|Y",
1991 attr_type => "ia32_x87_attr_t",
1995 op_flags => "L|X|Y",
1997 attr_type => "ia32_x87_attr_t",
2001 op_flags => "L|X|Y",
2003 attr_type => "ia32_x87_attr_t",
2007 op_flags => "L|X|Y",
2009 attr_type => "ia32_x87_attr_t",
2013 op_flags => "L|X|Y",
2015 attr_type => "ia32_x87_attr_t",
2019 # -------------------------------------------------------------------------------- #
2020 # ____ ____ _____ _ _ #
2021 # / ___/ ___|| ____| __ _____ ___| |_ ___ _ __ _ __ ___ __| | ___ ___ #
2022 # \___ \___ \| _| \ \ / / _ \/ __| __/ _ \| '__| | '_ \ / _ \ / _` |/ _ \/ __| #
2023 # ___) |__) | |___ \ V / __/ (__| || (_) | | | | | | (_) | (_| | __/\__ \ #
2024 # |____/____/|_____| \_/ \___|\___|\__\___/|_| |_| |_|\___/ \__,_|\___||___/ #
2026 # -------------------------------------------------------------------------------- #
2029 # Spilling and reloading of SSE registers, hardcoded, not generated #
2033 state => "exc_pinned",
2034 reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none" ] },
2035 emit => '. movdqu %D0, %AM',
2036 outs => [ "res", "M" ],
2042 state => "exc_pinned",
2043 reg_req => { in => [ "gp", "gp", "xmm", "none" ] },
2044 emit => '. movdqu %binop',
2051 # Include the generated SIMD node specification written by the SIMD optimization
2052 $my_script_name = dirname($myname) . "/../ia32/ia32_simd_spec.pl";
2053 unless ($return = do $my_script_name) {
2054 warn "couldn't parse $my_script_name: $@" if $@;
2055 warn "couldn't do $my_script_name: $!" unless defined $return;
2056 warn "couldn't run $my_script_name" unless $return;