3 # This is the specification for the ia32 assembler Firm-operations
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
8 # this string marks the beginning of a comment in emit
9 $comment_string = "/*";
11 # the number of additional opcodes you want to register
12 #$additional_opcodes = 0;
14 # The node description is done as a perl hash initializer with the
15 # following structure:
20 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
21 # "irn_flags" => "R|N|I"
22 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
23 # "state" => "floats|pinned|mem_pinned|exc_pinned",
25 # { "type" => "type 1", "name" => "name 1" },
26 # { "type" => "type 2", "name" => "name 2" },
29 # "comment" => "any comment for constructor",
30 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
31 # "cmp_attr" => "c source code for comparing node attributes",
32 # "emit" => "emit code with templates",
33 # "attr" => "attitional attribute arguments for constructor"
34 # "init_attr" => "emit attribute initialization template"
35 # "rd_constructor" => "c source code which constructs an ir_node"
38 # ... # (all nodes you need to describe)
40 # ); # close the %nodes initializer
42 # op_flags: flags for the operation, OPTIONAL (default is "N")
43 # the op_flags correspond to the firm irop_flags:
46 # C irop_flag_commutative
47 # X irop_flag_cfopcode
48 # I irop_flag_ip_cfopcode
51 # H irop_flag_highlevel
52 # c irop_flag_constlike
55 # irn_flags: special node flags, OPTIONAL (default is 0)
56 # following irn_flags are supported:
59 # I ignore for register allocation
61 # state: state of the operation, OPTIONAL (default is "floats")
63 # arity: arity of the operation, MUST NOT BE OMITTED
65 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
66 # are always the first 3 arguments and are always autmatically
68 # If this key is missing the following arguments will be created:
69 # for i = 1 .. arity: ir_node *op_i
72 # outs: if a node defines more than one output, the names of the projections
73 # nodes having outs having automatically the mode mode_T
75 # comment: OPTIONAL comment for the node constructor
77 # rd_constructor: for every operation there will be a
78 # new_rd_<arch>_<op-name> function with the arguments from above
79 # which creates the ir_node corresponding to the defined operation
80 # you can either put the complete source code of this function here
82 # This key is OPTIONAL. If omitted, the following constructor will
84 # if (!op_<arch>_<op-name>) assert(0);
88 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
91 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
95 # 1 - caller save (register must be saved by the caller of a function)
96 # 2 - callee save (register must be saved by the called function)
97 # 4 - ignore (do not assign this register)
98 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
101 { "name" => "eax", "type" => 1 },
102 { "name" => "edx", "type" => 1 },
103 { "name" => "ebx", "type" => 2 },
104 { "name" => "ecx", "type" => 1 },
105 { "name" => "esi", "type" => 2 },
106 { "name" => "edi", "type" => 2 },
107 { "name" => "ebp", "type" => 2 },
108 { "name" => "esp", "type" => 4 },
109 { "name" => "gp_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
110 { "name" => "gp_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
111 { "mode" => "mode_P" }
114 { "name" => "xmm0", "type" => 1 },
115 { "name" => "xmm1", "type" => 1 },
116 { "name" => "xmm2", "type" => 1 },
117 { "name" => "xmm3", "type" => 1 },
118 { "name" => "xmm4", "type" => 1 },
119 { "name" => "xmm5", "type" => 1 },
120 { "name" => "xmm6", "type" => 1 },
121 { "name" => "xmm7", "type" => 1 },
122 { "name" => "xmm_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
123 { "name" => "xmm_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
124 { "mode" => "mode_D" }
127 { "name" => "vf0", "type" => 1 },
128 { "name" => "vf1", "type" => 1 },
129 { "name" => "vf2", "type" => 1 },
130 { "name" => "vf3", "type" => 1 },
131 { "name" => "vf4", "type" => 1 },
132 { "name" => "vf5", "type" => 1 },
133 { "name" => "vf6", "type" => 1 },
134 { "name" => "vf7", "type" => 1 },
135 { "name" => "vfp_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
136 { "name" => "vfp_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
137 { "mode" => "mode_E" }
140 { "name" => "st0", "type" => 1 },
141 { "name" => "st1", "type" => 1 },
142 { "name" => "st2", "type" => 1 },
143 { "name" => "st3", "type" => 1 },
144 { "name" => "st4", "type" => 1 },
145 { "name" => "st5", "type" => 1 },
146 { "name" => "st6", "type" => 1 },
147 { "name" => "st7", "type" => 1 },
148 { "name" => "st_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
149 { "name" => "st_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
150 { "mode" => "mode_E" }
154 #--------------------------------------------------#
157 # _ __ _____ __ _ _ __ ___ _ __ ___ #
158 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
159 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
160 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
163 #--------------------------------------------------#
170 #-----------------------------------------------------------------#
173 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
174 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
175 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
176 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
179 #-----------------------------------------------------------------#
181 # commutative operations
184 # All nodes supporting Addressmode have 5 INs:
185 # 1 - base r1 == NoReg in case of no AM or no base
186 # 2 - index r2 == NoReg in case of no AM or no index
187 # 3 - op1 r3 == always present
188 # 4 - op2 r4 == NoReg in case of immediate operation
189 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
193 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
194 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
195 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
196 "emit" => '. add %ia32_emit_binop /* Add(%A1, %A2) -> %D1 */',
197 "outs" => [ "res", "M" ],
202 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
203 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
204 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
205 "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */',
206 "outs" => [ "res", "M" ],
209 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
211 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
212 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
213 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r3", "edx in_r4" ] },
214 "emit" => '. imul %ia32_emit_binop /* Mulh(%A1, %A2) -> %D1 */',
215 "outs" => [ "EAX", "EDX", "M" ],
220 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
221 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
222 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
223 "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */',
224 "outs" => [ "res", "M" ],
229 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
230 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
231 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
232 "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */',
233 "outs" => [ "res", "M" ],
238 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
239 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
240 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
241 "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */',
242 "outs" => [ "res", "M" ],
247 "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
248 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
250 '2. cmp %S1, %S2 /* prepare Max (%S1 - %S2), (%A1, %A2) */
251 if (mode_is_signed(get_irn_mode(n))) {
252 4. cmovl %D1, %S2 /* %S1 is less %S2 */
255 4. cmovb %D1, %S2 /* %S1 is below %S2 */
262 "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
263 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
265 '2. cmp %S1, %S2 /* prepare Min (%S1 - %S2), (%A1, %A2) */
266 if (mode_is_signed(get_irn_mode(n))) {
267 2. cmovg %D1, %S2 /* %S1 is greater %S2 */
270 2. cmova %D1, %S2, %D1 /* %S1 is above %S2 */
277 "comment" => "construct Mux: Mux(sel, a, b) == sel ? a : b",
278 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r2" ] },
280 '. cmp %S1, 0 /* compare Sel for CMov (%A2, %A3) */
281 . cmovne %D1, %S3 /* sel == true -> return %S3 */
285 # not commutative operations
289 "comment" => "construct Sub: Sub(a, b) = a - b",
290 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
291 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
292 "emit" => '. sub %ia32_emit_binop /* Sub(%A1, %A2) -> %D1 */',
293 "outs" => [ "res", "M" ],
298 "state" => "exc_pinned",
299 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "eax in_r1", "edx in_r3" ] },
300 "attr" => "ia32_op_flavour_t dm_flav",
301 "init_attr" => " attr->data.op_flav = dm_flav;",
302 "cmp_attr" => " return attr_a->data.op_flav != attr_b->data.op_flav;\n",
304 ' if (mode_is_signed(get_irn_mode(n))) {
305 4. idiv %S2 /* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
308 4. div %S2 /* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
311 "outs" => [ "div_res", "mod_res", "M" ],
316 "comment" => "construct Shl: Shl(a, b) = a << b",
317 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
318 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
319 "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */',
320 "outs" => [ "res", "M" ],
325 "comment" => "construct Shr: Shr(a, b) = a >> b",
326 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
327 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
328 "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */',
329 "outs" => [ "res", "M" ],
334 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
335 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
336 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
337 "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */',
338 "outs" => [ "res", "M" ],
343 "comment" => "construct RotR: RotR(a, b) = a ROTR b",
344 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
345 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
346 "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */',
347 "outs" => [ "res", "M" ],
352 "comment" => "construct RotL: RotL(a, b) = a ROTL b",
353 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
354 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
355 "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */',
356 "outs" => [ "res", "M" ],
363 "comment" => "construct Minus: Minus(a) = -a",
364 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
365 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
366 "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */',
367 "outs" => [ "res", "M" ],
372 "comment" => "construct Increment: Inc(a) = a++",
373 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
374 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
375 "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */',
376 "outs" => [ "res", "M" ],
381 "comment" => "construct Decrement: Dec(a) = a--",
382 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
383 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
384 "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */',
385 "outs" => [ "res", "M" ],
390 "comment" => "construct Not: Not(a) = !a",
391 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
392 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
393 "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */',
394 "outs" => [ "res", "M" ],
400 "op_flags" => "L|X|Y",
401 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
402 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
403 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
404 "outs" => [ "false", "true" ],
408 "op_flags" => "L|X|Y",
409 "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
410 "reg_req" => { "in" => [ "gp", "gp" ] },
411 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
412 "outs" => [ "false", "true" ],
416 "op_flags" => "L|X|Y",
417 "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
418 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
419 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
420 "outs" => [ "false", "true" ],
424 "op_flags" => "L|X|Y",
425 "comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
426 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
427 "reg_req" => { "in" => [ "gp", "gp" ] },
431 "op_flags" => "L|X|Y",
432 "comment" => "construct switch",
433 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
434 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
440 "comment" => "represents an integer constant",
441 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
442 "reg_req" => { "out" => [ "gp" ] },
447 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
448 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
449 "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */',
450 "outs" => [ "EAX", "EDX" ],
458 "state" => "exc_pinned",
459 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
460 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
461 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
463 ' if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) {
464 4. mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
467 4. mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
470 "outs" => [ "res", "M" ],
475 "state" => "exc_pinned",
476 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
477 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
478 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
479 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
485 "state" => "exc_pinned",
486 "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
487 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
488 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
489 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
495 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
496 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
497 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
498 "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */'
502 "comment" => "push a gp register on the stack",
503 "reg_req" => { "in" => [ "esp", "gp", "none" ], "out" => [ "esp" ] },
504 "emit" => '. push %S2 /* Push(%A2) */',
505 "outs" => [ "stack", "M" ],
509 "comment" => "pop a gp register from the stack",
510 "reg_req" => { "in" => [ "esp", "none" ], "out" => [ "gp", "esp" ] },
511 "emit" => '. pop %D1 /* Pop -> %D1 */',
512 "outs" => [ "res", "stack", "M" ],
516 "comment" => "create stack frame",
517 "reg_req" => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] },
518 "emit" => '. enter /* Enter */',
519 "outs" => [ "frame", "stack", "M" ],
523 "comment" => "destroy stack frame",
524 "reg_req" => { "in" => [ "esp", "ebp" ], "out" => [ "ebp", "esp" ] },
525 "emit" => '. leave /* Leave */',
526 "outs" => [ "frame", "stack", "M" ],
529 #-----------------------------------------------------------------------------#
530 # _____ _____ ______ __ _ _ _ #
531 # / ____/ ____| ____| / _| | | | | | #
532 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
533 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
534 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
535 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
536 #-----------------------------------------------------------------------------#
538 # commutative operations
542 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
543 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
544 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
545 "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */',
546 "outs" => [ "res", "M" ],
551 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
552 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
553 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
554 "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */',
555 "outs" => [ "res", "M" ],
560 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
561 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
562 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
563 "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */',
564 "outs" => [ "res", "M" ],
569 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
570 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
571 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
572 "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */',
573 "outs" => [ "res", "M" ],
578 "comment" => "construct SSE And: And(a, b) = a AND b",
579 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
580 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
581 "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */',
582 "outs" => [ "res", "M" ],
587 "comment" => "construct SSE Or: Or(a, b) = a OR b",
588 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
589 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
590 "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */',
591 "outs" => [ "res", "M" ],
596 "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
597 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
598 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
599 "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */',
600 "outs" => [ "res", "M" ],
603 # not commutative operations
607 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
608 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
609 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
610 "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */',
611 "outs" => [ "res", "M" ],
616 "comment" => "construct SSE Div: Div(a, b) = a / b",
617 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
618 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
619 "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */',
620 "outs" => [ "res", "M" ],
626 "op_flags" => "L|X|Y",
627 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
628 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
629 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
630 "outs" => [ "false", "true" ],
636 "comment" => "represents a SSE constant",
637 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
638 "reg_req" => { "out" => [ "xmm" ] },
639 "emit" => '. mov%M %D1, %C /* Load fConst into register */',
647 "state" => "exc_pinned",
648 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
649 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
650 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm" ] },
651 "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */',
652 "outs" => [ "res", "M" ],
657 "state" => "exc_pinned",
658 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
659 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
660 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
661 "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */',
670 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
671 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "none" ] },
677 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
678 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
679 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "none" ] },
685 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
686 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
687 "comment" => "construct Conv Int -> Int",
688 "outs" => [ "res", "M" ],
692 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
693 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
694 "comment" => "construct Conv Int -> Int",
695 "outs" => [ "res", "M" ],
699 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
700 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
701 "comment" => "construct Conv Int -> Floating Point",
702 "outs" => [ "res", "M" ],
706 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
707 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
708 "comment" => "construct Conv Floating Point -> Int",
709 "outs" => [ "res", "M" ],
713 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
714 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
715 "comment" => "construct Conv Floating Point -> Floating Point",
716 "outs" => [ "res", "M" ],
719 #----------------------------------------------------------#
721 # (_) | | | | / _| | | | #
722 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
723 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
724 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
725 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
727 # _ __ ___ __| | ___ ___ #
728 # | '_ \ / _ \ / _` |/ _ \/ __| #
729 # | | | | (_) | (_| | __/\__ \ #
730 # |_| |_|\___/ \__,_|\___||___/ #
731 #----------------------------------------------------------#
735 "comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
736 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
737 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
738 "outs" => [ "res", "M" ],
743 "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a + b",
744 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
745 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
746 "outs" => [ "res", "M" ],
751 "comment" => "virtual fp Sub: Sub(a, b) = a - b",
752 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
753 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
754 "outs" => [ "res", "M" ],
758 "comment" => "virtual fp Div: Div(a, b) = a / b",
759 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
760 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
761 "outs" => [ "res", "M" ],
766 "comment" => "virtual fp Abs: Abs(a) = |a|",
767 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
772 "comment" => "virtual fp Chs: Chs(a) = -a",
773 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
778 "comment" => "virtual fp Sin: Sin(a) = sin(a)",
779 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
784 "comment" => "virtual fp Cos: Cos(a) = cos(a)",
785 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
790 "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
791 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
794 # virtual Load and Store
799 "state" => "exc_pinned",
800 "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
801 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
802 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
803 "outs" => [ "res", "M" ],
808 "state" => "exc_pinned",
809 "comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
810 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
811 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
819 "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
820 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
821 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
822 "outs" => [ "res", "M" ],
826 "comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
827 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
828 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
836 "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg",
837 "reg_req" => { "out" => [ "vfp" ] },
842 "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg",
843 "reg_req" => { "out" => [ "vfp" ] },
848 "comment" => "virtual fp Load pi: Ld pi -> reg",
849 "reg_req" => { "out" => [ "vfp" ] },
854 "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg",
855 "reg_req" => { "out" => [ "vfp" ] },
860 "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg",
861 "reg_req" => { "out" => [ "vfp" ] },
866 "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg",
867 "reg_req" => { "out" => [ "vfp" ] },
872 "comment" => "virtual fp Load ld e: Ld ld e -> reg",
873 "reg_req" => { "out" => [ "vfp" ] },
879 "comment" => "represents a virtual floating point constant",
880 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
881 "reg_req" => { "out" => [ "vfp" ] },
884 #------------------------------------------------------------------------#
885 # ___ _____ __ _ _ _ #
886 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
887 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
888 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
889 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
890 #------------------------------------------------------------------------#
894 "rd_constructor" => "NONE",
895 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
897 "emit" => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */',
902 "rd_constructor" => "NONE",
903 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
905 "emit" => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */',
910 "rd_constructor" => "NONE",
911 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
913 "emit" => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */',
918 "rd_constructor" => "NONE",
919 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
921 "emit" => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */',,
926 "rd_constructor" => "NONE",
927 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
929 "emit" => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */',
934 "rd_constructor" => "NONE",
935 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
937 "emit" => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */',
942 "rd_constructor" => "NONE",
944 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
946 "emit" => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */',
951 "rd_constructor" => "NONE",
953 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
955 "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */',
960 "rd_constructor" => "NONE",
961 "comment" => "x87 fp Div: Div(a, b) = a / b",
963 "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */',
968 "rd_constructor" => "NONE",
969 "comment" => "x87 fp Div: Div(a, b) = a / b",
971 "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */',
976 "rd_constructor" => "NONE",
977 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
979 "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */',
984 "rd_constructor" => "NONE",
985 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
987 "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */',
992 "rd_constructor" => "NONE",
993 "comment" => "x87 fp Abs: Abs(a) = |a|",
995 "emit" => '. fabs /* x87 fabs(%S1) -> %D1 */',
1000 "rd_constructor" => "NONE",
1001 "comment" => "x87 fp Chs: Chs(a) = -a",
1003 "emit" => '. fchs /* x87 fchs(%S1) -> %D1 */',
1008 "rd_constructor" => "NONE",
1009 "comment" => "x87 fp Sin: Sin(a) = sin(a)",
1011 "emit" => '. fsin /* x87 sin(%S1) -> %D1 */',
1016 "rd_constructor" => "NONE",
1017 "comment" => "x87 fp Cos: Cos(a) = cos(a)",
1019 "emit" => '. fcos /* x87 cos(%S1) -> %D1 */',
1024 "rd_constructor" => "NONE",
1025 "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1027 "emit" => '. fsqrt $ /* x87 sqrt(%S1) -> %D1 */',
1030 # x87 Load and Store
1033 "rd_constructor" => "NONE",
1034 "op_flags" => "R|L|F",
1035 "state" => "exc_pinned",
1036 "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1038 "emit" => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */',
1042 "rd_constructor" => "NONE",
1043 "op_flags" => "R|L|F",
1044 "state" => "exc_pinned",
1045 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1047 "emit" => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */',
1051 "rd_constructor" => "NONE",
1052 "op_flags" => "R|L|F",
1053 "state" => "exc_pinned",
1054 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1056 "emit" => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */',
1064 "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1066 "emit" => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */',
1071 "rd_constructor" => "NONE",
1072 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1074 "emit" => '. fist %ia32_emit_am /* integer Store(%A3) -> (%A1) */',
1079 "rd_constructor" => "NONE",
1080 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1082 "emit" => '. fistp %ia32_emit_am /* integer Store(%A3) -> (%A1) and pop */',
1089 "rd_constructor" => "NONE",
1090 "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
1092 "emit" => '. fldz /* x87 0.0 -> %D1 */',
1097 "rd_constructor" => "NONE",
1098 "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
1100 "emit" => '. fld1 /* x87 1.0 -> %D1 */',
1105 "rd_constructor" => "NONE",
1106 "comment" => "x87 fp Load pi: Ld pi -> reg",
1108 "emit" => '. fldpi /* x87 pi -> %D1 */',
1113 "rd_constructor" => "NONE",
1114 "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
1116 "emit" => '. fldln2 /* x87 ln(2) -> %D1 */',
1121 "rd_constructor" => "NONE",
1122 "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
1124 "emit" => '. fldlg2 /* x87 log(2) -> %D1 */',
1129 "rd_constructor" => "NONE",
1130 "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
1132 "emit" => '. fldll2t /* x87 ld(10) -> %D1 */',
1137 "rd_constructor" => "NONE",
1138 "comment" => "x87 fp Load ld e: Ld ld e -> reg",
1140 "emit" => '. fldl2e /* x87 ld(e) -> %D1 */',
1147 "comment" => "represents a x87 constant",
1148 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1149 "reg_req" => { "out" => [ "st" ] },
1150 "emit" => '. fld%M %C /* Load fConst into register -> %D1 */',
1154 # Note that it is NEVER allowed to do CSE on these nodes
1157 "op_flags" => "R|K",
1158 "comment" => "x87 stack exchange",
1159 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1160 "cmp_attr" => " return 1;\n",
1161 "emit" => '. fxch %X1 /* x87 swap %X1, %X3 */',
1166 "comment" => "x87 stack push",
1167 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1168 "cmp_attr" => " return 1;\n",
1169 "emit" => '. fld %X1 /* x87 push %X1 */',