3 # This is the specification for the ia32 assembler Firm-operations
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
9 # The node description is done as a perl hash initializer with the
10 # following structure:
15 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
16 # "irn_flags" => "R|N|I"
17 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
18 # "state" => "floats|pinned|mem_pinned|exc_pinned",
20 # { "type" => "type 1", "name" => "name 1" },
21 # { "type" => "type 2", "name" => "name 2" },
24 # "comment" => "any comment for constructor",
25 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
26 # "cmp_attr" => "c source code for comparing node attributes",
27 # "emit" => "emit code with templates",
28 # "rd_constructor" => "c source code which constructs an ir_node"
31 # ... # (all nodes you need to describe)
33 # ); # close the %nodes initializer
35 # op_flags: flags for the operation, OPTIONAL (default is "N")
36 # the op_flags correspond to the firm irop_flags:
39 # C irop_flag_commutative
40 # X irop_flag_cfopcode
41 # I irop_flag_ip_cfopcode
44 # H irop_flag_highlevel
45 # c irop_flag_constlike
48 # irn_flags: special node flags, OPTIONAL (default is 0)
49 # following irn_flags are supported:
52 # I ignore for register allocation
54 # state: state of the operation, OPTIONAL (default is "floats")
56 # arity: arity of the operation, MUST NOT BE OMITTED
58 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
59 # are always the first 3 arguments and are always autmatically
61 # If this key is missing the following arguments will be created:
62 # for i = 1 .. arity: ir_node *op_i
65 # comment: OPTIONAL comment for the node constructor
67 # rd_constructor: for every operation there will be a
68 # new_rd_<arch>_<op-name> function with the arguments from above
69 # which creates the ir_node corresponding to the defined operation
70 # you can either put the complete source code of this function here
72 # This key is OPTIONAL. If omitted, the following constructor will
74 # if (!op_<arch>_<op-name>) assert(0);
78 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
81 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
85 # 1 - caller save (register must be saved by the caller of a function)
86 # 2 - callee save (register must be saved by the called function)
87 # 4 - ignore (do not assign this register)
88 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
91 { "name" => "eax", "type" => 1 },
92 { "name" => "edx", "type" => 1 },
93 { "name" => "ebx", "type" => 2 },
94 { "name" => "ecx", "type" => 1 },
95 { "name" => "esi", "type" => 2 },
96 { "name" => "edi", "type" => 2 },
97 { "name" => "ebp", "type" => 2 },
98 { "name" => "esp", "type" => 6 },
99 { "name" => "xxx", "type" => 6 }, # we need a dummy register for NoReg and Unknown nodes
100 { "mode" => "mode_P" }
103 { "name" => "xmm0", "type" => 1 },
104 { "name" => "xmm1", "type" => 1 },
105 { "name" => "xmm2", "type" => 1 },
106 { "name" => "xmm3", "type" => 1 },
107 { "name" => "xmm4", "type" => 1 },
108 { "name" => "xmm5", "type" => 1 },
109 { "name" => "xmm6", "type" => 1 },
110 { "name" => "xmm7", "type" => 1 },
111 { "name" => "xxxx", "type" => 6 }, # we need a dummy register for NoReg and Unknown nodes
112 { "mode" => "mode_D" }
116 #--------------------------------------------------#
119 # _ __ _____ __ _ _ __ ___ _ __ ___ #
120 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
121 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
122 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
125 #--------------------------------------------------#
129 #-----------------------------------------------------------------#
132 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
133 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
134 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
135 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
138 #-----------------------------------------------------------------#
140 # commutative operations
143 # All nodes supporting Addressmode have 5 INs:
144 # 1 - base r1 == NoReg in case of no AM or no base
145 # 2 - index r2 == NoReg in case of no AM or no index
146 # 3 - op1 r3 == always present
147 # 4 - op2 r4 == NoReg in case of immediate operation
148 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
152 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
153 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
154 "emit" => '. add %ia32_emit_binop\t\t\t/* Add(%A1, %A2) -> %D1 */'
159 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
160 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
161 "emit" => '. imul %ia32_emit_binop\t\t\t/* Mul(%A1, %A2) -> %D1 */'
164 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
166 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
167 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r1", "edx in_r2" ] },
168 "emit" => '. imul %ia32_emit_unop\t\t\t/* Mulh(%A1, %A2) -> %D1 */ '
173 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
174 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
175 "emit" => '. and %ia32_emit_binop\t\t\t/* And(%A1, %A2) -> %D1 */'
180 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
181 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
182 "emit" => '. or %ia32_emit_binop\t\t\t/* Or(%A1, %A2) -> %D1 */'
187 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
188 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
189 "emit" => '. xor %ia32_emit_binop\t\t\t/* Xor(%A1, %A2) -> %D1 */'
194 "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
195 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
197 '2. cmp %S1, %S2\t\t\t/* prepare Max (%S1 - %S2), (%A1, %A2) */
198 if (mode_is_signed(get_irn_mode(n))) {
199 4. cmovl %D1, %S2\t\t\t/* %S1 is less %S2 */
202 4. cmovb %D1, %S2\t\t\t/* %S1 is below %S2 */
209 "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
210 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
212 '2. cmp %S1, %S2\t\t\t/* prepare Min (%S1 - %S2), (%A1, %A2) */
213 if (mode_is_signed(get_irn_mode(n))) {
214 2. cmovg %D1, %S2\t\t\t/* %S1 is greater %S2 */
217 2. cmova %D1, %S2, %D1\t\t\t/* %S1 is above %S2 */
224 "comment" => "construct Mux: Mux(sel, a, b) == sel ? a : b",
225 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r2" ] },
227 '. cmp %S1, 0\t\t\t/* compare Sel for CMov (%A2, %A3) */
228 . cmovne %D1, %S3\t\t\t/* sel == true -> return %S3 */
232 # not commutative operations
236 "comment" => "construct Sub: Sub(a, b) = a - b",
237 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
238 "emit" => '. sub %ia32_emit_binop\t\t\t/* Sub(%A1, %A2) -> %D1 */'
243 "state" => "exc_pinned",
244 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "eax in_r1", "edx in_r3" ] },
246 ' if (mode_is_signed(get_irn_mode(n))) {
247 4. idiv %S2\t\t\t/* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
250 4. div %S2\t\t\t/* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
257 "comment" => "construct Shl: Shl(a, b) = a << b",
258 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r1" ] },
259 "emit" => '. shl %ia32_emit_binop\t\t\t/* Shl(%A1, %A2) -> %D1 */'
264 "comment" => "construct Shr: Shr(a, b) = a >> b",
265 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r1" ] },
266 "emit" => '. shr %ia32_emit_binop\t\t\t/* Shr(%A1, %A2) -> %D1 */'
271 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
272 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r1" ] },
273 "emit" => '. sar %ia32_emit_binop\t\t\t/* Shrs(%A1, %A2) -> %D1 */'
278 "comment" => "construct RotR: RotR(a, b) = a ROTR b",
279 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r1" ] },
280 "emit" => '. ror %ia32_emit_binop\t\t\t/* RotR(%A1, %A2) -> %D1 */'
285 "comment" => "construct RotL: RotL(a, b) = a ROTL b",
286 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r1" ] },
287 "emit" => '. rol %ia32_emit_binop\t\t\t/* RotL(%A1, %A2) -> %D1 */'
294 "comment" => "construct Minus: Minus(a) = -a",
295 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
296 "emit" => '. neg %ia32_emit_unop\t\t\t/* Neg(%A1) -> %D1, (%A1) */'
301 "comment" => "construct Increment: Inc(a) = a++",
302 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
303 "emit" => '. inc %ia32_emit_unop\t\t\t/* Inc(%S1) -> %D1, (%A1) */'
308 "comment" => "construct Decrement: Dec(a) = a--",
309 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
310 "emit" => '. dec %ia32_emit_unop\t\t\t/* Dec(%S1) -> %D1, (%A1) */'
315 "comment" => "construct Not: Not(a) = !a",
316 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
317 "emit" => '. not %ia32_emit_unop\t\t\t/* Not(%S1) -> %D1, (%A1) */'
323 "reg_req" => { "in" => [ "gp" ], "out" => [ "in_r1" ] },
324 "comment" => "construct Conv: Conv(a) = (conv)a"
328 "op_flags" => "L|X|Y",
329 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
330 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
334 "op_flags" => "L|X|Y",
335 "comment" => "construct switch",
336 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "none" ] },
342 "comment" => "represents an integer constant",
343 "reg_req" => { "out" => [ "gp" ] },
344 "emit" => '. mov %D1, %C\t\t\t/* Mov Const into register */',
347 if (attr_a->data.tp == attr_b->data.tp) {
348 if (attr_a->data.tp == ia32_SymConst) {
349 if (attr_a->sc == NULL || attr_b->sc == NULL)
352 return strcmp(attr_a->sc, attr_b->sc);
355 if (attr_a->tv == NULL || attr_b->tv == NULL)
358 if (tarval_cmp(attr_a->tv, attr_b->tv) == pn_Cmp_Eq)
371 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
372 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
373 "emit" => '. cdq\t\t\t/* sign extend EAX -> EDX:EAX, (%A1) */'
381 "state" => "exc_pinned",
382 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
383 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
384 "emit" => '. mov %D1, %ia32_emit_am\t\t\t/* Load((%A1)) -> %D1 */'
389 "state" => "exc_pinned",
390 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
391 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
392 "emit" => '. mov %ia32_emit_am, %S3\t\t\t/* Store(%A2) -> (%A1) */'
397 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
398 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
399 "emit" => '. lea %D1, %ia32_emit_am\t\t/* %D1 = %S1 + %S2 << %C + %O, (%A1, %A2) */'
402 #--------------------------------------------------------#
405 # | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
406 # | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
407 # | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
408 # |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
409 #--------------------------------------------------------#
411 # commutative operations
415 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
416 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r1" ] },
417 "emit" => '. adds%M %ia32_emit_binop\t\t\t/* SSE Add(%A1, %A2) -> %D1 */'
422 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
423 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
424 "emit" => '. muls%M %ia32_emit_binop\t\t\t/* SSE Mul(%A1, %A2) -> %D1 */'
429 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
430 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
431 "emit" => '. maxs%M %ia32_emit_binop\t\t\t/* SSE Max(%A1, %A2) -> %D1 */'
436 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
437 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
438 "emit" => '. mins%M %ia32_emit_binop\t\t\t/* SSE Min(%A1, %A2) -> %D1 */'
443 "comment" => "construct SSE And: And(a, b) = a AND b",
444 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
445 "emit" => '. andp%M %ia32_emit_binop\t\t\t/* SSE And(%A3, %A4) -> %D1 */'
450 "comment" => "construct SSE Or: Or(a, b) = a OR b",
451 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
452 "emit" => '. orp%M %ia32_emit_binop\t\t\t/* SSE Or(%A3, %A4) -> %D1 */'
457 "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
458 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
459 "emit" => '. xorp%M %ia32_emit_binop\t\t\t/* SSE Xor(%A3, %A4) -> %D1 */'
462 # not commutative operations
466 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
467 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r1" ] },
468 "emit" => '. subs%M %ia32_emit_binop\t\t\t/* SSE Sub(%A1, %A2) -> %D1 */'
473 "comment" => "construct SSE Div: Div(a, b) = a / b",
474 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r1" ] },
475 "emit" => '. divs%M %ia32_emit_binop\t\t\t/* SSE Div(%A1, %A2) -> %D1 */'
481 "reg_req" => { "in" => [ "fp" ], "out" => [ "gp" ] },
482 "comment" => "construct Conv: Conv(a) = (conv)a"
486 "op_flags" => "L|X|Y",
487 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
488 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "none", "none" ] },
494 "comment" => "represents a SSE constant",
495 "reg_req" => { "out" => [ "fp" ] },
496 "emit" => '. mov%M %D1, %C\t\t\t/* Load fConst into register */',
499 if (attr_a->data.tp == attr_b->data.tp) {
500 if (attr_a->data.tp == ia32_SymConst) {
501 if (attr_a->sc == NULL || attr_b->sc == NULL)
504 return strcmp(attr_a->sc, attr_b->sc);
507 if (attr_a->tv == NULL || attr_b->tv == NULL)
510 if (tarval_cmp(attr_a->tv, attr_b->tv) == pn_Cmp_Eq)
526 "state" => "exc_pinned",
527 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
528 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "fp" ] },
529 "emit" => '. movs%M %D1, %ia32_emit_am\t\t\t/* Load((%A1)) -> %D1 */'
534 "state" => "exc_pinned",
535 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
536 "reg_req" => { "in" => [ "gp", "gp", "fp", "none" ] },
537 "emit" => '. movs%M %ia32_emit_am, %S3\t\t\t/* Store(%S3) -> (%A1) */'
545 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
546 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "none" ] },
552 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
553 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "none" ] },
560 "state" => "mem_pinned",
561 "arity" => "variable",
562 "comment" => "construct Call: Call(...)",
564 { "type" => "int", "name" => "n" },
565 { "type" => "ir_node **", "name" => "in" }
568 " if (!op_ia32_Call) assert(0);
569 return new_ir_node(db, irg, block, op_ia32_Call, mode_T, n, in);