3 # This is the specification for the ia32 assembler Firm-operations
7 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
10 # The node description is done as a perl hash initializer with the
11 # following structure:
16 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
17 # "irn_flags" => "R|N|I|S"
18 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
19 # "state" => "floats|pinned|mem_pinned|exc_pinned",
21 # { "type" => "type 1", "name" => "name 1" },
22 # { "type" => "type 2", "name" => "name 2" },
25 # "comment" => "any comment for constructor",
26 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
27 # "cmp_attr" => "c source code for comparing node attributes",
28 # "emit" => "emit code with templates",
29 # "attr" => "attitional attribute arguments for constructor"
30 # "init_attr" => "emit attribute initialization template"
31 # "rd_constructor" => "c source code which constructs an ir_node"
32 # "latency" => "latency of this operation (can be float)"
35 # ... # (all nodes you need to describe)
37 # ); # close the %nodes initializer
39 # op_flags: flags for the operation, OPTIONAL (default is "N")
40 # the op_flags correspond to the firm irop_flags:
43 # C irop_flag_commutative
44 # X irop_flag_cfopcode
45 # I irop_flag_ip_cfopcode
48 # H irop_flag_highlevel
49 # c irop_flag_constlike
52 # irn_flags: special node flags, OPTIONAL (default is 0)
53 # following irn_flags are supported:
56 # I ignore for register allocation
57 # S modifies stack pointer
59 # state: state of the operation, OPTIONAL (default is "floats")
61 # arity: arity of the operation, MUST NOT BE OMITTED
63 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
64 # are always the first 3 arguments and are always autmatically
66 # If this key is missing the following arguments will be created:
67 # for i = 1 .. arity: ir_node *op_i
70 # outs: if a node defines more than one output, the names of the projections
71 # nodes having outs having automatically the mode mode_T
72 # One can also annotate some flags for each out, additional to irn_flags.
73 # They are separated from name with a colon ':', and concatenated by pipe '|'
74 # Only I and S are available at the moment (same meaning as in irn_flags).
75 # example: [ "frame:I", "stack:I|S", "M" ]
77 # comment: OPTIONAL comment for the node constructor
79 # rd_constructor: for every operation there will be a
80 # new_rd_<arch>_<op-name> function with the arguments from above
81 # which creates the ir_node corresponding to the defined operation
82 # you can either put the complete source code of this function here
84 # This key is OPTIONAL. If omitted, the following constructor will
86 # if (!op_<arch>_<op-name>) assert(0);
90 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
93 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
95 # latency: the latency of the operation, default is 1
100 # 1 - caller save (register must be saved by the caller of a function)
101 # 2 - callee save (register must be saved by the called function)
102 # 4 - ignore (do not assign this register)
103 # 8 - emitter can choose an arbitrary register of this class
104 # 16 - the register is a virtual one
105 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
108 { "name" => "eax", "type" => 1 },
109 { "name" => "edx", "type" => 1 },
110 { "name" => "ebx", "type" => 2 },
111 { "name" => "ecx", "type" => 1 },
112 { "name" => "esi", "type" => 2 },
113 { "name" => "edi", "type" => 2 },
114 { "name" => "ebp", "type" => 2 },
115 { "name" => "esp", "type" => 4 },
116 { "name" => "gp_NOREG", "type" => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
117 { "name" => "gp_UKNWN", "type" => 4 | 8 | 16 }, # we need a dummy register for Unknown nodes
118 { "mode" => "mode_Iu" }
121 { "name" => "xmm0", "type" => 1 },
122 { "name" => "xmm1", "type" => 1 },
123 { "name" => "xmm2", "type" => 1 },
124 { "name" => "xmm3", "type" => 1 },
125 { "name" => "xmm4", "type" => 1 },
126 { "name" => "xmm5", "type" => 1 },
127 { "name" => "xmm6", "type" => 1 },
128 { "name" => "xmm7", "type" => 1 },
129 { "name" => "xmm_NOREG", "type" => 4 | 16 }, # we need a dummy register for NoReg nodes
130 { "name" => "xmm_UKNWN", "type" => 4 | 8 | 16}, # we need a dummy register for Unknown nodes
131 { "mode" => "mode_DLu" }
134 { "name" => "vf0", "type" => 1 | 16 },
135 { "name" => "vf1", "type" => 1 | 16 },
136 { "name" => "vf2", "type" => 1 | 16 },
137 { "name" => "vf3", "type" => 1 | 16 },
138 { "name" => "vf4", "type" => 1 | 16 },
139 { "name" => "vf5", "type" => 1 | 16 },
140 { "name" => "vf6", "type" => 1 | 16 },
141 { "name" => "vf7", "type" => 1 | 16 },
142 { "name" => "vfp_NOREG", "type" => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
143 { "name" => "vfp_UKNWN", "type" => 4 | 8 | 16 }, # we need a dummy register for Unknown nodes
144 { "mode" => "mode_E" }
147 { "name" => "st0", "type" => 1 },
148 { "name" => "st1", "type" => 1 },
149 { "name" => "st2", "type" => 1 },
150 { "name" => "st3", "type" => 1 },
151 { "name" => "st4", "type" => 1 },
152 { "name" => "st5", "type" => 1 },
153 { "name" => "st6", "type" => 1 },
154 { "name" => "st7", "type" => 1 },
155 { "mode" => "mode_E" }
157 "fp_cw" => [ # the floating point control word
158 { "name" => "fpcw", "type" => 0 },
159 { "mode" => "mode_Hu" },
165 "GP" => [ 1, "GP_EAX", "GP_EBX", "GP_ECX", "GP_EDX", "GP_ESI", "GP_EDI", "GP_EBP" ],
166 "SSE" => [ 1, "SSE_XMM0", "SSE_XMM1", "SSE_XMM2", "SSE_XMM3", "SSE_XMM4", "SSE_XMM5", "SSE_XMM6", "SSE_XMM7" ],
167 "VFP" => [ 1, "VFP_VF0", "VFP_VF1", "VFP_VF2", "VFP_VF3", "VFP_VF4", "VFP_VF5", "VFP_VF6", "VFP_VF7" ],
168 "BRANCH" => [ 1, "BRANCH1", "BRANCH2" ],
173 "bundels_per_cycle" => 1
177 "S1" => "${arch}_emit_source_register(env, node, 0);",
178 "S2" => "${arch}_emit_source_register(env, node, 1);",
179 "S3" => "${arch}_emit_source_register(env, node, 2);",
180 "S4" => "${arch}_emit_source_register(env, node, 3);",
181 "S5" => "${arch}_emit_source_register(env, node, 4);",
182 "S6" => "${arch}_emit_source_register(env, node, 5);",
183 "D1" => "${arch}_emit_dest_register(env, node, 0);",
184 "D2" => "${arch}_emit_dest_register(env, node, 1);",
185 "D3" => "${arch}_emit_dest_register(env, node, 2);",
186 "D4" => "${arch}_emit_dest_register(env, node, 3);",
187 "D5" => "${arch}_emit_dest_register(env, node, 4);",
188 "D6" => "${arch}_emit_dest_register(env, node, 5);",
189 "A1" => "${arch}_emit_in_node_name(env, node, 0);",
190 "A2" => "${arch}_emit_in_node_name(env, node, 1);",
191 "A3" => "${arch}_emit_in_node_name(env, node, 2);",
192 "A4" => "${arch}_emit_in_node_name(env, node, 3);",
193 "A5" => "${arch}_emit_in_node_name(env, node, 4);",
194 "A6" => "${arch}_emit_in_node_name(env, node, 5);",
195 "X1" => "${arch}_emit_x87_name(env, node, 0);",
196 "X2" => "${arch}_emit_x87_name(env, node, 1);",
197 "X3" => "${arch}_emit_x87_name(env, node, 2);",
198 "C" => "${arch}_emit_immediate(env, node);",
199 "SE" => "${arch}_emit_extend_suffix(env, get_ia32_ls_mode(node));",
200 "ME" => "if(get_mode_size_bits(get_ia32_ls_mode(node)) != 32)\n
201 ${arch}_emit_mode_suffix(env, get_ia32_ls_mode(node));",
202 "M" => "${arch}_emit_mode_suffix(env, get_ia32_ls_mode(node));",
203 "XM" => "${arch}_emit_x87_mode_suffix(env, node);",
204 "XXM" => "${arch}_emit_xmm_mode_suffix(env, node);",
205 "XSD" => "${arch}_emit_xmm_mode_suffix_s(env, node);",
206 "AM" => "${arch}_emit_am(env, node);",
207 "unop" => "${arch}_emit_unop(env, node);",
208 "binop" => "${arch}_emit_binop(env, node);",
209 "x87_binop" => "${arch}_emit_x87_binop(env, node);",
212 #--------------------------------------------------#
215 # _ __ _____ __ _ _ __ ___ _ __ ___ #
216 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
217 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
218 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
221 #--------------------------------------------------#
223 $default_cmp_attr = "return ia32_compare_attr(attr_a, attr_b);";
230 #-----------------------------------------------------------------#
233 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
234 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
235 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
236 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
239 #-----------------------------------------------------------------#
241 # commutative operations
244 # All nodes supporting Addressmode have 5 INs:
245 # 1 - base r1 == NoReg in case of no AM or no base
246 # 2 - index r2 == NoReg in case of no AM or no index
247 # 3 - op1 r3 == always present
248 # 4 - op2 r4 == NoReg in case of immediate operation
249 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
253 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
254 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
255 "emit" => '. addl %binop',
261 "comment" => "construct Add with Carry: Adc(a, b) = Add(b, a) = a + b + carry",
262 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
263 "emit" => '. adcl %binop',
270 "comment" => "construct 64Bit Add: Add(a_l, a_h, b_l, b_h) = a_l + b_l; a_h + b_h + carry",
272 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
279 "outs" => [ "low_res", "high_res" ],
286 "cmp_attr" => "return 1;",
287 "comment" => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
293 "cmp_attr" => "return 1;",
294 "comment" => "construct lowered Add with Carry: Adc(a, b) = Adc(b, a) = a + b + carry",
299 # we should not rematrialize this node. It produces 2 results and has
300 # very strict constrains
301 "comment" => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
302 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx", "none" ] },
303 "emit" => '. mull %unop',
304 "outs" => [ "EAX", "EDX", "M" ],
310 # we should not rematrialize this node. It produces 2 results and has
311 # very strict constrains
313 "cmp_attr" => "return 1;",
314 "comment" => "construct lowered MulS: Mul(a, b) = Mul(b, a) = a * b",
315 "outs" => [ "EAX", "EDX", "M" ],
321 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
322 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
323 "emit" => '. imull %binop',
331 "comment" => "construct Mul (1 operand format): Mul(a, b) = Mul(b, a) = a * b",
332 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx", "none" ] },
333 "emit" => '. imull %unop',
334 "outs" => [ "EAX", "EDX", "M" ],
341 "cmp_attr" => "return 1;",
342 "comment" => "construct lowered IMul: IMul(a, b) = IMul(b, a) = a * b",
348 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
349 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
350 "emit" => '. andl %binop',
357 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
358 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
359 "emit" => '. orl %binop',
366 "comment" => "construct Xor: Xor(a, b) = Xor(b, a) = a EOR b",
367 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
368 "emit" => '. xorl %binop',
375 "cmp_attr" => "return 1;",
376 "comment" => "construct lowered Xor: Xor(a, b) = Xor(b, a) = a XOR b",
380 # not commutative operations
384 "comment" => "construct Sub: Sub(a, b) = a - b",
385 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
386 "emit" => '. subl %binop',
392 "comment" => "construct Sub with Carry: SubC(a, b) = a - b - carry",
393 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3 !in_r4" ] },
394 "emit" => '. sbbl %binop',
401 "comment" => "construct 64Bit Sub: Sub(a_l, a_h, b_l, b_h) = a_l - b_l; a_h - b_h - borrow",
403 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
410 "outs" => [ "low_res", "high_res" ],
416 "cmp_attr" => "return 1;",
417 "comment" => "construct lowered Sub: Sub(a, b) = a - b",
422 "cmp_attr" => "return 1;",
423 "comment" => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
429 "state" => "exc_pinned",
430 "reg_req" => { "in" => [ "gp", "gp", "eax", "edx", "gp", "none" ], "out" => [ "eax", "edx", "none" ] },
431 "attr" => "ia32_op_flavour_t dm_flav",
432 "init_attr" => "attr->data.op_flav = dm_flav;",
433 "emit" => ". idivl %unop",
434 "outs" => [ "div_res", "mod_res", "M" ],
441 "state" => "exc_pinned",
442 "reg_req" => { "in" => [ "gp", "gp", "eax", "edx", "gp", "none" ], "out" => [ "eax", "edx", "none" ] },
443 "attr" => "ia32_op_flavour_t dm_flav",
444 "init_attr" => "attr->data.op_flav = dm_flav;",
445 "emit" => ". divl %unop",
446 "outs" => [ "div_res", "mod_res", "M" ],
453 "comment" => "construct Shl: Shl(a, b) = a << b",
454 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
455 "emit" => '. shll %binop',
461 "cmp_attr" => "return 1;",
462 "comment" => "construct lowered Shl: Shl(a, b) = a << b",
468 "comment" => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
469 # Out requirements is: different from all in
470 # This is because, out must be different from LowPart and ShiftCount.
471 # We could say "!ecx !in_r4" but it can occur, that all values live through
472 # this Shift and the only value dying is the ShiftCount. Then there would be a
473 # register missing, as result must not be ecx and all other registers are
474 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
475 # (and probably never will). So we create artificial interferences of the result
476 # with all inputs, so the spiller can always assure a free register.
477 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!in" ] },
480 if (get_ia32_immop_type(node) == ia32_ImmNone) {
481 if (get_ia32_op_type(node) == ia32_AddrModeD) {
482 . shldl %%cl, %S4, %AM
484 . shldl %%cl, %S4, %S3
487 if (get_ia32_op_type(node) == ia32_AddrModeD) {
488 . shldl $%C, %S4, %AM
490 . shldl $%C, %S4, %S3
500 "cmp_attr" => "return 1;",
501 "comment" => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
507 "comment" => "construct Shr: Shr(a, b) = a >> b",
508 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
509 "emit" => '. shrl %binop',
515 "cmp_attr" => "return 1;",
516 "comment" => "construct lowered Shr: Shr(a, b) = a << b",
522 "comment" => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
523 # Out requirements is: different from all in
524 # This is because, out must be different from LowPart and ShiftCount.
525 # We could say "!ecx !in_r4" but it can occur, that all values live through
526 # this Shift and the only value dying is the ShiftCount. Then there would be a
527 # register missing, as result must not be ecx and all other registers are
528 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
529 # (and probably never will). So we create artificial interferences of the result
530 # with all inputs, so the spiller can always assure a free register.
531 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!in" ] },
533 if (get_ia32_immop_type(node) == ia32_ImmNone) {
534 if (get_ia32_op_type(node) == ia32_AddrModeD) {
535 . shrdl %%cl, %S4, %AM
537 . shrdl %%cl, %S4, %S3
540 if (get_ia32_op_type(node) == ia32_AddrModeD) {
541 . shrdl $%C, %S4, %AM
543 . shrdl $%C, %S4, %S3
553 "cmp_attr" => "return 1;",
554 "comment" => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
560 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
561 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
562 "emit" => '. sarl %binop',
568 "cmp_attr" => "return 1;",
569 "comment" => "construct lowered Sar: Sar(a, b) = a << b",
575 "comment" => "construct Ror: Ror(a, b) = a ROR b",
576 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
577 "emit" => '. rorl %binop',
584 "comment" => "construct Rol: Rol(a, b) = a ROL b",
585 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
586 "emit" => '. roll %binop',
595 "comment" => "construct Minus: Minus(a) = -a",
596 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
597 "emit" => '. negl %unop',
604 "comment" => "construct 64Bit Minus: Minus(a_l, a_h, 0) = 0 - a_l; 0 - a_h - borrow",
606 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
613 "outs" => [ "low_res", "high_res" ],
619 "cmp_attr" => "return 1;",
620 "comment" => "construct lowered Minus: Minus(a) = -a",
626 "comment" => "construct Increment: Inc(a) = a++",
627 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
628 "emit" => '. incl %unop',
635 "comment" => "construct Decrement: Dec(a) = a--",
636 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
637 "emit" => '. decl %unop',
644 "comment" => "construct Not: Not(a) = !a",
645 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
646 "emit" => '. notl %unop',
654 "op_flags" => "L|X|Y",
655 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
656 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
657 "outs" => [ "false", "true" ],
659 "units" => [ "BRANCH" ],
663 "op_flags" => "L|X|Y",
664 "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
665 "reg_req" => { "in" => [ "gp", "gp" ] },
666 "outs" => [ "false", "true" ],
668 "units" => [ "BRANCH" ],
672 "op_flags" => "L|X|Y",
673 "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
674 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
675 "outs" => [ "false", "true" ],
676 "units" => [ "BRANCH" ],
680 "op_flags" => "L|X|Y",
681 "comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
682 "reg_req" => { "in" => [ "gp", "gp" ] },
683 "units" => [ "BRANCH" ],
687 "op_flags" => "L|X|Y",
688 "comment" => "construct switch",
689 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
691 "units" => [ "BRANCH" ],
697 "comment" => "represents an integer constant",
698 "reg_req" => { "out" => [ "gp" ] },
706 "comment" => "unknown value",
707 "reg_req" => { "out" => [ "gp_UKNWN" ] },
716 "comment" => "unknown value",
717 "reg_req" => { "out" => [ "vfp_UKNWN" ] },
726 "comment" => "unknown value",
727 "reg_req" => { "out" => [ "xmm_UKNWN" ] },
736 "comment" => "unknown GP value",
737 "reg_req" => { "out" => [ "gp_NOREG" ] },
746 "comment" => "unknown VFP value",
747 "reg_req" => { "out" => [ "vfp_NOREG" ] },
756 "comment" => "unknown XMM value",
757 "reg_req" => { "out" => [ "xmm_NOREG" ] },
765 "comment" => "change floating point control word",
766 "reg_req" => { "out" => [ "fp_cw" ] },
774 "state" => "exc_pinned",
775 "comment" => "load floating point control word FldCW(ptr, mem) = LD ptr -> reg",
776 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "fp_cw" ] },
778 "emit" => ". fldcw %AM",
785 "state" => "exc_pinned",
786 "comment" => "store floating point control word: FstCW(ptr, mem) = ST ptr -> reg",
787 "reg_req" => { "in" => [ "gp", "gp", "fp_cw", "none" ] },
789 "emit" => ". fstcw %AM",
795 # we should not rematrialize this node. It produces 2 results and has
796 # very strict constrains
797 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
798 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
800 "outs" => [ "EAX", "EDX" ],
808 "state" => "exc_pinned",
809 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
810 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp", "none" ] },
812 "emit" => ". mov%SE%ME%.l %AM, %D1",
813 "outs" => [ "res", "M" ],
819 "cmp_attr" => "return 1;",
820 "comment" => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg",
821 "outs" => [ "res", "M" ],
827 "cmp_attr" => "return 1;",
828 "state" => "exc_pinned",
829 "comment" => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val",
836 "state" => "exc_pinned",
837 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
838 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
839 "emit" => '. mov%M %binop',
847 "state" => "exc_pinned",
848 "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
849 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
850 "emit" => '. mov%M %binop',
858 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
859 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
860 "emit" => '. leal %AM, %D1',
867 "comment" => "push on the stack",
868 "reg_req" => { "in" => [ "gp", "gp", "gp", "esp", "none" ], "out" => [ "esp", "none" ] },
869 "emit" => '. pushl %unop',
870 "outs" => [ "stack:I|S", "M" ],
876 "comment" => "pop a gp register from the stack",
877 "reg_req" => { "in" => [ "gp", "gp", "esp", "none" ], "out" => [ "esp", "gp", "none" ] },
878 "emit" => '. popl %unop',
879 "outs" => [ "stack:I|S", "res", "M" ],
885 "comment" => "create stack frame",
886 "reg_req" => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] },
888 "outs" => [ "frame:I", "stack:I|S", "M" ],
894 "comment" => "destroy stack frame",
895 "reg_req" => { "in" => [ "esp", "ebp" ], "out" => [ "ebp", "esp" ] },
897 "outs" => [ "frame:I", "stack:I|S" ],
904 "comment" => "allocate space on stack",
905 "reg_req" => { "in" => [ "gp", "gp", "esp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
906 "emit" => '. addl %binop',
907 "outs" => [ "stack:S", "M" ],
913 "comment" => "free space on stack",
914 "reg_req" => { "in" => [ "gp", "gp", "esp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
915 "emit" => '. subl %binop',
916 "outs" => [ "stack:S", "M" ],
922 "comment" => "get the TLS base address",
923 "reg_req" => { "out" => [ "gp" ] },
929 #-----------------------------------------------------------------------------#
930 # _____ _____ ______ __ _ _ _ #
931 # / ____/ ____| ____| / _| | | | | | #
932 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
933 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
934 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
935 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
936 #-----------------------------------------------------------------------------#
938 # commutative operations
942 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
943 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
944 "emit" => '. add%XXM %binop',
946 "units" => [ "SSE" ],
952 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
953 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
954 "emit" => '. mul%XXM %binop',
956 "units" => [ "SSE" ],
962 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
963 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
964 "emit" => '. max%XXM %binop',
966 "units" => [ "SSE" ],
972 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
973 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
974 "emit" => '. min%XXM %binop',
976 "units" => [ "SSE" ],
982 "comment" => "construct SSE And: And(a, b) = a AND b",
983 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
984 "emit" => '. andp%XSD %binop',
986 "units" => [ "SSE" ],
992 "comment" => "construct SSE Or: Or(a, b) = a OR b",
993 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
994 "emit" => '. orp%XSD %binop',
995 "units" => [ "SSE" ],
1001 "comment" => "construct SSE Xor: Xor(a, b) = a XOR b",
1002 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
1003 "emit" => '. xorp%XSD %binop',
1005 "units" => [ "SSE" ],
1009 # not commutative operations
1013 "comment" => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
1014 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
1015 "emit" => '. andnp%XSD %binop',
1017 "units" => [ "SSE" ],
1023 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
1024 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
1025 "emit" => '. sub%XXM %binop',
1027 "units" => [ "SSE" ],
1033 "comment" => "construct SSE Div: Div(a, b) = a / b",
1034 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
1035 "outs" => [ "res", "M" ],
1036 "emit" => '. div%XXM %binop',
1038 "units" => [ "SSE" ],
1045 "comment" => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
1046 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
1048 "units" => [ "SSE" ],
1053 "op_flags" => "L|X|Y",
1054 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
1055 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
1056 "outs" => [ "false", "true" ],
1058 "units" => [ "SSE" ],
1064 "comment" => "represents a SSE constant",
1065 "reg_req" => { "out" => [ "xmm" ] },
1066 "emit" => '. mov%XXM $%C, %D1',
1068 "units" => [ "SSE" ],
1075 "op_flags" => "L|F",
1076 "state" => "exc_pinned",
1077 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
1078 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
1079 "emit" => '. mov%XXM %AM, %D1',
1080 "outs" => [ "res", "M" ],
1082 "units" => [ "SSE" ],
1086 "op_flags" => "L|F",
1087 "state" => "exc_pinned",
1088 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
1089 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
1090 "emit" => '. mov%XXM %binop',
1092 "units" => [ "SSE" ],
1097 "op_flags" => "L|F",
1098 "state" => "exc_pinned",
1099 "comment" => "construct Store without index: Store(ptr, val, mem) = ST ptr,val",
1100 "reg_req" => { "in" => [ "gp", "xmm", "none" ] },
1101 "emit" => '. mov%XXM %S2, %AM',
1103 "units" => [ "SSE" ],
1108 "op_flags" => "L|F",
1109 "comment" => "construct: transfer a value from x87 FPU into a SSE register",
1110 "cmp_attr" => "return 1;",
1115 "op_flags" => "L|F",
1116 "comment" => "construct: transfer a value from SSE register to x87 FPU",
1117 "cmp_attr" => "return 1;",
1122 "op_flags" => "L|F",
1124 "state" => "exc_pinned",
1125 "comment" => "store ST0 onto stack",
1126 "reg_req" => { "in" => [ "gp", "gp", "none" ] },
1127 "emit" => '. fstp%XM %AM',
1129 "units" => [ "SSE" ],
1134 "op_flags" => "L|F",
1136 "state" => "exc_pinned",
1137 "comment" => "load ST0 from stack",
1138 "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "vf0", "none" ] },
1139 "emit" => '. fld%M %AM',
1140 "outs" => [ "res", "M" ],
1142 "units" => [ "SSE" ],
1148 "op_flags" => "F|H",
1149 "state" => "pinned",
1150 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
1151 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "edi", "esi", "ecx", "none" ] },
1152 "outs" => [ "DST", "SRC", "CNT", "M" ],
1153 "units" => [ "GP" ],
1157 "op_flags" => "F|H",
1158 "state" => "pinned",
1159 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
1160 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "edi", "esi", "none" ] },
1161 "outs" => [ "DST", "SRC", "M" ],
1162 "units" => [ "GP" ],
1168 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
1169 "comment" => "construct Conv Int -> Int",
1170 "units" => [ "GP" ],
1171 "mode" => "mode_Iu",
1175 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
1176 "comment" => "construct Conv Int -> Int",
1177 "units" => [ "GP" ],
1178 "mode" => "mode_Iu",
1182 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
1183 "comment" => "construct Conv Int -> Floating Point",
1185 "units" => [ "SSE" ],
1190 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
1191 "comment" => "construct Conv Floating Point -> Int",
1193 "units" => [ "SSE" ],
1194 "mode" => "mode_Iu",
1198 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
1199 "comment" => "construct Conv Floating Point -> Floating Point",
1201 "units" => [ "SSE" ],
1207 "comment" => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
1208 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "in_r4" ] },
1210 "units" => [ "GP" ],
1211 "mode" => "mode_Iu",
1216 "comment" => "check if Psi condition tree evaluates to true and move result accordingly",
1217 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r3" ] },
1219 "units" => [ "GP" ],
1220 "mode" => "mode_Iu",
1225 "comment" => "construct Conditional Move: SSE Compare + int CMov ",
1226 "reg_req" => { "in" => [ "xmm", "xmm", "gp", "gp" ], "out" => [ "in_r4" ] },
1228 "units" => [ "SSE" ],
1229 "mode" => "mode_Iu",
1234 "comment" => "construct Conditional Move: x87 Compare + int CMov",
1235 "reg_req" => { "in" => [ "vfp", "vfp", "gp", "gp" ], "out" => [ "in_r4" ] },
1237 "units" => [ "VFP" ],
1238 "mode" => "mode_Iu",
1243 "comment" => "construct Set: Set(sel) == sel ? 1 : 0",
1244 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax ebx ecx edx" ] },
1246 "units" => [ "GP" ],
1247 "mode" => "mode_Iu",
1252 "comment" => "check if Psi condition tree evaluates to true and set result accordingly",
1253 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax ebx ecx edx" ] },
1255 "units" => [ "GP" ],
1256 "mode" => "mode_Iu",
1261 "comment" => "construct Set: SSE Compare + int Set",
1262 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "eax ebx ecx edx" ] },
1264 "units" => [ "SSE" ],
1265 "mode" => "mode_Iu",
1270 "comment" => "construct Set: x87 Compare + int Set",
1271 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "eax ebx ecx edx" ] },
1273 "units" => [ "VFP" ],
1274 "mode" => "mode_Iu",
1279 "comment" => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
1280 "reg_req" => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] },
1282 "units" => [ "VFP" ],
1286 #----------------------------------------------------------#
1288 # (_) | | | | / _| | | | #
1289 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
1290 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
1291 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
1292 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
1294 # _ __ ___ __| | ___ ___ #
1295 # | '_ \ / _ \ / _` |/ _ \/ __| #
1296 # | | | | (_) | (_| | __/\__ \ #
1297 # |_| |_|\___/ \__,_|\___||___/ #
1298 #----------------------------------------------------------#
1302 "comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
1303 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1305 "units" => [ "VFP" ],
1311 "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1312 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1314 "units" => [ "VFP" ],
1320 "cmp_attr" => "return 1;",
1321 "comment" => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1327 "comment" => "virtual fp Sub: Sub(a, b) = a - b",
1328 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1330 "units" => [ "VFP" ],
1335 "cmp_attr" => "return 1;",
1336 "comment" => "lowered virtual fp Sub: Sub(a, b) = a - b",
1341 "comment" => "virtual fp Div: Div(a, b) = a / b",
1342 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1343 "outs" => [ "res", "M" ],
1345 "units" => [ "VFP" ],
1349 "cmp_attr" => "return 1;",
1350 "comment" => "lowered virtual fp Div: Div(a, b) = a / b",
1351 "outs" => [ "res", "M" ],
1356 "comment" => "virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1357 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1359 "units" => [ "VFP" ],
1364 "cmp_attr" => "return 1;",
1365 "comment" => "lowered virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1371 "comment" => "virtual fp Abs: Abs(a) = |a|",
1372 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1374 "units" => [ "VFP" ],
1380 "comment" => "virtual fp Chs: Chs(a) = -a",
1381 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1383 "units" => [ "VFP" ],
1389 "comment" => "virtual fp Sin: Sin(a) = sin(a)",
1390 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1392 "units" => [ "VFP" ],
1398 "comment" => "virtual fp Cos: Cos(a) = cos(a)",
1399 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1401 "units" => [ "VFP" ],
1407 "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
1408 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1410 "units" => [ "VFP" ],
1414 # virtual Load and Store
1417 "op_flags" => "L|F",
1418 "state" => "exc_pinned",
1419 "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
1420 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1421 "outs" => [ "res", "M" ],
1423 "units" => [ "VFP" ],
1427 "op_flags" => "L|F",
1428 "state" => "exc_pinned",
1429 "comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
1430 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1432 "units" => [ "VFP" ],
1439 "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1440 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1441 "outs" => [ "res", "M" ],
1443 "units" => [ "VFP" ],
1447 "cmp_attr" => "return 1;",
1448 "comment" => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1449 "outs" => [ "res", "M" ],
1454 "comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1455 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1457 "units" => [ "VFP" ],
1462 "cmp_attr" => "return 1;",
1463 "comment" => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1473 "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg",
1474 "reg_req" => { "out" => [ "vfp" ] },
1476 "units" => [ "VFP" ],
1482 "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg",
1483 "reg_req" => { "out" => [ "vfp" ] },
1485 "units" => [ "VFP" ],
1491 "comment" => "virtual fp Load pi: Ld pi -> reg",
1492 "reg_req" => { "out" => [ "vfp" ] },
1494 "units" => [ "VFP" ],
1500 "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg",
1501 "reg_req" => { "out" => [ "vfp" ] },
1503 "units" => [ "VFP" ],
1509 "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg",
1510 "reg_req" => { "out" => [ "vfp" ] },
1512 "units" => [ "VFP" ],
1518 "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg",
1519 "reg_req" => { "out" => [ "vfp" ] },
1521 "units" => [ "VFP" ],
1527 "comment" => "virtual fp Load ld e: Ld ld e -> reg",
1528 "reg_req" => { "out" => [ "vfp" ] },
1530 "units" => [ "VFP" ],
1537 # "init_attr" => " set_ia32_ls_mode(res, mode);",
1538 "comment" => "represents a virtual floating point constant",
1539 "reg_req" => { "out" => [ "vfp" ] },
1541 "units" => [ "VFP" ],
1548 "op_flags" => "L|X|Y",
1549 "comment" => "represents a virtual floating point compare",
1550 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] },
1551 "outs" => [ "false", "true", "temp_reg_eax" ],
1553 "units" => [ "VFP" ],
1556 #------------------------------------------------------------------------#
1557 # ___ _____ __ _ _ _ #
1558 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1559 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1560 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1561 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1562 #------------------------------------------------------------------------#
1564 # Note: gas is strangely buggy: fdivrp and fdivp as well as fsubrp and fsubp
1565 # are swapped, we work this around in the emitter...
1569 "rd_constructor" => "NONE",
1570 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1572 "emit" => '. fadd%XM %x87_binop',
1577 "rd_constructor" => "NONE",
1578 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1580 "emit" => '. faddp %x87_binop',
1585 "rd_constructor" => "NONE",
1586 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1588 "emit" => '. fmul%XM %x87_binop',
1593 "rd_constructor" => "NONE",
1594 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1596 "emit" => '. fmulp %x87_binop',,
1601 "rd_constructor" => "NONE",
1602 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1604 "emit" => '. fsub%XM %x87_binop',
1609 "rd_constructor" => "NONE",
1610 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1612 # see note about gas bugs
1613 "emit" => '. fsubrp %x87_binop',
1618 "rd_constructor" => "NONE",
1620 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1622 "emit" => '. fsubr%XM %x87_binop',
1627 "rd_constructor" => "NONE",
1629 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1631 # see note about gas bugs
1632 "emit" => '. fsubp %x87_binop',
1637 "rd_constructor" => "NONE",
1638 "comment" => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1640 "emit" => '. fprem1',
1643 # this node is just here, to keep the simulator running
1644 # we can omit this when a fprem simulation function exists
1647 "rd_constructor" => "NONE",
1648 "comment" => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1650 "emit" => '. fprem1',
1655 "rd_constructor" => "NONE",
1656 "comment" => "x87 fp Div: Div(a, b) = a / b",
1658 "emit" => '. fdiv%XM %x87_binop',
1663 "rd_constructor" => "NONE",
1664 "comment" => "x87 fp Div: Div(a, b) = a / b",
1666 # see note about gas bugs
1667 "emit" => '. fdivrp %x87_binop',
1672 "rd_constructor" => "NONE",
1673 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1675 "emit" => '. fdivr%XM %x87_binop',
1680 "rd_constructor" => "NONE",
1681 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1683 # see note about gas bugs
1684 "emit" => '. fdivp %x87_binop',
1689 "rd_constructor" => "NONE",
1690 "comment" => "x87 fp Abs: Abs(a) = |a|",
1697 "rd_constructor" => "NONE",
1698 "comment" => "x87 fp Chs: Chs(a) = -a",
1705 "rd_constructor" => "NONE",
1706 "comment" => "x87 fp Sin: Sin(a) = sin(a)",
1713 "rd_constructor" => "NONE",
1714 "comment" => "x87 fp Cos: Cos(a) = cos(a)",
1721 "rd_constructor" => "NONE",
1722 "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1724 "emit" => '. fsqrt $',
1727 # x87 Load and Store
1730 "rd_constructor" => "NONE",
1731 "op_flags" => "R|L|F",
1732 "state" => "exc_pinned",
1733 "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1735 "emit" => '. fld%XM %AM',
1739 "rd_constructor" => "NONE",
1740 "op_flags" => "R|L|F",
1741 "state" => "exc_pinned",
1742 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1744 "emit" => '. fst%XM %AM',
1749 "rd_constructor" => "NONE",
1750 "op_flags" => "R|L|F",
1751 "state" => "exc_pinned",
1752 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1754 "emit" => '. fstp%XM %AM',
1762 "rd_constructor" => "NONE",
1763 "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1765 "emit" => '. fild%XM %AM',
1770 "rd_constructor" => "NONE",
1771 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1773 "emit" => '. fist%M %AM',
1779 "rd_constructor" => "NONE",
1780 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1782 "emit" => '. fistp%M %AM',
1789 "op_flags" => "R|c",
1791 "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
1797 "op_flags" => "R|c",
1799 "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
1805 "op_flags" => "R|c",
1807 "comment" => "x87 fp Load pi: Ld pi -> reg",
1809 "emit" => '. fldpi',
1813 "op_flags" => "R|c",
1815 "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
1817 "emit" => '. fldln2',
1821 "op_flags" => "R|c",
1823 "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
1825 "emit" => '. fldlg2',
1829 "op_flags" => "R|c",
1831 "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
1833 "emit" => '. fldll2t',
1837 "op_flags" => "R|c",
1839 "comment" => "x87 fp Load ld e: Ld ld e -> reg",
1841 "emit" => '. fldl2e',
1845 # Note that it is NEVER allowed to do CSE on these nodes
1846 # Moreover, note the virtual register requierements!
1849 "op_flags" => "R|K",
1850 "comment" => "x87 stack exchange",
1852 "cmp_attr" => "return 1;",
1853 "emit" => '. fxch %X1',
1857 "op_flags" => "R|K",
1858 "comment" => "x87 stack push",
1860 "cmp_attr" => "return 1;",
1861 "emit" => '. fld %X1',
1866 "comment" => "x87 stack push",
1867 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1868 "cmp_attr" => "return 1;",
1869 "emit" => '. fld %X1',
1873 "op_flags" => "R|K",
1874 "comment" => "x87 stack pop",
1876 "cmp_attr" => "return 1;",
1877 "emit" => '. fstp %X1',
1883 "op_flags" => "L|X|Y",
1884 "comment" => "floating point compare",
1889 "op_flags" => "L|X|Y",
1890 "comment" => "floating point compare and pop",
1895 "op_flags" => "L|X|Y",
1896 "comment" => "floating point compare and pop twice",
1901 "op_flags" => "L|X|Y",
1902 "comment" => "floating point compare reverse",
1907 "op_flags" => "L|X|Y",
1908 "comment" => "floating point compare reverse and pop",
1913 "op_flags" => "L|X|Y",
1914 "comment" => "floating point compare reverse and pop twice",
1919 # -------------------------------------------------------------------------------- #
1920 # ____ ____ _____ _ _ #
1921 # / ___/ ___|| ____| __ _____ ___| |_ ___ _ __ _ __ ___ __| | ___ ___ #
1922 # \___ \___ \| _| \ \ / / _ \/ __| __/ _ \| '__| | '_ \ / _ \ / _` |/ _ \/ __| #
1923 # ___) |__) | |___ \ V / __/ (__| || (_) | | | | | | (_) | (_| | __/\__ \ #
1924 # |____/____/|_____| \_/ \___|\___|\__\___/|_| |_| |_|\___/ \__,_|\___||___/ #
1926 # -------------------------------------------------------------------------------- #
1929 # Spilling and reloading of SSE registers, hardcoded, not generated #
1932 "op_flags" => "L|F",
1933 "state" => "exc_pinned",
1934 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
1935 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
1936 "emit" => '. movdqu %D1, %AM',
1937 "outs" => [ "res", "M" ],
1938 "units" => [ "SSE" ],
1942 "op_flags" => "L|F",
1943 "state" => "exc_pinned",
1944 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
1945 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
1946 "emit" => '. movdqu %binop',
1947 "units" => [ "SSE" ],
1953 # Include the generated SIMD node specification written by the SIMD optimization
1955 do "../ir/be/ia32/ia32_simd_spec.pl";