3 # This is the specification for the ia32 assembler Firm-operations
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
8 # this string marks the beginning of a comment in emit
9 $comment_string = "/*";
11 # the number of additional opcodes you want to register
12 #$additional_opcodes = 0;
14 # The node description is done as a perl hash initializer with the
15 # following structure:
20 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
21 # "irn_flags" => "R|N|I"
22 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
23 # "state" => "floats|pinned|mem_pinned|exc_pinned",
25 # { "type" => "type 1", "name" => "name 1" },
26 # { "type" => "type 2", "name" => "name 2" },
29 # "comment" => "any comment for constructor",
30 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
31 # "cmp_attr" => "c source code for comparing node attributes",
32 # "emit" => "emit code with templates",
33 # "attr" => "attitional attribute arguments for constructor"
34 # "init_attr" => "emit attribute initialization template"
35 # "rd_constructor" => "c source code which constructs an ir_node"
38 # ... # (all nodes you need to describe)
40 # ); # close the %nodes initializer
42 # op_flags: flags for the operation, OPTIONAL (default is "N")
43 # the op_flags correspond to the firm irop_flags:
46 # C irop_flag_commutative
47 # X irop_flag_cfopcode
48 # I irop_flag_ip_cfopcode
51 # H irop_flag_highlevel
52 # c irop_flag_constlike
55 # irn_flags: special node flags, OPTIONAL (default is 0)
56 # following irn_flags are supported:
59 # I ignore for register allocation
61 # state: state of the operation, OPTIONAL (default is "floats")
63 # arity: arity of the operation, MUST NOT BE OMITTED
65 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
66 # are always the first 3 arguments and are always autmatically
68 # If this key is missing the following arguments will be created:
69 # for i = 1 .. arity: ir_node *op_i
72 # outs: if a node defines more than one output, the names of the projections
73 # nodes having outs having automatically the mode mode_T
75 # comment: OPTIONAL comment for the node constructor
77 # rd_constructor: for every operation there will be a
78 # new_rd_<arch>_<op-name> function with the arguments from above
79 # which creates the ir_node corresponding to the defined operation
80 # you can either put the complete source code of this function here
82 # This key is OPTIONAL. If omitted, the following constructor will
84 # if (!op_<arch>_<op-name>) assert(0);
88 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
91 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
95 # 1 - caller save (register must be saved by the caller of a function)
96 # 2 - callee save (register must be saved by the called function)
97 # 4 - ignore (do not assign this register)
98 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
101 { "name" => "eax", "type" => 1 },
102 { "name" => "edx", "type" => 1 },
103 { "name" => "ebx", "type" => 2 },
104 { "name" => "ecx", "type" => 1 },
105 { "name" => "esi", "type" => 2 },
106 { "name" => "edi", "type" => 2 },
107 # { "name" => "r11", "type" => 1 },
108 # { "name" => "r12", "type" => 1 },
109 # { "name" => "r13", "type" => 1 },
110 # { "name" => "r14", "type" => 1 },
111 # { "name" => "r15", "type" => 1 },
112 # { "name" => "r16", "type" => 1 },
113 # { "name" => "r17", "type" => 1 },
114 # { "name" => "r18", "type" => 1 },
115 # { "name" => "r19", "type" => 1 },
116 # { "name" => "r20", "type" => 1 },
117 # { "name" => "r21", "type" => 1 },
118 # { "name" => "r22", "type" => 1 },
119 # { "name" => "r23", "type" => 1 },
120 # { "name" => "r24", "type" => 1 },
121 # { "name" => "r25", "type" => 1 },
122 # { "name" => "r26", "type" => 1 },
123 # { "name" => "r27", "type" => 1 },
124 # { "name" => "r28", "type" => 1 },
125 # { "name" => "r29", "type" => 1 },
126 # { "name" => "r30", "type" => 1 },
127 # { "name" => "r31", "type" => 1 },
128 # { "name" => "r32", "type" => 1 },
129 { "name" => "ebp", "type" => 2 },
130 { "name" => "esp", "type" => 4 },
131 { "name" => "gp_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
132 { "name" => "gp_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
133 { "mode" => "mode_P" }
136 { "name" => "xmm0", "type" => 1 },
137 { "name" => "xmm1", "type" => 1 },
138 { "name" => "xmm2", "type" => 1 },
139 { "name" => "xmm3", "type" => 1 },
140 { "name" => "xmm4", "type" => 1 },
141 { "name" => "xmm5", "type" => 1 },
142 { "name" => "xmm6", "type" => 1 },
143 { "name" => "xmm7", "type" => 1 },
144 { "name" => "xmm_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
145 { "name" => "xmm_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
146 { "mode" => "mode_D" }
149 { "name" => "vf0", "type" => 1 },
150 { "name" => "vf1", "type" => 1 },
151 { "name" => "vf2", "type" => 1 },
152 { "name" => "vf3", "type" => 1 },
153 { "name" => "vf4", "type" => 1 },
154 { "name" => "vf5", "type" => 1 },
155 { "name" => "vf6", "type" => 1 },
156 { "name" => "vf7", "type" => 1 },
157 { "name" => "vfp_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
158 { "name" => "vfp_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
159 { "mode" => "mode_E" }
162 { "name" => "st0", "type" => 1 },
163 { "name" => "st1", "type" => 1 },
164 { "name" => "st2", "type" => 1 },
165 { "name" => "st3", "type" => 1 },
166 { "name" => "st4", "type" => 1 },
167 { "name" => "st5", "type" => 1 },
168 { "name" => "st6", "type" => 1 },
169 { "name" => "st7", "type" => 1 },
170 { "mode" => "mode_E" }
174 #--------------------------------------------------#
177 # _ __ _____ __ _ _ __ ___ _ __ ___ #
178 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
179 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
180 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
183 #--------------------------------------------------#
190 #-----------------------------------------------------------------#
193 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
194 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
195 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
196 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
199 #-----------------------------------------------------------------#
201 # commutative operations
204 # All nodes supporting Addressmode have 5 INs:
205 # 1 - base r1 == NoReg in case of no AM or no base
206 # 2 - index r2 == NoReg in case of no AM or no index
207 # 3 - op1 r3 == always present
208 # 4 - op2 r4 == NoReg in case of immediate operation
209 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
213 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
214 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
215 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
216 "emit" => '. add %ia32_emit_binop /* Add(%A3, %A4) -> %D1 */',
217 "outs" => [ "res", "M" ],
221 "comment" => "construct Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
222 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
223 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
224 "emit" => '. adc %ia32_emit_binop /* AddC(%A3, %A4) -> %D1 */',
225 "outs" => [ "res", "M" ],
231 "comment" => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
237 "comment" => "construct lowered Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
242 "comment" => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
243 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
244 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r3", "edx in_r4" ] },
245 "emit" => '. mul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */',
246 "outs" => [ "EAX", "EDX", "M" ],
251 "comment" => "construct lowered MulS: MulS(a, b) = MulS(b, a) = a * b",
252 "outs" => [ "EAX", "EDX", "M" ],
258 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
259 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
260 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
261 "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */',
262 "outs" => [ "res", "M" ],
267 "comment" => "construct lowered Mul: Mul(a, b) = Mul(b, a) = a * b",
271 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
273 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
274 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
275 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r3", "edx in_r4" ] },
276 "emit" => '. imul %ia32_emit_binop /* Mulh(%A1, %A2) -> %D1 */',
277 "outs" => [ "EAX", "EDX", "M" ],
282 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
283 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
284 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
285 "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */',
286 "outs" => [ "res", "M" ],
291 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
292 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
293 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
294 "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */',
295 "outs" => [ "res", "M" ],
300 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
301 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
302 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
303 "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */',
304 "outs" => [ "res", "M" ],
309 "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
310 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
312 '2. cmp %S1, %S2 /* prepare Max (%S1 - %S2), (%A1, %A2) */
313 if (mode_is_signed(get_irn_mode(n))) {
314 4. cmovl %D1, %S2 /* %S1 is less %S2 */
317 4. cmovb %D1, %S2 /* %S1 is below %S2 */
324 "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
325 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
327 '2. cmp %S1, %S2 /* prepare Min (%S1 - %S2), (%A1, %A2) */
328 if (mode_is_signed(get_irn_mode(n))) {
329 2. cmovg %D1, %S2 /* %S1 is greater %S2 */
332 2. cmova %D1, %S2, %D1 /* %S1 is above %S2 */
337 # not commutative operations
341 "comment" => "construct Sub: Sub(a, b) = a - b",
342 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
343 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
344 "emit" => '. sub %ia32_emit_binop /* Sub(%A3, %A4) -> %D1 */',
345 "outs" => [ "res", "M" ],
349 "comment" => "construct Sub with Carry: SubC(a, b) = a - b - carry",
350 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
351 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
352 "emit" => '. sbb %ia32_emit_binop /* SubC(%A3, %A4) -> %D1 */',
353 "outs" => [ "res", "M" ],
358 "comment" => "construct lowered Sub: Sub(a, b) = a - b",
363 "comment" => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
369 "state" => "exc_pinned",
370 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "eax in_r1", "edx in_r3" ] },
371 "attr" => "ia32_op_flavour_t dm_flav",
372 "init_attr" => " attr->data.op_flav = dm_flav;",
373 "cmp_attr" => " return attr_a->data.op_flav != attr_b->data.op_flav;\n",
375 ' if (mode_is_signed(get_irn_mode(n))) {
376 4. idiv %S2 /* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
379 4. div %S2 /* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
382 "outs" => [ "div_res", "mod_res", "M" ],
387 "comment" => "construct Shl: Shl(a, b) = a << b",
388 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
389 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
390 "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */',
391 "outs" => [ "res", "M" ],
395 "comment" => "construct lowered Shl: Shl(a, b) = a << b",
401 "comment" => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
402 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
403 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r5" ] },
406 if (get_ia32_immop_type(n) == ia32_ImmNone) {
407 if (get_ia32_op_type(n) == ia32_AddrModeD) {
408 4. shld %ia32_emit_am, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
411 4. shld %S3, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
415 if (get_ia32_op_type(n) == ia32_AddrModeD) {
416 4. shld %ia32_emit_am, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
419 4. shld %S3, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
423 "outs" => [ "res", "M" ],
427 "comment" => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
433 "comment" => "construct Shr: Shr(a, b) = a >> b",
434 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
435 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
436 "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */',
437 "outs" => [ "res", "M" ],
441 "comment" => "construct lowered Shr: Shr(a, b) = a << b",
447 "comment" => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
448 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
449 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r5" ] },
452 if (get_ia32_immop_type(n) == ia32_ImmNone) {
453 if (get_ia32_op_type(n) == ia32_AddrModeD) {
454 4. shrd %ia32_emit_am, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
457 4. shrd %S3, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
461 if (get_ia32_op_type(n) == ia32_AddrModeD) {
462 4. shrd %ia32_emit_am, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
465 4. shrd %S3, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
469 "outs" => [ "res", "M" ],
473 "comment" => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
479 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
480 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
481 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
482 "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */',
483 "outs" => [ "res", "M" ],
487 "comment" => "construct lowered Shrs: Shrs(a, b) = a << b",
493 "comment" => "construct RotR: RotR(a, b) = a ROTR b",
494 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
495 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
496 "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */',
497 "outs" => [ "res", "M" ],
502 "comment" => "construct RotL: RotL(a, b) = a ROTL b",
503 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
504 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
505 "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */',
506 "outs" => [ "res", "M" ],
513 "comment" => "construct Minus: Minus(a) = -a",
514 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
515 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
516 "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */',
517 "outs" => [ "res", "M" ],
521 "comment" => "construct lowered Minus: Minus(a) = -a",
527 "comment" => "construct Increment: Inc(a) = a++",
528 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
529 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
530 "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */',
531 "outs" => [ "res", "M" ],
536 "comment" => "construct Decrement: Dec(a) = a--",
537 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
538 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
539 "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */',
540 "outs" => [ "res", "M" ],
545 "comment" => "construct Not: Not(a) = !a",
546 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
547 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
548 "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */',
549 "outs" => [ "res", "M" ],
555 "op_flags" => "L|X|Y",
556 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
557 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
558 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
559 "outs" => [ "false", "true" ],
563 "op_flags" => "L|X|Y",
564 "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
565 "reg_req" => { "in" => [ "gp", "gp" ] },
566 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
567 "outs" => [ "false", "true" ],
571 "op_flags" => "L|X|Y",
572 "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
573 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
574 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
575 "outs" => [ "false", "true" ],
579 "op_flags" => "L|X|Y",
580 "comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
581 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
582 "reg_req" => { "in" => [ "gp", "gp" ] },
586 "op_flags" => "L|X|Y",
587 "comment" => "construct switch",
588 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
589 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
595 "comment" => "represents an integer constant",
596 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
597 "reg_req" => { "in" => [ "none" ], "out" => [ "gp" ] },
602 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
603 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
604 "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */',
605 "outs" => [ "EAX", "EDX" ],
613 "state" => "exc_pinned",
614 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
615 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
616 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
618 ' if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) {
619 4. mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
622 4. mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
625 "outs" => [ "res", "M" ],
630 "state" => "exc_pinned",
631 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
632 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
633 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
634 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
640 "state" => "exc_pinned",
641 "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
642 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
643 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
644 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
650 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
651 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
652 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
653 "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */'
657 "comment" => "push a gp register on the stack",
658 "reg_req" => { "in" => [ "esp", "gp", "none" ], "out" => [ "esp" ] },
660 if (get_ia32_id_cnst(n)) {
661 if (get_ia32_immop_type(n) == ia32_ImmConst) {
662 . push %C /* Push(%A2) */
664 . push OFFSET FLAT:%C /* Push(%A2) */
668 . push %S2 /* Push(%A2) */
671 "outs" => [ "stack", "M" ],
675 "comment" => "pop a gp register from the stack",
676 "reg_req" => { "in" => [ "esp", "none" ], "out" => [ "gp", "esp" ] },
677 "emit" => '. pop %D1 /* Pop -> %D1 */',
678 "outs" => [ "res", "stack", "M" ],
682 "comment" => "create stack frame",
683 "reg_req" => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] },
684 "emit" => '. enter /* Enter */',
685 "outs" => [ "frame", "stack", "M" ],
689 "comment" => "destroy stack frame",
690 "reg_req" => { "in" => [ "esp", "ebp" ], "out" => [ "ebp", "esp" ] },
691 "emit" => '. leave /* Leave */',
692 "outs" => [ "frame", "stack", "M" ],
695 #-----------------------------------------------------------------------------#
696 # _____ _____ ______ __ _ _ _ #
697 # / ____/ ____| ____| / _| | | | | | #
698 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
699 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
700 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
701 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
702 #-----------------------------------------------------------------------------#
704 # commutative operations
708 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
709 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
710 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
711 "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */',
712 "outs" => [ "res", "M" ],
717 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
718 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
719 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
720 "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */',
721 "outs" => [ "res", "M" ],
726 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
727 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
728 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
729 "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */',
730 "outs" => [ "res", "M" ],
735 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
736 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
737 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
738 "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */',
739 "outs" => [ "res", "M" ],
744 "comment" => "construct SSE And: And(a, b) = a AND b",
745 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
746 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
747 "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */',
748 "outs" => [ "res", "M" ],
753 "comment" => "construct SSE Or: Or(a, b) = a OR b",
754 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
755 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
756 "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */',
757 "outs" => [ "res", "M" ],
762 "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
763 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
764 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
765 "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */',
766 "outs" => [ "res", "M" ],
769 # not commutative operations
773 "comment" => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
774 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
775 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
776 "emit" => '. andnp%M %ia32_emit_binop /* SSE AndNot(%A3, %A4) -> %D1 */',
777 "outs" => [ "res", "M" ],
782 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
783 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
784 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
785 "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */',
786 "outs" => [ "res", "M" ],
791 "comment" => "construct SSE Div: Div(a, b) = a / b",
792 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
793 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
794 "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */',
795 "outs" => [ "res", "M" ],
802 "comment" => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
803 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
804 "outs" => [ "res", "M" ],
808 "op_flags" => "L|X|Y",
809 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
810 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
811 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
812 "outs" => [ "false", "true" ],
818 "comment" => "represents a SSE constant",
819 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
820 "reg_req" => { "in" => [ "none" ], "out" => [ "xmm" ] },
821 "emit" => '. movs%M %D1, %C /* Load fConst into register */',
829 "state" => "exc_pinned",
830 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
831 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
832 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm" ] },
833 "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */',
834 "outs" => [ "res", "M" ],
839 "state" => "exc_pinned",
840 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
841 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
842 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
843 "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */',
852 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
853 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "none" ] },
859 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
860 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
861 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "none" ] },
867 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
868 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
869 "comment" => "construct Conv Int -> Int",
870 "outs" => [ "res", "M" ],
874 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
875 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
876 "comment" => "construct Conv Int -> Int",
877 "outs" => [ "res", "M" ],
881 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
882 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
883 "comment" => "construct Conv Int -> Floating Point",
884 "outs" => [ "res", "M" ],
888 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
889 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
890 "comment" => "construct Conv Floating Point -> Int",
891 "outs" => [ "res", "M" ],
895 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
896 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
897 "comment" => "construct Conv Floating Point -> Floating Point",
898 "outs" => [ "res", "M" ],
903 "comment" => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
904 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "in_r4" ] }
909 "comment" => "check if Psi condition tree evaluates to true and move result accordingly",
910 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r3" ] }
915 "comment" => "construct Conditional Move: SSE Compare + int CMov ",
916 "reg_req" => { "in" => [ "xmm", "xmm", "gp", "gp" ], "out" => [ "in_r4" ] }
921 "comment" => "construct Conditional Move: x87 Compare + int CMov",
922 "reg_req" => { "in" => [ "vfp", "vfp", "gp", "gp" ], "out" => [ "in_r4" ] }
927 "comment" => "construct Set: Set(sel) == sel ? 1 : 0",
928 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
929 "outs" => [ "res", "M" ],
934 "comment" => "check if Psi condition tree evaluates to true and set result accordingly",
935 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax ebx ecx edx" ] },
940 "comment" => "construct Set: SSE Compare + int Set",
941 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
942 "outs" => [ "res", "M" ],
947 "comment" => "construct Set: x87 Compare + int Set",
948 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
949 "outs" => [ "res", "M" ],
954 "comment" => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
955 "reg_req" => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] }
958 #----------------------------------------------------------#
960 # (_) | | | | / _| | | | #
961 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
962 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
963 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
964 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
966 # _ __ ___ __| | ___ ___ #
967 # | '_ \ / _ \ / _` |/ _ \/ __| #
968 # | | | | (_) | (_| | __/\__ \ #
969 # |_| |_|\___/ \__,_|\___||___/ #
970 #----------------------------------------------------------#
974 "comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
975 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
976 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
977 "outs" => [ "res", "M" ],
982 "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a + b",
983 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
984 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
985 "outs" => [ "res", "M" ],
990 "comment" => "virtual fp Sub: Sub(a, b) = a - b",
991 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
992 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
993 "outs" => [ "res", "M" ],
997 "comment" => "virtual fp Div: Div(a, b) = a / b",
998 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
999 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1000 "outs" => [ "res", "M" ],
1005 "comment" => "virtual fp Abs: Abs(a) = |a|",
1006 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1011 "comment" => "virtual fp Chs: Chs(a) = -a",
1012 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1017 "comment" => "virtual fp Sin: Sin(a) = sin(a)",
1018 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1023 "comment" => "virtual fp Cos: Cos(a) = cos(a)",
1024 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1029 "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
1030 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1033 # virtual Load and Store
1036 "op_flags" => "L|F",
1038 "state" => "exc_pinned",
1039 "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
1040 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1041 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1042 "outs" => [ "res", "M" ],
1046 "op_flags" => "L|F",
1047 "state" => "exc_pinned",
1048 "comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
1049 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1050 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1058 "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1059 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1060 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1061 "outs" => [ "res", "M" ],
1065 "comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1066 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1067 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1075 "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg",
1076 "reg_req" => { "out" => [ "vfp" ] },
1081 "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg",
1082 "reg_req" => { "out" => [ "vfp" ] },
1087 "comment" => "virtual fp Load pi: Ld pi -> reg",
1088 "reg_req" => { "out" => [ "vfp" ] },
1093 "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg",
1094 "reg_req" => { "out" => [ "vfp" ] },
1099 "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg",
1100 "reg_req" => { "out" => [ "vfp" ] },
1105 "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg",
1106 "reg_req" => { "out" => [ "vfp" ] },
1111 "comment" => "virtual fp Load ld e: Ld ld e -> reg",
1112 "reg_req" => { "out" => [ "vfp" ] },
1118 "init_attr" => " set_ia32_ls_mode(res, mode);",
1119 "comment" => "represents a virtual floating point constant",
1120 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1121 "reg_req" => { "in" => [ "none" ], "out" => [ "vfp" ] },
1127 "op_flags" => "L|X|Y",
1128 "comment" => "represents a virtual floating point compare",
1129 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1130 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] },
1131 "outs" => [ "false", "true", "temp_reg_eax" ],
1134 #------------------------------------------------------------------------#
1135 # ___ _____ __ _ _ _ #
1136 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1137 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1138 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1139 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1140 #------------------------------------------------------------------------#
1144 "rd_constructor" => "NONE",
1145 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1147 "emit" => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */',
1152 "rd_constructor" => "NONE",
1153 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1155 "emit" => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */',
1160 "rd_constructor" => "NONE",
1161 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1163 "emit" => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */',
1168 "rd_constructor" => "NONE",
1169 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1171 "emit" => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */',,
1176 "rd_constructor" => "NONE",
1177 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1179 "emit" => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */',
1184 "rd_constructor" => "NONE",
1185 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1187 "emit" => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */',
1192 "rd_constructor" => "NONE",
1194 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1196 "emit" => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */',
1201 "rd_constructor" => "NONE",
1203 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1205 "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */',
1210 "rd_constructor" => "NONE",
1211 "comment" => "x87 fp Div: Div(a, b) = a / b",
1213 "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */',
1218 "rd_constructor" => "NONE",
1219 "comment" => "x87 fp Div: Div(a, b) = a / b",
1221 "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */',
1226 "rd_constructor" => "NONE",
1227 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1229 "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */',
1234 "rd_constructor" => "NONE",
1235 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1237 "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */',
1242 "rd_constructor" => "NONE",
1243 "comment" => "x87 fp Abs: Abs(a) = |a|",
1245 "emit" => '. fabs /* x87 fabs(%S1) -> %D1 */',
1250 "rd_constructor" => "NONE",
1251 "comment" => "x87 fp Chs: Chs(a) = -a",
1253 "emit" => '. fchs /* x87 fchs(%S1) -> %D1 */',
1258 "rd_constructor" => "NONE",
1259 "comment" => "x87 fp Sin: Sin(a) = sin(a)",
1261 "emit" => '. fsin /* x87 sin(%S1) -> %D1 */',
1266 "rd_constructor" => "NONE",
1267 "comment" => "x87 fp Cos: Cos(a) = cos(a)",
1269 "emit" => '. fcos /* x87 cos(%S1) -> %D1 */',
1274 "rd_constructor" => "NONE",
1275 "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1277 "emit" => '. fsqrt $ /* x87 sqrt(%S1) -> %D1 */',
1280 # x87 Load and Store
1283 "rd_constructor" => "NONE",
1284 "op_flags" => "R|L|F",
1285 "state" => "exc_pinned",
1286 "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1288 "emit" => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */',
1292 "rd_constructor" => "NONE",
1293 "op_flags" => "R|L|F",
1294 "state" => "exc_pinned",
1295 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1297 "emit" => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */',
1301 "rd_constructor" => "NONE",
1302 "op_flags" => "R|L|F",
1303 "state" => "exc_pinned",
1304 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1306 "emit" => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */',
1314 "rd_constructor" => "NONE",
1315 "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1317 "emit" => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */',
1322 "rd_constructor" => "NONE",
1323 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1325 "emit" => '. fist %ia32_emit_am /* integer Store(%A3) -> (%A1) */',
1330 "rd_constructor" => "NONE",
1331 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1333 "emit" => '. fistp %ia32_emit_am /* integer Store(%A3) -> (%A1) and pop */',
1340 "rd_constructor" => "NONE",
1341 "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
1343 "emit" => '. fldz /* x87 0.0 -> %D1 */',
1348 "rd_constructor" => "NONE",
1349 "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
1351 "emit" => '. fld1 /* x87 1.0 -> %D1 */',
1356 "rd_constructor" => "NONE",
1357 "comment" => "x87 fp Load pi: Ld pi -> reg",
1359 "emit" => '. fldpi /* x87 pi -> %D1 */',
1364 "rd_constructor" => "NONE",
1365 "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
1367 "emit" => '. fldln2 /* x87 ln(2) -> %D1 */',
1372 "rd_constructor" => "NONE",
1373 "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
1375 "emit" => '. fldlg2 /* x87 log(2) -> %D1 */',
1380 "rd_constructor" => "NONE",
1381 "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
1383 "emit" => '. fldll2t /* x87 ld(10) -> %D1 */',
1388 "rd_constructor" => "NONE",
1389 "comment" => "x87 fp Load ld e: Ld ld e -> reg",
1391 "emit" => '. fldl2e /* x87 ld(e) -> %D1 */',
1395 "op_flags" => "R|c",
1397 "rd_constructor" => "NONE",
1398 "comment" => "represents a x87 constant",
1399 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1400 "reg_req" => { "out" => [ "st" ] },
1401 "emit" => '. fld %ia32_emit_adr /* Load fConst into register -> %D1 */',
1405 # Note that it is NEVER allowed to do CSE on these nodes
1408 "op_flags" => "R|K",
1409 "comment" => "x87 stack exchange",
1410 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1411 "cmp_attr" => " return 1;\n",
1412 "emit" => '. fxch %X1 /* x87 swap %X1, %X3 */',
1417 "comment" => "x87 stack push",
1418 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1419 "cmp_attr" => " return 1;\n",
1420 "emit" => '. fld %X1 /* x87 push %X1 */',
1424 "op_flags" => "R|K",
1425 "comment" => "x87 stack pop",
1426 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1427 "cmp_attr" => " return 1;\n",
1428 "emit" => '. fstp %X1 /* x87 pop %X1 */',
1434 "op_flags" => "L|X|Y",
1435 "comment" => "floating point compare",
1436 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1441 "op_flags" => "L|X|Y",
1442 "comment" => "floating point compare and pop",
1443 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1448 "op_flags" => "L|X|Y",
1449 "comment" => "floating point compare and pop twice",
1450 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1455 "op_flags" => "L|X|Y",
1456 "comment" => "floating point compare reverse",
1457 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1462 "op_flags" => "L|X|Y",
1463 "comment" => "floating point compare reverse and pop",
1464 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1469 "op_flags" => "L|X|Y",
1470 "comment" => "floating point compare reverse and pop twice",
1471 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",