3 # This is the specification for the ia32 assembler Firm-operations
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
8 # this string marks the beginning of a comment in emit
9 $comment_string = "/*";
11 # the number of additional opcodes you want to register
12 #$additional_opcodes = 0;
14 # The node description is done as a perl hash initializer with the
15 # following structure:
20 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
21 # "irn_flags" => "R|N|I"
22 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
23 # "state" => "floats|pinned|mem_pinned|exc_pinned",
25 # { "type" => "type 1", "name" => "name 1" },
26 # { "type" => "type 2", "name" => "name 2" },
29 # "comment" => "any comment for constructor",
30 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
31 # "cmp_attr" => "c source code for comparing node attributes",
32 # "emit" => "emit code with templates",
33 # "attr" => "attitional attribute arguments for constructor"
34 # "init_attr" => "emit attribute initialization template"
35 # "rd_constructor" => "c source code which constructs an ir_node"
38 # ... # (all nodes you need to describe)
40 # ); # close the %nodes initializer
42 # op_flags: flags for the operation, OPTIONAL (default is "N")
43 # the op_flags correspond to the firm irop_flags:
46 # C irop_flag_commutative
47 # X irop_flag_cfopcode
48 # I irop_flag_ip_cfopcode
51 # H irop_flag_highlevel
52 # c irop_flag_constlike
55 # irn_flags: special node flags, OPTIONAL (default is 0)
56 # following irn_flags are supported:
59 # I ignore for register allocation
61 # state: state of the operation, OPTIONAL (default is "floats")
63 # arity: arity of the operation, MUST NOT BE OMITTED
65 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
66 # are always the first 3 arguments and are always autmatically
68 # If this key is missing the following arguments will be created:
69 # for i = 1 .. arity: ir_node *op_i
72 # outs: if a node defines more than one output, the names of the projections
73 # nodes having outs having automatically the mode mode_T
75 # comment: OPTIONAL comment for the node constructor
77 # rd_constructor: for every operation there will be a
78 # new_rd_<arch>_<op-name> function with the arguments from above
79 # which creates the ir_node corresponding to the defined operation
80 # you can either put the complete source code of this function here
82 # This key is OPTIONAL. If omitted, the following constructor will
84 # if (!op_<arch>_<op-name>) assert(0);
88 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
91 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
95 # 1 - caller save (register must be saved by the caller of a function)
96 # 2 - callee save (register must be saved by the called function)
97 # 4 - ignore (do not assign this register)
98 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
101 { "name" => "eax", "type" => 1 },
102 { "name" => "edx", "type" => 1 },
103 { "name" => "ebx", "type" => 2 },
104 { "name" => "ecx", "type" => 1 },
105 { "name" => "esi", "type" => 2 },
106 { "name" => "edi", "type" => 2 },
107 # { "name" => "r11", "type" => 1 },
108 # { "name" => "r12", "type" => 1 },
109 # { "name" => "r13", "type" => 1 },
110 # { "name" => "r14", "type" => 1 },
111 # { "name" => "r15", "type" => 1 },
112 # { "name" => "r16", "type" => 1 },
113 # { "name" => "r17", "type" => 1 },
114 # { "name" => "r18", "type" => 1 },
115 # { "name" => "r19", "type" => 1 },
116 # { "name" => "r20", "type" => 1 },
117 # { "name" => "r21", "type" => 1 },
118 # { "name" => "r22", "type" => 1 },
119 # { "name" => "r23", "type" => 1 },
120 # { "name" => "r24", "type" => 1 },
121 # { "name" => "r25", "type" => 1 },
122 # { "name" => "r26", "type" => 1 },
123 # { "name" => "r27", "type" => 1 },
124 # { "name" => "r28", "type" => 1 },
125 # { "name" => "r29", "type" => 1 },
126 # { "name" => "r30", "type" => 1 },
127 # { "name" => "r31", "type" => 1 },
128 # { "name" => "r32", "type" => 1 },
129 { "name" => "ebp", "type" => 2 },
130 { "name" => "esp", "type" => 4 },
131 { "name" => "gp_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
132 { "name" => "gp_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
133 { "mode" => "mode_P" }
136 { "name" => "xmm0", "type" => 1 },
137 { "name" => "xmm1", "type" => 1 },
138 { "name" => "xmm2", "type" => 1 },
139 { "name" => "xmm3", "type" => 1 },
140 { "name" => "xmm4", "type" => 1 },
141 { "name" => "xmm5", "type" => 1 },
142 { "name" => "xmm6", "type" => 1 },
143 { "name" => "xmm7", "type" => 1 },
144 { "name" => "xmm_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
145 { "name" => "xmm_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
146 { "mode" => "mode_D" }
149 { "name" => "vf0", "type" => 1 },
150 { "name" => "vf1", "type" => 1 },
151 { "name" => "vf2", "type" => 1 },
152 { "name" => "vf3", "type" => 1 },
153 { "name" => "vf4", "type" => 1 },
154 { "name" => "vf5", "type" => 1 },
155 { "name" => "vf6", "type" => 1 },
156 { "name" => "vf7", "type" => 1 },
157 { "name" => "vfp_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
158 { "name" => "vfp_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
159 { "mode" => "mode_E" }
162 { "name" => "st0", "type" => 1 },
163 { "name" => "st1", "type" => 1 },
164 { "name" => "st2", "type" => 1 },
165 { "name" => "st3", "type" => 1 },
166 { "name" => "st4", "type" => 1 },
167 { "name" => "st5", "type" => 1 },
168 { "name" => "st6", "type" => 1 },
169 { "name" => "st7", "type" => 1 },
170 { "mode" => "mode_E" }
174 #--------------------------------------------------#
177 # _ __ _____ __ _ _ __ ___ _ __ ___ #
178 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
179 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
180 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
183 #--------------------------------------------------#
190 #-----------------------------------------------------------------#
193 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
194 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
195 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
196 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
199 #-----------------------------------------------------------------#
201 # commutative operations
204 # All nodes supporting Addressmode have 5 INs:
205 # 1 - base r1 == NoReg in case of no AM or no base
206 # 2 - index r2 == NoReg in case of no AM or no index
207 # 3 - op1 r3 == always present
208 # 4 - op2 r4 == NoReg in case of immediate operation
209 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
213 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
214 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
215 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
216 "emit" => '. add %ia32_emit_binop /* Add(%A3, %A4) -> %D1 */',
217 "outs" => [ "res", "M" ],
221 "comment" => "construct Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
222 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
223 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
224 "emit" => '. adc %ia32_emit_binop /* AddC(%A3, %A4) -> %D1 */',
225 "outs" => [ "res", "M" ],
231 "cmp_attr" => " return 1;\n",
232 "comment" => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
238 "cmp_attr" => " return 1;\n",
239 "comment" => "construct lowered Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
244 "comment" => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
245 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
246 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r3", "edx" ] },
247 "emit" => '. mul %ia32_emit_unop /* Mul(%A1, %A2) -> %D1 */',
248 "outs" => [ "EAX", "EDX", "M" ],
253 "cmp_attr" => " return 1;\n",
254 "comment" => "construct lowered MulS: MulS(a, b) = MulS(b, a) = a * b",
255 "outs" => [ "EAX", "EDX", "M" ],
261 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
262 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
263 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
264 "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */',
265 "outs" => [ "res", "M" ],
270 "cmp_attr" => " return 1;\n",
271 "comment" => "construct lowered Mul: Mul(a, b) = Mul(b, a) = a * b",
275 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
277 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
278 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
279 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r3", "edx" ] },
280 "emit" => '. imul %ia32_emit_unop /* Mulh(%A1, %A2) -> %D1 */',
281 "outs" => [ "EAX", "EDX", "M" ],
286 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
287 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
288 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
289 "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */',
290 "outs" => [ "res", "M" ],
295 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
296 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
297 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
298 "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */',
299 "outs" => [ "res", "M" ],
304 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
305 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
306 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
307 "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */',
308 "outs" => [ "res", "M" ],
313 "cmp_attr" => " return 1;\n",
314 "comment" => "construct lowered Eor: Eor(a, b) = Eor(b, a) = a EOR b",
320 "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
321 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
323 '2. cmp %S1, %S2 /* prepare Max (%S1 - %S2), (%A1, %A2) */
324 if (mode_is_signed(get_irn_mode(n))) {
325 4. cmovl %D1, %S2 /* %S1 is less %S2 */
328 4. cmovb %D1, %S2 /* %S1 is below %S2 */
335 "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
336 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
338 '2. cmp %S1, %S2 /* prepare Min (%S1 - %S2), (%A1, %A2) */
339 if (mode_is_signed(get_irn_mode(n))) {
340 2. cmovg %D1, %S2 /* %S1 is greater %S2 */
343 2. cmova %D1, %S2, %D1 /* %S1 is above %S2 */
348 # not commutative operations
352 "comment" => "construct Sub: Sub(a, b) = a - b",
353 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
354 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
355 "emit" => '. sub %ia32_emit_binop /* Sub(%A3, %A4) -> %D1 */',
356 "outs" => [ "res", "M" ],
360 "comment" => "construct Sub with Carry: SubC(a, b) = a - b - carry",
361 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
362 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
363 "emit" => '. sbb %ia32_emit_binop /* SubC(%A3, %A4) -> %D1 */',
364 "outs" => [ "res", "M" ],
369 "cmp_attr" => " return 1;\n",
370 "comment" => "construct lowered Sub: Sub(a, b) = a - b",
375 "cmp_attr" => " return 1;\n",
376 "comment" => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
382 "state" => "exc_pinned",
383 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "eax in_r1", "edx in_r3" ] },
384 "attr" => "ia32_op_flavour_t dm_flav",
385 "init_attr" => " attr->data.op_flav = dm_flav;",
386 "cmp_attr" => " return attr_a->data.op_flav != attr_b->data.op_flav;\n",
388 ' if (mode_is_signed(get_irn_mode(n))) {
389 4. idiv %S2 /* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
392 4. div %S2 /* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
395 "outs" => [ "div_res", "mod_res", "M" ],
400 "comment" => "construct Shl: Shl(a, b) = a << b",
401 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
402 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
403 "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */',
404 "outs" => [ "res", "M" ],
408 "cmp_attr" => " return 1;\n",
409 "comment" => "construct lowered Shl: Shl(a, b) = a << b",
415 "comment" => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
416 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
417 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r5" ] },
420 if (get_ia32_immop_type(n) == ia32_ImmNone) {
421 if (get_ia32_op_type(n) == ia32_AddrModeD) {
422 4. shld %ia32_emit_am, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
425 4. shld %S3, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
429 if (get_ia32_op_type(n) == ia32_AddrModeD) {
430 4. shld %ia32_emit_am, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
433 4. shld %S3, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
437 "outs" => [ "res", "M" ],
441 "cmp_attr" => " return 1;\n",
442 "comment" => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
448 "comment" => "construct Shr: Shr(a, b) = a >> b",
449 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
450 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
451 "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */',
452 "outs" => [ "res", "M" ],
456 "cmp_attr" => " return 1;\n",
457 "comment" => "construct lowered Shr: Shr(a, b) = a << b",
463 "comment" => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
464 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
465 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r5" ] },
468 if (get_ia32_immop_type(n) == ia32_ImmNone) {
469 if (get_ia32_op_type(n) == ia32_AddrModeD) {
470 4. shrd %ia32_emit_am, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
473 4. shrd %S3, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
477 if (get_ia32_op_type(n) == ia32_AddrModeD) {
478 4. shrd %ia32_emit_am, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
481 4. shrd %S3, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
485 "outs" => [ "res", "M" ],
489 "cmp_attr" => " return 1;\n",
490 "comment" => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
496 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
497 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
498 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
499 "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */',
500 "outs" => [ "res", "M" ],
504 "cmp_attr" => " return 1;\n",
505 "comment" => "construct lowered Shrs: Shrs(a, b) = a << b",
511 "comment" => "construct RotR: RotR(a, b) = a ROTR b",
512 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
513 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
514 "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */',
515 "outs" => [ "res", "M" ],
520 "comment" => "construct RotL: RotL(a, b) = a ROTL b",
521 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
522 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
523 "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */',
524 "outs" => [ "res", "M" ],
531 "comment" => "construct Minus: Minus(a) = -a",
532 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
533 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
534 "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */',
535 "outs" => [ "res", "M" ],
539 "cmp_attr" => " return 1;\n",
540 "comment" => "construct lowered Minus: Minus(a) = -a",
546 "comment" => "construct Increment: Inc(a) = a++",
547 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
548 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
549 "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */',
550 "outs" => [ "res", "M" ],
555 "comment" => "construct Decrement: Dec(a) = a--",
556 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
557 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
558 "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */',
559 "outs" => [ "res", "M" ],
564 "comment" => "construct Not: Not(a) = !a",
565 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
566 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
567 "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */',
568 "outs" => [ "res", "M" ],
574 "op_flags" => "L|X|Y",
575 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
576 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
577 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
578 "outs" => [ "false", "true" ],
582 "op_flags" => "L|X|Y",
583 "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
584 "reg_req" => { "in" => [ "gp", "gp" ] },
585 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
586 "outs" => [ "false", "true" ],
590 "op_flags" => "L|X|Y",
591 "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
592 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
593 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
594 "outs" => [ "false", "true" ],
598 "op_flags" => "L|X|Y",
599 "comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
600 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
601 "reg_req" => { "in" => [ "gp", "gp" ] },
605 "op_flags" => "L|X|Y",
606 "comment" => "construct switch",
607 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
608 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
614 "comment" => "represents an integer constant",
615 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
616 "reg_req" => { "in" => [ "none" ], "out" => [ "gp" ] },
621 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
622 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
623 "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */',
624 "outs" => [ "EAX", "EDX" ],
632 "state" => "exc_pinned",
633 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
634 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
635 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
637 ' if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) {
638 4. mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
641 4. mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
644 "outs" => [ "res", "M" ],
649 "cmp_attr" => " return 1;\n",
650 "comment" => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg",
651 "outs" => [ "res", "M" ],
657 "cmp_attr" => " return 1;\n",
658 "state" => "exc_pinned",
659 "comment" => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val",
666 "state" => "exc_pinned",
667 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
668 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
669 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
670 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
676 "state" => "exc_pinned",
677 "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
678 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
679 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
680 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
686 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
687 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
688 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
689 "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */'
693 "comment" => "push a gp register on the stack",
694 "reg_req" => { "in" => [ "esp", "gp", "none" ], "out" => [ "esp" ] },
696 if (get_ia32_id_cnst(n)) {
697 if (get_ia32_immop_type(n) == ia32_ImmConst) {
698 . push %C /* Push(%A2) */
700 . push OFFSET FLAT:%C /* Push(%A2) */
704 . push %S2 /* Push(%A2) */
707 "outs" => [ "stack", "M" ],
711 "comment" => "pop a gp register from the stack",
712 "reg_req" => { "in" => [ "esp", "none" ], "out" => [ "gp", "esp" ] },
713 "emit" => '. pop %D1 /* Pop -> %D1 */',
714 "outs" => [ "res", "stack", "M" ],
718 "comment" => "create stack frame",
719 "reg_req" => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] },
720 "emit" => '. enter /* Enter */',
721 "outs" => [ "frame", "stack", "M" ],
725 "comment" => "destroy stack frame",
726 "reg_req" => { "in" => [ "esp", "ebp" ], "out" => [ "ebp", "esp" ] },
727 "emit" => '. leave /* Leave */',
728 "outs" => [ "frame", "stack", "M" ],
731 #-----------------------------------------------------------------------------#
732 # _____ _____ ______ __ _ _ _ #
733 # / ____/ ____| ____| / _| | | | | | #
734 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
735 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
736 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
737 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
738 #-----------------------------------------------------------------------------#
740 # commutative operations
744 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
745 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
746 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
747 "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */',
748 "outs" => [ "res", "M" ],
753 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
754 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
755 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
756 "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */',
757 "outs" => [ "res", "M" ],
762 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
763 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
764 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
765 "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */',
766 "outs" => [ "res", "M" ],
771 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
772 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
773 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
774 "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */',
775 "outs" => [ "res", "M" ],
780 "comment" => "construct SSE And: And(a, b) = a AND b",
781 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
782 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
783 "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */',
784 "outs" => [ "res", "M" ],
789 "comment" => "construct SSE Or: Or(a, b) = a OR b",
790 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
791 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
792 "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */',
793 "outs" => [ "res", "M" ],
798 "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
799 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
800 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
801 "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */',
802 "outs" => [ "res", "M" ],
805 # not commutative operations
809 "comment" => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
810 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
811 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
812 "emit" => '. andnp%M %ia32_emit_binop /* SSE AndNot(%A3, %A4) -> %D1 */',
813 "outs" => [ "res", "M" ],
818 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
819 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
820 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
821 "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */',
822 "outs" => [ "res", "M" ],
827 "comment" => "construct SSE Div: Div(a, b) = a / b",
828 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
829 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
830 "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */',
831 "outs" => [ "res", "M" ],
838 "comment" => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
839 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
840 "outs" => [ "res", "M" ],
844 "op_flags" => "L|X|Y",
845 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
846 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
847 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
848 "outs" => [ "false", "true" ],
854 "comment" => "represents a SSE constant",
855 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
856 "reg_req" => { "in" => [ "none" ], "out" => [ "xmm" ] },
857 "emit" => '. movs%M %D1, %C /* Load fConst into register */',
865 "state" => "exc_pinned",
866 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
867 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
868 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm" ] },
869 "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */',
870 "outs" => [ "res", "M" ],
875 "state" => "exc_pinned",
876 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
877 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
878 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
879 "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */',
885 "comment" => "construct: transfer a value from x87 FPU into a SSE register",
886 "cmp_attr" => " return 1;\n",
892 "comment" => "construct: transfer a value from SSE register to x87 FPU",
893 "cmp_attr" => " return 1;\n",
902 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
903 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "none" ] },
909 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
910 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
911 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "none" ] },
917 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
918 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
919 "comment" => "construct Conv Int -> Int",
920 "outs" => [ "res", "M" ],
924 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
925 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
926 "comment" => "construct Conv Int -> Int",
927 "outs" => [ "res", "M" ],
931 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
932 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
933 "comment" => "construct Conv Int -> Floating Point",
934 "outs" => [ "res", "M" ],
938 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
939 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
940 "comment" => "construct Conv Floating Point -> Int",
941 "outs" => [ "res", "M" ],
945 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
946 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
947 "comment" => "construct Conv Floating Point -> Floating Point",
948 "outs" => [ "res", "M" ],
953 "comment" => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
954 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "in_r4" ] }
959 "comment" => "check if Psi condition tree evaluates to true and move result accordingly",
960 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r3" ] }
965 "comment" => "construct Conditional Move: SSE Compare + int CMov ",
966 "reg_req" => { "in" => [ "xmm", "xmm", "gp", "gp" ], "out" => [ "in_r4" ] }
971 "comment" => "construct Conditional Move: x87 Compare + int CMov",
972 "reg_req" => { "in" => [ "vfp", "vfp", "gp", "gp" ], "out" => [ "in_r4" ] }
977 "comment" => "construct Set: Set(sel) == sel ? 1 : 0",
978 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
979 "outs" => [ "res", "M" ],
984 "comment" => "check if Psi condition tree evaluates to true and set result accordingly",
985 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax ebx ecx edx" ] },
990 "comment" => "construct Set: SSE Compare + int Set",
991 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
992 "outs" => [ "res", "M" ],
997 "comment" => "construct Set: x87 Compare + int Set",
998 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
999 "outs" => [ "res", "M" ],
1004 "comment" => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
1005 "reg_req" => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] }
1008 #----------------------------------------------------------#
1010 # (_) | | | | / _| | | | #
1011 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
1012 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
1013 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
1014 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
1016 # _ __ ___ __| | ___ ___ #
1017 # | '_ \ / _ \ / _` |/ _ \/ __| #
1018 # | | | | (_) | (_| | __/\__ \ #
1019 # |_| |_|\___/ \__,_|\___||___/ #
1020 #----------------------------------------------------------#
1024 "comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
1025 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1026 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1027 "outs" => [ "res", "M" ],
1032 "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1033 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1034 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1035 "outs" => [ "res", "M" ],
1040 "cmp_attr" => " return 1;\n",
1041 "comment" => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1047 "comment" => "virtual fp Sub: Sub(a, b) = a - b",
1048 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1049 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1050 "outs" => [ "res", "M" ],
1054 "cmp_attr" => " return 1;\n",
1055 "comment" => "lowered virtual fp Sub: Sub(a, b) = a - b",
1060 "comment" => "virtual fp Div: Div(a, b) = a / b",
1061 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1062 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1063 "outs" => [ "res", "M" ],
1067 "cmp_attr" => " return 1;\n",
1068 "comment" => "lowered virtual fp Div: Div(a, b) = a / b",
1074 "comment" => "virtual fp Abs: Abs(a) = |a|",
1075 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1080 "comment" => "virtual fp Chs: Chs(a) = -a",
1081 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1086 "comment" => "virtual fp Sin: Sin(a) = sin(a)",
1087 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1092 "comment" => "virtual fp Cos: Cos(a) = cos(a)",
1093 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1098 "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
1099 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1102 # virtual Load and Store
1105 "op_flags" => "L|F",
1107 "state" => "exc_pinned",
1108 "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
1109 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1110 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1111 "outs" => [ "res", "M" ],
1115 "op_flags" => "L|F",
1116 "state" => "exc_pinned",
1117 "comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
1118 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1119 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1127 "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1128 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1129 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1130 "outs" => [ "res", "M" ],
1134 "cmp_attr" => " return 1;\n",
1135 "comment" => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1136 "outs" => [ "res", "M" ],
1141 "comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1142 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1143 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1148 "cmp_attr" => " return 1;\n",
1149 "comment" => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1159 "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg",
1160 "reg_req" => { "out" => [ "vfp" ] },
1165 "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg",
1166 "reg_req" => { "out" => [ "vfp" ] },
1171 "comment" => "virtual fp Load pi: Ld pi -> reg",
1172 "reg_req" => { "out" => [ "vfp" ] },
1177 "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg",
1178 "reg_req" => { "out" => [ "vfp" ] },
1183 "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg",
1184 "reg_req" => { "out" => [ "vfp" ] },
1189 "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg",
1190 "reg_req" => { "out" => [ "vfp" ] },
1195 "comment" => "virtual fp Load ld e: Ld ld e -> reg",
1196 "reg_req" => { "out" => [ "vfp" ] },
1202 "init_attr" => " set_ia32_ls_mode(res, mode);",
1203 "comment" => "represents a virtual floating point constant",
1204 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1205 "reg_req" => { "in" => [ "none" ], "out" => [ "vfp" ] },
1211 "op_flags" => "L|X|Y",
1212 "comment" => "represents a virtual floating point compare",
1213 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1214 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] },
1215 "outs" => [ "false", "true", "temp_reg_eax" ],
1218 #------------------------------------------------------------------------#
1219 # ___ _____ __ _ _ _ #
1220 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1221 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1222 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1223 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1224 #------------------------------------------------------------------------#
1228 "rd_constructor" => "NONE",
1229 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1231 "emit" => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */',
1236 "rd_constructor" => "NONE",
1237 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1239 "emit" => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */',
1244 "rd_constructor" => "NONE",
1245 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1247 "emit" => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */',
1252 "rd_constructor" => "NONE",
1253 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1255 "emit" => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */',,
1260 "rd_constructor" => "NONE",
1261 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1263 "emit" => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */',
1268 "rd_constructor" => "NONE",
1269 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1271 "emit" => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */',
1276 "rd_constructor" => "NONE",
1278 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1280 "emit" => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */',
1285 "rd_constructor" => "NONE",
1287 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1289 "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */',
1294 "rd_constructor" => "NONE",
1295 "comment" => "x87 fp Div: Div(a, b) = a / b",
1297 "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */',
1302 "rd_constructor" => "NONE",
1303 "comment" => "x87 fp Div: Div(a, b) = a / b",
1305 "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */',
1310 "rd_constructor" => "NONE",
1311 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1313 "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */',
1318 "rd_constructor" => "NONE",
1319 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1321 "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */',
1326 "rd_constructor" => "NONE",
1327 "comment" => "x87 fp Abs: Abs(a) = |a|",
1329 "emit" => '. fabs /* x87 fabs(%S1) -> %D1 */',
1334 "rd_constructor" => "NONE",
1335 "comment" => "x87 fp Chs: Chs(a) = -a",
1337 "emit" => '. fchs /* x87 fchs(%S1) -> %D1 */',
1342 "rd_constructor" => "NONE",
1343 "comment" => "x87 fp Sin: Sin(a) = sin(a)",
1345 "emit" => '. fsin /* x87 sin(%S1) -> %D1 */',
1350 "rd_constructor" => "NONE",
1351 "comment" => "x87 fp Cos: Cos(a) = cos(a)",
1353 "emit" => '. fcos /* x87 cos(%S1) -> %D1 */',
1358 "rd_constructor" => "NONE",
1359 "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1361 "emit" => '. fsqrt $ /* x87 sqrt(%S1) -> %D1 */',
1364 # x87 Load and Store
1367 "rd_constructor" => "NONE",
1368 "op_flags" => "R|L|F",
1369 "state" => "exc_pinned",
1370 "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1372 "emit" => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */',
1376 "rd_constructor" => "NONE",
1377 "op_flags" => "R|L|F",
1378 "state" => "exc_pinned",
1379 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1381 "emit" => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */',
1385 "rd_constructor" => "NONE",
1386 "op_flags" => "R|L|F",
1387 "state" => "exc_pinned",
1388 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1390 "emit" => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */',
1398 "rd_constructor" => "NONE",
1399 "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1401 "emit" => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */',
1406 "rd_constructor" => "NONE",
1407 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1409 "emit" => '. fist %ia32_emit_am /* integer Store(%A3) -> (%A1) */',
1414 "rd_constructor" => "NONE",
1415 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1417 "emit" => '. fistp %ia32_emit_am /* integer Store(%A3) -> (%A1) and pop */',
1424 "rd_constructor" => "NONE",
1425 "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
1427 "emit" => '. fldz /* x87 0.0 -> %D1 */',
1432 "rd_constructor" => "NONE",
1433 "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
1435 "emit" => '. fld1 /* x87 1.0 -> %D1 */',
1440 "rd_constructor" => "NONE",
1441 "comment" => "x87 fp Load pi: Ld pi -> reg",
1443 "emit" => '. fldpi /* x87 pi -> %D1 */',
1448 "rd_constructor" => "NONE",
1449 "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
1451 "emit" => '. fldln2 /* x87 ln(2) -> %D1 */',
1456 "rd_constructor" => "NONE",
1457 "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
1459 "emit" => '. fldlg2 /* x87 log(2) -> %D1 */',
1464 "rd_constructor" => "NONE",
1465 "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
1467 "emit" => '. fldll2t /* x87 ld(10) -> %D1 */',
1472 "rd_constructor" => "NONE",
1473 "comment" => "x87 fp Load ld e: Ld ld e -> reg",
1475 "emit" => '. fldl2e /* x87 ld(e) -> %D1 */',
1479 "op_flags" => "R|c",
1481 "rd_constructor" => "NONE",
1482 "comment" => "represents a x87 constant",
1483 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1484 "reg_req" => { "out" => [ "st" ] },
1485 "emit" => '. fld %ia32_emit_adr /* Load fConst into register -> %D1 */',
1489 # Note that it is NEVER allowed to do CSE on these nodes
1492 "op_flags" => "R|K",
1493 "comment" => "x87 stack exchange",
1494 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1495 "cmp_attr" => " return 1;\n",
1496 "emit" => '. fxch %X1 /* x87 swap %X1, %X3 */',
1501 "comment" => "x87 stack push",
1502 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1503 "cmp_attr" => " return 1;\n",
1504 "emit" => '. fld %X1 /* x87 push %X1 */',
1508 "op_flags" => "R|K",
1509 "comment" => "x87 stack pop",
1510 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1511 "cmp_attr" => " return 1;\n",
1512 "emit" => '. fstp %X1 /* x87 pop %X1 */',
1518 "op_flags" => "L|X|Y",
1519 "comment" => "floating point compare",
1520 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1525 "op_flags" => "L|X|Y",
1526 "comment" => "floating point compare and pop",
1527 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1532 "op_flags" => "L|X|Y",
1533 "comment" => "floating point compare and pop twice",
1534 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1539 "op_flags" => "L|X|Y",
1540 "comment" => "floating point compare reverse",
1541 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1546 "op_flags" => "L|X|Y",
1547 "comment" => "floating point compare reverse and pop",
1548 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1553 "op_flags" => "L|X|Y",
1554 "comment" => "floating point compare reverse and pop twice",
1555 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",