3 # This is the specification for the ia32 assembler Firm-operations
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
8 # this string marks the beginning of a comment in emit
9 $comment_string = "/*";
11 # the number of additional opcodes you want to register
12 #$additional_opcodes = 0;
14 # The node description is done as a perl hash initializer with the
15 # following structure:
20 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
21 # "irn_flags" => "R|N|I"
22 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
23 # "state" => "floats|pinned|mem_pinned|exc_pinned",
25 # { "type" => "type 1", "name" => "name 1" },
26 # { "type" => "type 2", "name" => "name 2" },
29 # "comment" => "any comment for constructor",
30 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
31 # "cmp_attr" => "c source code for comparing node attributes",
32 # "emit" => "emit code with templates",
33 # "attr" => "attitional attribute arguments for constructor"
34 # "init_attr" => "emit attribute initialization template"
35 # "rd_constructor" => "c source code which constructs an ir_node"
38 # ... # (all nodes you need to describe)
40 # ); # close the %nodes initializer
42 # op_flags: flags for the operation, OPTIONAL (default is "N")
43 # the op_flags correspond to the firm irop_flags:
46 # C irop_flag_commutative
47 # X irop_flag_cfopcode
48 # I irop_flag_ip_cfopcode
51 # H irop_flag_highlevel
52 # c irop_flag_constlike
55 # irn_flags: special node flags, OPTIONAL (default is 0)
56 # following irn_flags are supported:
59 # I ignore for register allocation
61 # state: state of the operation, OPTIONAL (default is "floats")
63 # arity: arity of the operation, MUST NOT BE OMITTED
65 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
66 # are always the first 3 arguments and are always autmatically
68 # If this key is missing the following arguments will be created:
69 # for i = 1 .. arity: ir_node *op_i
72 # outs: if a node defines more than one output, the names of the projections
73 # nodes having outs having automatically the mode mode_T
75 # comment: OPTIONAL comment for the node constructor
77 # rd_constructor: for every operation there will be a
78 # new_rd_<arch>_<op-name> function with the arguments from above
79 # which creates the ir_node corresponding to the defined operation
80 # you can either put the complete source code of this function here
82 # This key is OPTIONAL. If omitted, the following constructor will
84 # if (!op_<arch>_<op-name>) assert(0);
88 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
91 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
95 # 1 - caller save (register must be saved by the caller of a function)
96 # 2 - callee save (register must be saved by the called function)
97 # 4 - ignore (do not assign this register)
98 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
101 { "name" => "eax", "type" => 1 },
102 { "name" => "edx", "type" => 1 },
103 { "name" => "ebx", "type" => 2 },
104 { "name" => "ecx", "type" => 1 },
105 { "name" => "esi", "type" => 2 },
106 { "name" => "edi", "type" => 2 },
107 # { "name" => "r11", "type" => 1 },
108 # { "name" => "r12", "type" => 1 },
109 # { "name" => "r13", "type" => 1 },
110 # { "name" => "r14", "type" => 1 },
111 # { "name" => "r15", "type" => 1 },
112 # { "name" => "r16", "type" => 1 },
113 # { "name" => "r17", "type" => 1 },
114 # { "name" => "r18", "type" => 1 },
115 # { "name" => "r19", "type" => 1 },
116 # { "name" => "r20", "type" => 1 },
117 # { "name" => "r21", "type" => 1 },
118 # { "name" => "r22", "type" => 1 },
119 # { "name" => "r23", "type" => 1 },
120 # { "name" => "r24", "type" => 1 },
121 # { "name" => "r25", "type" => 1 },
122 # { "name" => "r26", "type" => 1 },
123 # { "name" => "r27", "type" => 1 },
124 # { "name" => "r28", "type" => 1 },
125 # { "name" => "r29", "type" => 1 },
126 # { "name" => "r30", "type" => 1 },
127 # { "name" => "r31", "type" => 1 },
128 # { "name" => "r32", "type" => 1 },
129 { "name" => "ebp", "type" => 2 },
130 { "name" => "esp", "type" => 4 },
131 { "name" => "gp_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
132 { "name" => "gp_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
133 { "mode" => "mode_P" }
136 { "name" => "xmm0", "type" => 1 },
137 { "name" => "xmm1", "type" => 1 },
138 { "name" => "xmm2", "type" => 1 },
139 { "name" => "xmm3", "type" => 1 },
140 { "name" => "xmm4", "type" => 1 },
141 { "name" => "xmm5", "type" => 1 },
142 { "name" => "xmm6", "type" => 1 },
143 { "name" => "xmm7", "type" => 1 },
144 { "name" => "xmm_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
145 { "name" => "xmm_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
146 { "mode" => "mode_D" }
149 { "name" => "vf0", "type" => 1 },
150 { "name" => "vf1", "type" => 1 },
151 { "name" => "vf2", "type" => 1 },
152 { "name" => "vf3", "type" => 1 },
153 { "name" => "vf4", "type" => 1 },
154 { "name" => "vf5", "type" => 1 },
155 { "name" => "vf6", "type" => 1 },
156 { "name" => "vf7", "type" => 1 },
157 { "name" => "vfp_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
158 { "name" => "vfp_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
159 { "mode" => "mode_E" }
162 { "name" => "st0", "type" => 1 },
163 { "name" => "st1", "type" => 1 },
164 { "name" => "st2", "type" => 1 },
165 { "name" => "st3", "type" => 1 },
166 { "name" => "st4", "type" => 1 },
167 { "name" => "st5", "type" => 1 },
168 { "name" => "st6", "type" => 1 },
169 { "name" => "st7", "type" => 1 },
170 { "mode" => "mode_E" }
174 #--------------------------------------------------#
177 # _ __ _____ __ _ _ __ ___ _ __ ___ #
178 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
179 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
180 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
183 #--------------------------------------------------#
190 #-----------------------------------------------------------------#
193 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
194 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
195 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
196 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
199 #-----------------------------------------------------------------#
201 # commutative operations
204 # All nodes supporting Addressmode have 5 INs:
205 # 1 - base r1 == NoReg in case of no AM or no base
206 # 2 - index r2 == NoReg in case of no AM or no index
207 # 3 - op1 r3 == always present
208 # 4 - op2 r4 == NoReg in case of immediate operation
209 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
213 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
214 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
215 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
216 "emit" => '. add %ia32_emit_binop /* Add(%A3, %A4) -> %D1 */',
217 "outs" => [ "res", "M" ],
221 "comment" => "construct Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
222 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
223 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
224 "emit" => '. adc %ia32_emit_binop /* AddC(%A3, %A4) -> %D1 */',
225 "outs" => [ "res", "M" ],
231 "comment" => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
237 "comment" => "construct lowered Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
243 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
244 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
245 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
246 "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */',
247 "outs" => [ "res", "M" ],
250 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
252 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
253 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
254 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r3", "edx in_r4" ] },
255 "emit" => '. imul %ia32_emit_binop /* Mulh(%A1, %A2) -> %D1 */',
256 "outs" => [ "EAX", "EDX", "M" ],
261 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
262 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
263 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
264 "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */',
265 "outs" => [ "res", "M" ],
270 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
271 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
272 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
273 "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */',
274 "outs" => [ "res", "M" ],
279 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
280 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
281 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
282 "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */',
283 "outs" => [ "res", "M" ],
288 "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
289 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
291 '2. cmp %S1, %S2 /* prepare Max (%S1 - %S2), (%A1, %A2) */
292 if (mode_is_signed(get_irn_mode(n))) {
293 4. cmovl %D1, %S2 /* %S1 is less %S2 */
296 4. cmovb %D1, %S2 /* %S1 is below %S2 */
303 "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
304 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
306 '2. cmp %S1, %S2 /* prepare Min (%S1 - %S2), (%A1, %A2) */
307 if (mode_is_signed(get_irn_mode(n))) {
308 2. cmovg %D1, %S2 /* %S1 is greater %S2 */
311 2. cmova %D1, %S2, %D1 /* %S1 is above %S2 */
316 # not commutative operations
320 "comment" => "construct Sub: Sub(a, b) = a - b",
321 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
322 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
323 "emit" => '. sub %ia32_emit_binop /* Sub(%A3, %A4) -> %D1 */',
324 "outs" => [ "res", "M" ],
328 "comment" => "construct Sub with Carry: SubC(a, b) = a - b - carry",
329 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
330 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
331 "emit" => '. sbb %ia32_emit_binop /* SubC(%A3, %A4) -> %D1 */',
332 "outs" => [ "res", "M" ],
337 "comment" => "construct lowered Sub: Sub(a, b) = a - b",
342 "comment" => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
348 "state" => "exc_pinned",
349 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "eax in_r1", "edx in_r3" ] },
350 "attr" => "ia32_op_flavour_t dm_flav",
351 "init_attr" => " attr->data.op_flav = dm_flav;",
352 "cmp_attr" => " return attr_a->data.op_flav != attr_b->data.op_flav;\n",
354 ' if (mode_is_signed(get_irn_mode(n))) {
355 4. idiv %S2 /* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
358 4. div %S2 /* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
361 "outs" => [ "div_res", "mod_res", "M" ],
366 "comment" => "construct Shl: Shl(a, b) = a << b",
367 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
368 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
369 "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */',
370 "outs" => [ "res", "M" ],
375 "comment" => "construct Shr: Shr(a, b) = a >> b",
376 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
377 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
378 "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */',
379 "outs" => [ "res", "M" ],
384 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
385 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
386 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
387 "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */',
388 "outs" => [ "res", "M" ],
393 "comment" => "construct RotR: RotR(a, b) = a ROTR b",
394 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
395 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
396 "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */',
397 "outs" => [ "res", "M" ],
402 "comment" => "construct RotL: RotL(a, b) = a ROTL b",
403 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
404 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
405 "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */',
406 "outs" => [ "res", "M" ],
413 "comment" => "construct Minus: Minus(a) = -a",
414 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
415 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
416 "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */',
417 "outs" => [ "res", "M" ],
422 "comment" => "construct Increment: Inc(a) = a++",
423 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
424 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
425 "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */',
426 "outs" => [ "res", "M" ],
431 "comment" => "construct Decrement: Dec(a) = a--",
432 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
433 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
434 "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */',
435 "outs" => [ "res", "M" ],
440 "comment" => "construct Not: Not(a) = !a",
441 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
442 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
443 "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */',
444 "outs" => [ "res", "M" ],
450 "op_flags" => "L|X|Y",
451 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
452 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
453 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
454 "outs" => [ "false", "true" ],
458 "op_flags" => "L|X|Y",
459 "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
460 "reg_req" => { "in" => [ "gp", "gp" ] },
461 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
462 "outs" => [ "false", "true" ],
466 "op_flags" => "L|X|Y",
467 "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
468 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
469 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
470 "outs" => [ "false", "true" ],
474 "op_flags" => "L|X|Y",
475 "comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
476 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
477 "reg_req" => { "in" => [ "gp", "gp" ] },
481 "op_flags" => "L|X|Y",
482 "comment" => "construct switch",
483 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
484 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
490 "comment" => "represents an integer constant",
491 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
492 "reg_req" => { "in" => [ "none" ], "out" => [ "gp" ] },
497 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
498 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
499 "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */',
500 "outs" => [ "EAX", "EDX" ],
508 "state" => "exc_pinned",
509 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
510 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
511 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
513 ' if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) {
514 4. mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
517 4. mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
520 "outs" => [ "res", "M" ],
525 "state" => "exc_pinned",
526 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
527 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
528 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
529 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
535 "state" => "exc_pinned",
536 "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
537 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
538 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
539 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
545 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
546 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
547 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
548 "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */'
552 "comment" => "push a gp register on the stack",
553 "reg_req" => { "in" => [ "esp", "gp", "none" ], "out" => [ "esp" ] },
555 if (get_ia32_id_cnst(n)) {
556 if (get_ia32_immop_type(n) == ia32_ImmConst) {
557 . push %C /* Push(%A2) */
559 . push OFFSET FLAT:%C /* Push(%A2) */
563 . push %S2 /* Push(%A2) */
566 "outs" => [ "stack", "M" ],
570 "comment" => "pop a gp register from the stack",
571 "reg_req" => { "in" => [ "esp", "none" ], "out" => [ "gp", "esp" ] },
572 "emit" => '. pop %D1 /* Pop -> %D1 */',
573 "outs" => [ "res", "stack", "M" ],
577 "comment" => "create stack frame",
578 "reg_req" => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] },
579 "emit" => '. enter /* Enter */',
580 "outs" => [ "frame", "stack", "M" ],
584 "comment" => "destroy stack frame",
585 "reg_req" => { "in" => [ "esp", "ebp" ], "out" => [ "ebp", "esp" ] },
586 "emit" => '. leave /* Leave */',
587 "outs" => [ "frame", "stack", "M" ],
590 #-----------------------------------------------------------------------------#
591 # _____ _____ ______ __ _ _ _ #
592 # / ____/ ____| ____| / _| | | | | | #
593 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
594 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
595 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
596 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
597 #-----------------------------------------------------------------------------#
599 # commutative operations
603 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
604 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
605 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
606 "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */',
607 "outs" => [ "res", "M" ],
612 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
613 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
614 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
615 "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */',
616 "outs" => [ "res", "M" ],
621 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
622 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
623 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
624 "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */',
625 "outs" => [ "res", "M" ],
630 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
631 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
632 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
633 "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */',
634 "outs" => [ "res", "M" ],
639 "comment" => "construct SSE And: And(a, b) = a AND b",
640 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
641 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
642 "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */',
643 "outs" => [ "res", "M" ],
648 "comment" => "construct SSE Or: Or(a, b) = a OR b",
649 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
650 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
651 "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */',
652 "outs" => [ "res", "M" ],
657 "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
658 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
659 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
660 "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */',
661 "outs" => [ "res", "M" ],
664 # not commutative operations
668 "comment" => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
669 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
670 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
671 "emit" => '. andnp%M %ia32_emit_binop /* SSE AndNot(%A3, %A4) -> %D1 */',
672 "outs" => [ "res", "M" ],
677 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
678 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
679 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
680 "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */',
681 "outs" => [ "res", "M" ],
686 "comment" => "construct SSE Div: Div(a, b) = a / b",
687 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
688 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
689 "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */',
690 "outs" => [ "res", "M" ],
697 "comment" => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
698 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
699 "outs" => [ "res", "M" ],
703 "op_flags" => "L|X|Y",
704 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
705 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
706 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
707 "outs" => [ "false", "true" ],
713 "comment" => "represents a SSE constant",
714 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
715 "reg_req" => { "in" => [ "none" ], "out" => [ "xmm" ] },
716 "emit" => '. movs%M %D1, %C /* Load fConst into register */',
724 "state" => "exc_pinned",
725 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
726 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
727 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm" ] },
728 "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */',
729 "outs" => [ "res", "M" ],
734 "state" => "exc_pinned",
735 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
736 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
737 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
738 "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */',
747 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
748 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "none" ] },
754 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
755 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
756 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "none" ] },
762 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
763 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
764 "comment" => "construct Conv Int -> Int",
765 "outs" => [ "res", "M" ],
769 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
770 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
771 "comment" => "construct Conv Int -> Int",
772 "outs" => [ "res", "M" ],
776 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
777 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
778 "comment" => "construct Conv Int -> Floating Point",
779 "outs" => [ "res", "M" ],
783 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
784 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
785 "comment" => "construct Conv Floating Point -> Int",
786 "outs" => [ "res", "M" ],
790 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
791 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
792 "comment" => "construct Conv Floating Point -> Floating Point",
793 "outs" => [ "res", "M" ],
798 "comment" => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
799 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "in_r4" ] }
804 "comment" => "check if Psi condition tree evaluates to true and move result accordingly",
805 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r3" ] }
810 "comment" => "construct Conditional Move: SSE Compare + int CMov ",
811 "reg_req" => { "in" => [ "xmm", "xmm", "gp", "gp" ], "out" => [ "in_r4" ] }
816 "comment" => "construct Conditional Move: x87 Compare + int CMov",
817 "reg_req" => { "in" => [ "vfp", "vfp", "gp", "gp" ], "out" => [ "in_r4" ] }
822 "comment" => "construct Set: Set(sel) == sel ? 1 : 0",
823 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
824 "outs" => [ "res", "M" ],
829 "comment" => "check if Psi condition tree evaluates to true and set result accordingly",
830 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax ebx ecx edx" ] },
835 "comment" => "construct Set: SSE Compare + int Set",
836 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
837 "outs" => [ "res", "M" ],
842 "comment" => "construct Set: x87 Compare + int Set",
843 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
844 "outs" => [ "res", "M" ],
849 "comment" => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
850 "reg_req" => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] }
853 #----------------------------------------------------------#
855 # (_) | | | | / _| | | | #
856 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
857 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
858 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
859 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
861 # _ __ ___ __| | ___ ___ #
862 # | '_ \ / _ \ / _` |/ _ \/ __| #
863 # | | | | (_) | (_| | __/\__ \ #
864 # |_| |_|\___/ \__,_|\___||___/ #
865 #----------------------------------------------------------#
869 "comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
870 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
871 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
872 "outs" => [ "res", "M" ],
877 "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a + b",
878 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
879 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
880 "outs" => [ "res", "M" ],
885 "comment" => "virtual fp Sub: Sub(a, b) = a - b",
886 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
887 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
888 "outs" => [ "res", "M" ],
892 "comment" => "virtual fp Div: Div(a, b) = a / b",
893 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
894 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
895 "outs" => [ "res", "M" ],
900 "comment" => "virtual fp Abs: Abs(a) = |a|",
901 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
906 "comment" => "virtual fp Chs: Chs(a) = -a",
907 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
912 "comment" => "virtual fp Sin: Sin(a) = sin(a)",
913 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
918 "comment" => "virtual fp Cos: Cos(a) = cos(a)",
919 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
924 "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
925 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
928 # virtual Load and Store
933 "state" => "exc_pinned",
934 "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
935 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
936 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
937 "outs" => [ "res", "M" ],
942 "state" => "exc_pinned",
943 "comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
944 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
945 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
953 "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
954 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
955 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
956 "outs" => [ "res", "M" ],
960 "comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
961 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
962 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
970 "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg",
971 "reg_req" => { "out" => [ "vfp" ] },
976 "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg",
977 "reg_req" => { "out" => [ "vfp" ] },
982 "comment" => "virtual fp Load pi: Ld pi -> reg",
983 "reg_req" => { "out" => [ "vfp" ] },
988 "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg",
989 "reg_req" => { "out" => [ "vfp" ] },
994 "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg",
995 "reg_req" => { "out" => [ "vfp" ] },
1000 "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg",
1001 "reg_req" => { "out" => [ "vfp" ] },
1006 "comment" => "virtual fp Load ld e: Ld ld e -> reg",
1007 "reg_req" => { "out" => [ "vfp" ] },
1013 "init_attr" => " set_ia32_ls_mode(res, mode);",
1014 "comment" => "represents a virtual floating point constant",
1015 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1016 "reg_req" => { "in" => [ "none" ], "out" => [ "vfp" ] },
1022 "op_flags" => "L|X|Y",
1023 "comment" => "represents a virtual floating point compare",
1024 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1025 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] },
1026 "outs" => [ "false", "true", "temp_reg_eax" ],
1029 #------------------------------------------------------------------------#
1030 # ___ _____ __ _ _ _ #
1031 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1032 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1033 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1034 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1035 #------------------------------------------------------------------------#
1039 "rd_constructor" => "NONE",
1040 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1042 "emit" => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */',
1047 "rd_constructor" => "NONE",
1048 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1050 "emit" => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */',
1055 "rd_constructor" => "NONE",
1056 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1058 "emit" => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */',
1063 "rd_constructor" => "NONE",
1064 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1066 "emit" => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */',,
1071 "rd_constructor" => "NONE",
1072 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1074 "emit" => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */',
1079 "rd_constructor" => "NONE",
1080 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1082 "emit" => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */',
1087 "rd_constructor" => "NONE",
1089 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1091 "emit" => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */',
1096 "rd_constructor" => "NONE",
1098 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1100 "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */',
1105 "rd_constructor" => "NONE",
1106 "comment" => "x87 fp Div: Div(a, b) = a / b",
1108 "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */',
1113 "rd_constructor" => "NONE",
1114 "comment" => "x87 fp Div: Div(a, b) = a / b",
1116 "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */',
1121 "rd_constructor" => "NONE",
1122 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1124 "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */',
1129 "rd_constructor" => "NONE",
1130 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1132 "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */',
1137 "rd_constructor" => "NONE",
1138 "comment" => "x87 fp Abs: Abs(a) = |a|",
1140 "emit" => '. fabs /* x87 fabs(%S1) -> %D1 */',
1145 "rd_constructor" => "NONE",
1146 "comment" => "x87 fp Chs: Chs(a) = -a",
1148 "emit" => '. fchs /* x87 fchs(%S1) -> %D1 */',
1153 "rd_constructor" => "NONE",
1154 "comment" => "x87 fp Sin: Sin(a) = sin(a)",
1156 "emit" => '. fsin /* x87 sin(%S1) -> %D1 */',
1161 "rd_constructor" => "NONE",
1162 "comment" => "x87 fp Cos: Cos(a) = cos(a)",
1164 "emit" => '. fcos /* x87 cos(%S1) -> %D1 */',
1169 "rd_constructor" => "NONE",
1170 "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1172 "emit" => '. fsqrt $ /* x87 sqrt(%S1) -> %D1 */',
1175 # x87 Load and Store
1178 "rd_constructor" => "NONE",
1179 "op_flags" => "R|L|F",
1180 "state" => "exc_pinned",
1181 "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1183 "emit" => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */',
1187 "rd_constructor" => "NONE",
1188 "op_flags" => "R|L|F",
1189 "state" => "exc_pinned",
1190 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1192 "emit" => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */',
1196 "rd_constructor" => "NONE",
1197 "op_flags" => "R|L|F",
1198 "state" => "exc_pinned",
1199 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1201 "emit" => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */',
1209 "rd_constructor" => "NONE",
1210 "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1212 "emit" => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */',
1217 "rd_constructor" => "NONE",
1218 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1220 "emit" => '. fist %ia32_emit_am /* integer Store(%A3) -> (%A1) */',
1225 "rd_constructor" => "NONE",
1226 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1228 "emit" => '. fistp %ia32_emit_am /* integer Store(%A3) -> (%A1) and pop */',
1235 "rd_constructor" => "NONE",
1236 "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
1238 "emit" => '. fldz /* x87 0.0 -> %D1 */',
1243 "rd_constructor" => "NONE",
1244 "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
1246 "emit" => '. fld1 /* x87 1.0 -> %D1 */',
1251 "rd_constructor" => "NONE",
1252 "comment" => "x87 fp Load pi: Ld pi -> reg",
1254 "emit" => '. fldpi /* x87 pi -> %D1 */',
1259 "rd_constructor" => "NONE",
1260 "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
1262 "emit" => '. fldln2 /* x87 ln(2) -> %D1 */',
1267 "rd_constructor" => "NONE",
1268 "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
1270 "emit" => '. fldlg2 /* x87 log(2) -> %D1 */',
1275 "rd_constructor" => "NONE",
1276 "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
1278 "emit" => '. fldll2t /* x87 ld(10) -> %D1 */',
1283 "rd_constructor" => "NONE",
1284 "comment" => "x87 fp Load ld e: Ld ld e -> reg",
1286 "emit" => '. fldl2e /* x87 ld(e) -> %D1 */',
1290 "op_flags" => "R|c",
1292 "rd_constructor" => "NONE",
1293 "comment" => "represents a x87 constant",
1294 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1295 "reg_req" => { "out" => [ "st" ] },
1296 "emit" => '. fld %ia32_emit_adr /* Load fConst into register -> %D1 */',
1300 # Note that it is NEVER allowed to do CSE on these nodes
1303 "op_flags" => "R|K",
1304 "comment" => "x87 stack exchange",
1305 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1306 "cmp_attr" => " return 1;\n",
1307 "emit" => '. fxch %X1 /* x87 swap %X1, %X3 */',
1312 "comment" => "x87 stack push",
1313 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1314 "cmp_attr" => " return 1;\n",
1315 "emit" => '. fld %X1 /* x87 push %X1 */',
1319 "op_flags" => "R|K",
1320 "comment" => "x87 stack pop",
1321 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1322 "cmp_attr" => " return 1;\n",
1323 "emit" => '. fstp %X1 /* x87 pop %X1 */',
1329 "op_flags" => "L|X|Y",
1330 "comment" => "floating point compare",
1331 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1336 "op_flags" => "L|X|Y",
1337 "comment" => "floating point compare and pop",
1338 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1343 "op_flags" => "L|X|Y",
1344 "comment" => "floating point compare and pop twice",
1345 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1350 "op_flags" => "L|X|Y",
1351 "comment" => "floating point compare reverse",
1352 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1357 "op_flags" => "L|X|Y",
1358 "comment" => "floating point compare reverse and pop",
1359 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1364 "op_flags" => "L|X|Y",
1365 "comment" => "floating point compare reverse and pop twice",
1366 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",