3 # This is the specification for the ia32 assembler Firm-operations
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
8 # this string marks the beginning of a comment in emit
9 $comment_string = "/*";
11 # the number of additional opcodes you want to register
12 $additional_opcodes = 0;
14 # The node description is done as a perl hash initializer with the
15 # following structure:
20 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
21 # "irn_flags" => "R|N|I"
22 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
23 # "state" => "floats|pinned|mem_pinned|exc_pinned",
25 # { "type" => "type 1", "name" => "name 1" },
26 # { "type" => "type 2", "name" => "name 2" },
29 # "comment" => "any comment for constructor",
30 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
31 # "cmp_attr" => "c source code for comparing node attributes",
32 # "emit" => "emit code with templates",
33 # "attr" => "attitional attribute arguments for constructor"
34 # "init_attr" => "emit attribute initialization template"
35 # "rd_constructor" => "c source code which constructs an ir_node"
38 # ... # (all nodes you need to describe)
40 # ); # close the %nodes initializer
42 # op_flags: flags for the operation, OPTIONAL (default is "N")
43 # the op_flags correspond to the firm irop_flags:
46 # C irop_flag_commutative
47 # X irop_flag_cfopcode
48 # I irop_flag_ip_cfopcode
51 # H irop_flag_highlevel
52 # c irop_flag_constlike
55 # irn_flags: special node flags, OPTIONAL (default is 0)
56 # following irn_flags are supported:
59 # I ignore for register allocation
61 # state: state of the operation, OPTIONAL (default is "floats")
63 # arity: arity of the operation, MUST NOT BE OMITTED
65 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
66 # are always the first 3 arguments and are always autmatically
68 # If this key is missing the following arguments will be created:
69 # for i = 1 .. arity: ir_node *op_i
72 # comment: OPTIONAL comment for the node constructor
74 # rd_constructor: for every operation there will be a
75 # new_rd_<arch>_<op-name> function with the arguments from above
76 # which creates the ir_node corresponding to the defined operation
77 # you can either put the complete source code of this function here
79 # This key is OPTIONAL. If omitted, the following constructor will
81 # if (!op_<arch>_<op-name>) assert(0);
85 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
88 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
92 # 1 - caller save (register must be saved by the caller of a function)
93 # 2 - callee save (register must be saved by the called function)
94 # 4 - ignore (do not assign this register)
95 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
98 { "name" => "eax", "type" => 1 },
99 { "name" => "edx", "type" => 1 },
100 { "name" => "ebx", "type" => 2 },
101 { "name" => "ecx", "type" => 1 },
102 { "name" => "esi", "type" => 2 },
103 { "name" => "edi", "type" => 2 },
104 { "name" => "ebp", "type" => 2 },
105 { "name" => "esp", "type" => 4 },
106 { "name" => "gp_NOREG", "type" => 6 }, # we need a dummy register for NoReg and Unknown nodes
107 { "mode" => "mode_P" }
110 { "name" => "xmm0", "type" => 1 },
111 { "name" => "xmm1", "type" => 1 },
112 { "name" => "xmm2", "type" => 1 },
113 { "name" => "xmm3", "type" => 1 },
114 { "name" => "xmm4", "type" => 1 },
115 { "name" => "xmm5", "type" => 1 },
116 { "name" => "xmm6", "type" => 1 },
117 { "name" => "xmm7", "type" => 1 },
118 { "name" => "xmm_NOREG", "type" => 6 }, # we need a dummy register for NoReg and Unknown nodes
119 { "mode" => "mode_D" }
122 { "name" => "vf0", "type" => 1 },
123 { "name" => "vf1", "type" => 1 },
124 { "name" => "vf2", "type" => 1 },
125 { "name" => "vf3", "type" => 1 },
126 { "name" => "vf4", "type" => 1 },
127 { "name" => "vf5", "type" => 1 },
128 { "name" => "vf6", "type" => 1 },
129 { "name" => "vf7", "type" => 4 },
130 { "name" => "vfp_NOREG", "type" => 6 }, # we need a dummy register for NoReg and Unknown nodes
131 { "mode" => "mode_E" }
134 { "name" => "st0", "type" => 1 },
135 { "name" => "st1", "type" => 1 },
136 { "name" => "st2", "type" => 1 },
137 { "name" => "st3", "type" => 1 },
138 { "name" => "st4", "type" => 1 },
139 { "name" => "st5", "type" => 1 },
140 { "name" => "st6", "type" => 1 },
141 { "name" => "st7", "type" => 1 },
142 { "name" => "st_NOREG", "type" => 6 }, # we need a dummy register for NoReg and Unknown nodes
143 { "mode" => "mode_E" }
147 #--------------------------------------------------#
150 # _ __ _____ __ _ _ __ ___ _ __ ___ #
151 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
152 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
153 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
156 #--------------------------------------------------#
160 #-----------------------------------------------------------------#
163 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
164 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
165 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
166 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
169 #-----------------------------------------------------------------#
171 # commutative operations
174 # All nodes supporting Addressmode have 5 INs:
175 # 1 - base r1 == NoReg in case of no AM or no base
176 # 2 - index r2 == NoReg in case of no AM or no index
177 # 3 - op1 r3 == always present
178 # 4 - op2 r4 == NoReg in case of immediate operation
179 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
183 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
184 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
185 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
186 "emit" => '. add %ia32_emit_binop /* Add(%A1, %A2) -> %D1 */',
191 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
192 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
193 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
194 "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */'
197 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
199 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
200 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
201 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r3", "edx in_r4" ] },
202 "emit" => '. imul %ia32_emit_unop /* Mulh(%A1, %A2) -> %D1 */'
207 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
208 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
209 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
210 "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */'
215 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
216 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
217 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
218 "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */'
223 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
224 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
225 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
226 "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */'
231 "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
232 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
234 '2. cmp %S1, %S2 /* prepare Max (%S1 - %S2), (%A1, %A2) */
235 if (mode_is_signed(get_irn_mode(n))) {
236 4. cmovl %D1, %S2 /* %S1 is less %S2 */
239 4. cmovb %D1, %S2 /* %S1 is below %S2 */
246 "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
247 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
249 '2. cmp %S1, %S2 /* prepare Min (%S1 - %S2), (%A1, %A2) */
250 if (mode_is_signed(get_irn_mode(n))) {
251 2. cmovg %D1, %S2 /* %S1 is greater %S2 */
254 2. cmova %D1, %S2, %D1 /* %S1 is above %S2 */
261 "comment" => "construct Mux: Mux(sel, a, b) == sel ? a : b",
262 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r2" ] },
264 '. cmp %S1, 0 /* compare Sel for CMov (%A2, %A3) */
265 . cmovne %D1, %S3 /* sel == true -> return %S3 */
269 # not commutative operations
273 "comment" => "construct Sub: Sub(a, b) = a - b",
274 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
275 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
276 "emit" => '. sub %ia32_emit_binop /* Sub(%A1, %A2) -> %D1 */'
281 "state" => "exc_pinned",
282 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "eax in_r1", "edx in_r3" ] },
284 ' if (mode_is_signed(get_irn_mode(n))) {
285 4. idiv %S2 /* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
288 4. div %S2 /* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
295 "comment" => "construct Shl: Shl(a, b) = a << b",
296 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
297 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
298 "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */'
303 "comment" => "construct Shr: Shr(a, b) = a >> b",
304 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
305 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
306 "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */'
311 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
312 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
313 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
314 "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */'
319 "comment" => "construct RotR: RotR(a, b) = a ROTR b",
320 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
321 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
322 "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */'
327 "comment" => "construct RotL: RotL(a, b) = a ROTL b",
328 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
329 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
330 "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */'
337 "comment" => "construct Minus: Minus(a) = -a",
338 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
339 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
340 "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */'
345 "comment" => "construct Increment: Inc(a) = a++",
346 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
347 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
348 "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */'
353 "comment" => "construct Decrement: Dec(a) = a--",
354 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
355 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
356 "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */'
361 "comment" => "construct Not: Not(a) = !a",
362 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
363 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
364 "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */'
370 "op_flags" => "L|X|Y",
371 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
372 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
373 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
377 "op_flags" => "L|X|Y",
378 "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
379 "reg_req" => { "in" => [ "gp", "gp" ] },
380 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
384 "op_flags" => "L|X|Y",
385 "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
386 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
387 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
391 "op_flags" => "L|X|Y",
392 "comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
393 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
394 "reg_req" => { "in" => [ "gp", "gp" ] },
398 "op_flags" => "L|X|Y",
399 "comment" => "construct switch",
400 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
401 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
407 "comment" => "represents an integer constant",
408 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
409 "reg_req" => { "out" => [ "gp" ] },
411 ' if (get_ia32_Immop_tarval(n) == get_tarval_null(get_irn_mode(n))) {
412 4. sub %D1, %D1 /* optimized mov 0 to register */
415 if (get_ia32_op_type(n) == ia32_SymConst) {
416 6. mov %D1, OFFSET FLAT:%C /* Move address of SymConst into register */
419 6. mov %D1, %C /* Mov Const into register */
427 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
428 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
429 "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */'
437 "state" => "exc_pinned",
438 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
439 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
440 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
442 ' if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) {
443 4. mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
446 4. mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
453 "state" => "exc_pinned",
454 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
455 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
456 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
457 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */'
462 "state" => "exc_pinned",
463 "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
464 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
465 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] }
470 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
471 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
472 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
473 "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */'
476 #--------------------------------------------------------#
479 # | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
480 # | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
481 # | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
482 # |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
483 #--------------------------------------------------------#
485 # commutative operations
489 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
490 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
491 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
492 "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */'
497 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
498 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
499 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
500 "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */'
505 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
506 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
507 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
508 "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */'
513 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
514 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
515 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
516 "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */'
521 "comment" => "construct SSE And: And(a, b) = a AND b",
522 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
523 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
524 "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */'
529 "comment" => "construct SSE Or: Or(a, b) = a OR b",
530 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
531 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
532 "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */'
537 "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
538 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
539 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
540 "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */'
543 # not commutative operations
547 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
548 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
549 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
550 "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */'
555 "comment" => "construct SSE Div: Div(a, b) = a / b",
556 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
557 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
558 "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */'
564 "op_flags" => "L|X|Y",
565 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
566 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
567 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
573 "comment" => "represents a SSE constant",
574 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
575 "reg_req" => { "out" => [ "xmm" ] },
576 "emit" => '. mov%M %D1, %C /* Load fConst into register */',
584 "state" => "exc_pinned",
585 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
586 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
587 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm" ] },
588 "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */'
593 "state" => "exc_pinned",
594 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
595 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
596 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
597 "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */'
605 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
606 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "none" ] },
612 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
613 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
614 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "none" ] },
620 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
621 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
622 "comment" => "construct Conv Int -> Int"
626 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
627 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
628 "comment" => "construct Conv Int -> Int"
632 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
633 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
634 "comment" => "construct Conv Int -> Floating Point"
638 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
639 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
640 "comment" => "construct Conv Floating Point -> Int"
644 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
645 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
646 "comment" => "construct Conv Floating Point -> Floating Point",
649 #--------------------------------------------------------#
652 # | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
653 # | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
654 # | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
655 # |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
656 #--------------------------------------------------------#
658 # virtual float nodes
662 "comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
663 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
664 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
669 "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a + b",
670 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
671 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
676 "comment" => "virtual fp Sub: Sub(a, b) = a - b",
677 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
678 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
683 "comment" => "virtual fp SubR: SubR(a, b) = b - a",
684 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
685 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
689 "comment" => "virtual fp Div: Div(a, b) = a / b",
690 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
691 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
695 "comment" => "virtual fp DivR: DivR(a, b) = b / a",
696 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
697 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
702 "comment" => "virtual fp Abs: Abs(a) = |a|",
703 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
708 "comment" => "virtual fp Chs: Chs(a) = -a",
709 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
714 "comment" => "virtual fp Sin: Sin(a) = sin(a)",
715 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
720 "comment" => "virtual fp Cos: Cos(a) = cos(a)",
721 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
726 "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
727 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
730 # virtual Load and Store
735 "state" => "exc_pinned",
736 "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
737 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
738 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp" ] },
743 "state" => "exc_pinned",
744 "comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
745 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
746 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
753 "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
754 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
755 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp" ] },
759 "comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
760 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
761 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
768 "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg",
769 "reg_req" => { "out" => [ "vfp" ] },
774 "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg",
775 "reg_req" => { "out" => [ "vfp" ] },
780 "comment" => "virtual fp Load pi: Ld pi -> reg",
781 "reg_req" => { "out" => [ "vfp" ] },
786 "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg",
787 "reg_req" => { "out" => [ "vfp" ] },
792 "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg",
793 "reg_req" => { "out" => [ "vfp" ] },
798 "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg",
799 "reg_req" => { "out" => [ "vfp" ] },
804 "comment" => "virtual fp Load ld e: Ld ld e -> reg",
805 "reg_req" => { "out" => [ "vfp" ] },
811 "comment" => "represents a virtual floating point constant",
812 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
813 "reg_req" => { "out" => [ "vfp" ] },
816 #--------------------------------------------------------#
819 # | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
820 # | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
821 # | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
822 # |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
823 #--------------------------------------------------------#
828 "rd_constructor" => "NONE",
829 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
831 # "emit" => '. fadd %ia32_emit_binop /* x87 fadd(%A1, %A2) -> %D1 */'
832 "emit" => '. fadd %X1, %X2 /* x87 fadd(%X1, %X2) -> %X3 */'
836 "rd_constructor" => "NONE",
837 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
839 # "emit" => '. faddp %ia32_emit_binop /* x87 fadd(%A1, %A2) -> %D1 */'
840 "emit" => '. faddp %X1, %X2 /* x87 fadd(%X1, %X2) -> %X3 and pop */'
844 "rd_constructor" => "NONE",
845 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
847 # "emit" => '. fmul %ia32_emit_binop /* x87 fmul(%A1, %A2) -> %D1 */'
848 "emit" => '. fmul %X1, %X2 /* x87 fmul(%X1, %X2) -> %X3 */'
852 "rd_constructor" => "NONE",
853 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
855 # "emit" => '. fmulp %ia32_emit_binop /* x87 fmul(%A1, %A2) -> %D1 */'
856 "emit" => '. fmulp %X1, %X2 /* x87 fmul(%X1, %X2) -> %X3 and pop */'
860 "rd_constructor" => "NONE",
861 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
863 # "emit" => '. fsub %ia32_emit_binop /* x87 fsub(%A1, %A2) -> %D1 */'
864 "emit" => '. fsub %X1, %X2 /* x87 fsub(%X1, %X2) -> %X3 */'
868 "rd_constructor" => "NONE",
869 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
871 # "emit" => '. fsubp %ia32_emit_binop /* x87 fsub(%A1, %A2) -> %D1 */'
872 "emit" => '. fsubp %X1, %X2 /* x87 fsub(%X1, %X2) -> %X3 and pop */'
876 "rd_constructor" => "NONE",
878 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
880 # "emit" => '. fsubr %ia32_emit_binop /* x87 fsubr(%A1, %A2) -> %D1 */'
881 "emit" => '. fsubr %X1, %X2 /* x87 fsubr(%X1, %X2) -> %X3 */'
885 "rd_constructor" => "NONE",
887 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
889 # "emit" => '. fsubrp %ia32_emit_binop /* x87 fsubr(%A1, %A2) -> %D1 */'
890 "emit" => '. fsubrp %X1, %X2 /* x87 fsubr(%X1, %X2) -> %X3 and pop */'
894 "rd_constructor" => "NONE",
895 "comment" => "x87 fp Div: Div(a, b) = a / b",
897 # "emit" => '. fdiv %ia32_emit_binop /* x87 fdiv(%A1, %A2) -> %D1 */'
898 "emit" => '. fdiv %X1, %X2 /* x87 fdiv(%X1, %X2) -> %X3 */'
902 "rd_constructor" => "NONE",
903 "comment" => "x87 fp Div: Div(a, b) = a / b",
905 # "emit" => '. fdivp %ia32_emit_binop /* x87 fdiv(%A1, %A2) -> %D1 */'
906 "emit" => '. fdivp %X1, %X2 /* x87 fdiv(%X1, %X2) -> %X3 and pop */'
910 "rd_constructor" => "NONE",
911 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
913 # "emit" => '. fdivr %ia32_emit_binop /* x87 fdivr(%A1, %A2) -> %D1 */'
914 "emit" => '. fdivr %X1, %X2 /* x87 fdivr(%X1, %X2) -> %X3 */'
918 "rd_constructor" => "NONE",
919 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
921 # "emit" => '. fdivrp %ia32_emit_binop /* x87 fdivr(%A1, %A2) -> %D1 */'
922 "emit" => '. fdivrp %X1, %X2 /* x87 fdivr(%X1, %X2) -> %X3 and pop */'
926 "rd_constructor" => "NONE",
927 "comment" => "x87 fp Abs: Abs(a) = |a|",
929 "emit" => '. fabs %X1 /* x87 fabs(%X1) -> %X3 */'
933 "rd_constructor" => "NONE",
934 "comment" => "x87 fp Chs: Chs(a) = -a",
936 "emit" => '. fchs %X1 /* x87 fchs(%X1) -> %X3 */'
940 "rd_constructor" => "NONE",
941 "comment" => "x87 fp Sin: Sin(a) = sin(a)",
943 "emit" => '. fsin %X1 /* x87 sin(%X1) -> %X3 */'
947 "rd_constructor" => "NONE",
948 "comment" => "x87 fp Cos: Cos(a) = cos(a)",
950 "emit" => '. fcos %X1 /* x87 cos(%X1) -> %X3 */'
954 "rd_constructor" => "NONE",
955 "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
957 "emit" => '. fsqrt %X1 $ /* x87 sqrt(%X1) -> %X3 */'
963 "rd_constructor" => "NONE",
965 "state" => "exc_pinned",
966 "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
968 "emit" => '. fld %X3, %ia32_emit_am /* Load((%A1)) -> %X3 */'
972 "rd_constructor" => "NONE",
974 "state" => "exc_pinned",
975 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
977 "emit" => '. fst %ia32_emit_binop /* Store(%X3) -> (%A1) */'
981 "rd_constructor" => "NONE",
983 "state" => "exc_pinned",
984 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
986 "emit" => '. fstp %ia32_emit_binop /* Store(%X3) -> (%A1) and pop */'
993 "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
995 "emit" => '. fild %X3, %ia32_emit_am /* integer Load((%A1)) -> %X3 */'
999 "rd_constructor" => "NONE",
1000 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1002 "emit" => '. fist %ia32_emit_binop /* integer Store(%X3) -> (%A1) */'
1006 "rd_constructor" => "NONE",
1007 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1009 "emit" => '. fistp %ia32_emit_binop /* integer Store(%X3) -> (%A1) and pop */'
1015 "rd_constructor" => "NONE",
1016 "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
1018 "emit" => '. fldz %X3 /* x87 0.0 -> %X3 */'
1022 "rd_constructor" => "NONE",
1023 "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
1025 "emit" => '. fld1 %X3 /* x87 1.0 -> %X3 */'
1029 "rd_constructor" => "NONE",
1030 "comment" => "x87 fp Load pi: Ld pi -> reg",
1032 "emit" => '. fldpi %X3 /* x87 pi -> %X3 */'
1036 "rd_constructor" => "NONE",
1037 "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
1039 "emit" => '. fldln2 %X3 /* x87 ln(2) -> %X3 */'
1043 "rd_constructor" => "NONE",
1044 "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
1046 "emit" => '. fldlg2 %X3 /* x87 log(2) -> %X3 */'
1050 "rd_constructor" => "NONE",
1051 "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
1053 "emit" => '. fldll2t %X3 /* x87 ld(10) -> %X3 */'
1057 "rd_constructor" => "NONE",
1058 "comment" => "x87 fp Load ld e: Ld ld e -> reg",
1060 "emit" => '. fldl2e %X3 /* x87 ld(e) -> %X3 */'
1066 "comment" => "represents a x87 constant",
1067 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1068 "reg_req" => { "out" => [ "st" ] },
1069 "emit" => '. fld%M %C /* Load fConst into register -> %X3 */',
1075 "comment" => "x87 stack exchange",
1076 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1077 "emit" => '. fxch %X1, %X3 /* x87 swap %X1, %X3 */',
1081 "comment" => "x87 stack push",
1082 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1083 "emit" => '. fld %X1 /* x87 push %X1 */',