3 # This is the specification for the ia32 assembler Firm-operations
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
8 # this string marks the beginning of a comment in emit
9 $comment_string = "/*";
11 # the number of additional opcodes you want to register
12 #$additional_opcodes = 0;
14 # The node description is done as a perl hash initializer with the
15 # following structure:
20 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
21 # "irn_flags" => "R|N|I"
22 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
23 # "state" => "floats|pinned|mem_pinned|exc_pinned",
25 # { "type" => "type 1", "name" => "name 1" },
26 # { "type" => "type 2", "name" => "name 2" },
29 # "comment" => "any comment for constructor",
30 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
31 # "cmp_attr" => "c source code for comparing node attributes",
32 # "emit" => "emit code with templates",
33 # "attr" => "attitional attribute arguments for constructor"
34 # "init_attr" => "emit attribute initialization template"
35 # "rd_constructor" => "c source code which constructs an ir_node"
38 # ... # (all nodes you need to describe)
40 # ); # close the %nodes initializer
42 # op_flags: flags for the operation, OPTIONAL (default is "N")
43 # the op_flags correspond to the firm irop_flags:
46 # C irop_flag_commutative
47 # X irop_flag_cfopcode
48 # I irop_flag_ip_cfopcode
51 # H irop_flag_highlevel
52 # c irop_flag_constlike
55 # irn_flags: special node flags, OPTIONAL (default is 0)
56 # following irn_flags are supported:
59 # I ignore for register allocation
61 # state: state of the operation, OPTIONAL (default is "floats")
63 # arity: arity of the operation, MUST NOT BE OMITTED
65 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
66 # are always the first 3 arguments and are always autmatically
68 # If this key is missing the following arguments will be created:
69 # for i = 1 .. arity: ir_node *op_i
72 # outs: if a node defines more than one output, the names of the projections
73 # nodes having outs having automatically the mode mode_T
75 # comment: OPTIONAL comment for the node constructor
77 # rd_constructor: for every operation there will be a
78 # new_rd_<arch>_<op-name> function with the arguments from above
79 # which creates the ir_node corresponding to the defined operation
80 # you can either put the complete source code of this function here
82 # This key is OPTIONAL. If omitted, the following constructor will
84 # if (!op_<arch>_<op-name>) assert(0);
88 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
91 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
95 # 1 - caller save (register must be saved by the caller of a function)
96 # 2 - callee save (register must be saved by the called function)
97 # 4 - ignore (do not assign this register)
98 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
101 { "name" => "eax", "type" => 1 },
102 { "name" => "edx", "type" => 1 },
103 { "name" => "ebx", "type" => 2 },
104 { "name" => "ecx", "type" => 1 },
105 { "name" => "esi", "type" => 2 },
106 { "name" => "edi", "type" => 2 },
107 # { "name" => "r11", "type" => 1 },
108 # { "name" => "r12", "type" => 1 },
109 # { "name" => "r13", "type" => 1 },
110 # { "name" => "r14", "type" => 1 },
111 # { "name" => "r15", "type" => 1 },
112 # { "name" => "r16", "type" => 1 },
113 # { "name" => "r17", "type" => 1 },
114 # { "name" => "r18", "type" => 1 },
115 # { "name" => "r19", "type" => 1 },
116 # { "name" => "r20", "type" => 1 },
117 # { "name" => "r21", "type" => 1 },
118 # { "name" => "r22", "type" => 1 },
119 # { "name" => "r23", "type" => 1 },
120 # { "name" => "r24", "type" => 1 },
121 # { "name" => "r25", "type" => 1 },
122 # { "name" => "r26", "type" => 1 },
123 # { "name" => "r27", "type" => 1 },
124 # { "name" => "r28", "type" => 1 },
125 # { "name" => "r29", "type" => 1 },
126 # { "name" => "r30", "type" => 1 },
127 # { "name" => "r31", "type" => 1 },
128 # { "name" => "r32", "type" => 1 },
129 { "name" => "ebp", "type" => 2 },
130 { "name" => "esp", "type" => 4 },
131 { "name" => "gp_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
132 { "name" => "gp_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
133 { "mode" => "mode_P" }
136 { "name" => "xmm0", "type" => 1 },
137 { "name" => "xmm1", "type" => 1 },
138 { "name" => "xmm2", "type" => 1 },
139 { "name" => "xmm3", "type" => 1 },
140 { "name" => "xmm4", "type" => 1 },
141 { "name" => "xmm5", "type" => 1 },
142 { "name" => "xmm6", "type" => 1 },
143 { "name" => "xmm7", "type" => 1 },
144 { "name" => "xmm_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
145 { "name" => "xmm_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
146 { "mode" => "mode_D" }
149 { "name" => "vf0", "type" => 1 },
150 { "name" => "vf1", "type" => 1 },
151 { "name" => "vf2", "type" => 1 },
152 { "name" => "vf3", "type" => 1 },
153 { "name" => "vf4", "type" => 1 },
154 { "name" => "vf5", "type" => 1 },
155 { "name" => "vf6", "type" => 1 },
156 { "name" => "vf7", "type" => 1 },
157 { "name" => "vfp_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
158 { "name" => "vfp_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
159 { "mode" => "mode_E" }
162 { "name" => "st0", "type" => 1 },
163 { "name" => "st1", "type" => 1 },
164 { "name" => "st2", "type" => 1 },
165 { "name" => "st3", "type" => 1 },
166 { "name" => "st4", "type" => 1 },
167 { "name" => "st5", "type" => 1 },
168 { "name" => "st6", "type" => 1 },
169 { "name" => "st7", "type" => 1 },
170 { "mode" => "mode_E" }
174 #--------------------------------------------------#
177 # _ __ _____ __ _ _ __ ___ _ __ ___ #
178 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
179 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
180 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
183 #--------------------------------------------------#
190 #-----------------------------------------------------------------#
193 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
194 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
195 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
196 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
199 #-----------------------------------------------------------------#
201 # commutative operations
204 # All nodes supporting Addressmode have 5 INs:
205 # 1 - base r1 == NoReg in case of no AM or no base
206 # 2 - index r2 == NoReg in case of no AM or no index
207 # 3 - op1 r3 == always present
208 # 4 - op2 r4 == NoReg in case of immediate operation
209 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
213 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
214 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
215 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
216 "emit" => '. add %ia32_emit_binop /* Add(%A3, %A4) -> %D1 */',
217 "outs" => [ "res", "M" ],
221 "comment" => "construct Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
222 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
223 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
224 "emit" => '. adc %ia32_emit_binop /* AddC(%A3, %A4) -> %D1 */',
225 "outs" => [ "res", "M" ],
231 "cmp_attr" => " return 1;\n",
232 "comment" => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
238 "cmp_attr" => " return 1;\n",
239 "comment" => "construct lowered Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
244 "comment" => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
245 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
246 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] },
247 "emit" => '. mul %ia32_emit_unop /* Mul(%A1, %A2) -> %D1 */',
248 "outs" => [ "EAX", "EDX", "M" ],
253 "cmp_attr" => " return 1;\n",
254 "comment" => "construct lowered MulS: MulS(a, b) = MulS(b, a) = a * b",
255 "outs" => [ "EAX", "EDX", "M" ],
261 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
262 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
263 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
264 "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */',
265 "outs" => [ "res", "M" ],
270 "cmp_attr" => " return 1;\n",
271 "comment" => "construct lowered Mul: Mul(a, b) = Mul(b, a) = a * b",
275 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
277 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
278 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
279 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] },
280 "emit" => '. imul %ia32_emit_unop /* Mulh(%A1, %A2) -> %D1 */',
281 "outs" => [ "EAX", "EDX", "M" ],
286 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
287 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
288 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
289 "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */',
290 "outs" => [ "res", "M" ],
295 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
296 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
297 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
298 "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */',
299 "outs" => [ "res", "M" ],
304 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
305 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
306 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
307 "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */',
308 "outs" => [ "res", "M" ],
313 "cmp_attr" => " return 1;\n",
314 "comment" => "construct lowered Eor: Eor(a, b) = Eor(b, a) = a EOR b",
320 "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
321 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
323 '2. cmp %S1, %S2 /* prepare Max (%S1 - %S2), (%A1, %A2) */
324 if (mode_is_signed(get_irn_mode(n))) {
325 4. cmovl %D1, %S2 /* %S1 is less %S2 */
328 4. cmovb %D1, %S2 /* %S1 is below %S2 */
335 "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
336 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
338 '2. cmp %S1, %S2 /* prepare Min (%S1 - %S2), (%A1, %A2) */
339 if (mode_is_signed(get_irn_mode(n))) {
340 2. cmovg %D1, %S2 /* %S1 is greater %S2 */
343 2. cmova %D1, %S2, %D1 /* %S1 is above %S2 */
348 # not commutative operations
352 "comment" => "construct Sub: Sub(a, b) = a - b",
353 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
354 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
355 "emit" => '. sub %ia32_emit_binop /* Sub(%A3, %A4) -> %D1 */',
356 "outs" => [ "res", "M" ],
360 "comment" => "construct Sub with Carry: SubC(a, b) = a - b - carry",
361 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
362 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
363 "emit" => '. sbb %ia32_emit_binop /* SubC(%A3, %A4) -> %D1 */',
364 "outs" => [ "res", "M" ],
369 "cmp_attr" => " return 1;\n",
370 "comment" => "construct lowered Sub: Sub(a, b) = a - b",
375 "cmp_attr" => " return 1;\n",
376 "comment" => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
382 "state" => "exc_pinned",
383 "reg_req" => { "in" => [ "eax", "gp", "edx", "none" ], "out" => [ "eax", "edx" ] },
384 "attr" => "ia32_op_flavour_t dm_flav",
385 "init_attr" => " attr->data.op_flav = dm_flav;",
386 "cmp_attr" => " return attr_a->data.op_flav != attr_b->data.op_flav;\n",
388 ' if (mode_is_signed(get_ia32_res_mode(n))) {
389 4. idiv %S2 /* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
392 4. div %S2 /* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
395 "outs" => [ "div_res", "mod_res", "M" ],
400 "comment" => "construct Shl: Shl(a, b) = a << b",
401 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
402 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
403 "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */',
404 "outs" => [ "res", "M" ],
408 "cmp_attr" => " return 1;\n",
409 "comment" => "construct lowered Shl: Shl(a, b) = a << b",
415 "comment" => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
416 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
417 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r5" ] },
420 if (get_ia32_immop_type(n) == ia32_ImmNone) {
421 if (get_ia32_op_type(n) == ia32_AddrModeD) {
422 4. shld %ia32_emit_am, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
425 4. shld %S3, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
429 if (get_ia32_op_type(n) == ia32_AddrModeD) {
430 4. shld %ia32_emit_am, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
433 4. shld %S3, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
437 "outs" => [ "res", "M" ],
441 "cmp_attr" => " return 1;\n",
442 "comment" => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
448 "comment" => "construct Shr: Shr(a, b) = a >> b",
449 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
450 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
451 "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */',
452 "outs" => [ "res", "M" ],
456 "cmp_attr" => " return 1;\n",
457 "comment" => "construct lowered Shr: Shr(a, b) = a << b",
463 "comment" => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
464 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
465 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r5" ] },
468 if (get_ia32_immop_type(n) == ia32_ImmNone) {
469 if (get_ia32_op_type(n) == ia32_AddrModeD) {
470 4. shrd %ia32_emit_am, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
473 4. shrd %S3, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
477 if (get_ia32_op_type(n) == ia32_AddrModeD) {
478 4. shrd %ia32_emit_am, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
481 4. shrd %S3, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
485 "outs" => [ "res", "M" ],
489 "cmp_attr" => " return 1;\n",
490 "comment" => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
496 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
497 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
498 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
499 "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */',
500 "outs" => [ "res", "M" ],
504 "cmp_attr" => " return 1;\n",
505 "comment" => "construct lowered Shrs: Shrs(a, b) = a << b",
511 "comment" => "construct RotR: RotR(a, b) = a ROTR b",
512 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
513 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
514 "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */',
515 "outs" => [ "res", "M" ],
520 "comment" => "construct RotL: RotL(a, b) = a ROTL b",
521 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
522 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
523 "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */',
524 "outs" => [ "res", "M" ],
531 "comment" => "construct Minus: Minus(a) = -a",
532 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
533 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
534 "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */',
535 "outs" => [ "res", "M" ],
539 "cmp_attr" => " return 1;\n",
540 "comment" => "construct lowered Minus: Minus(a) = -a",
546 "comment" => "construct Increment: Inc(a) = a++",
547 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
548 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
549 "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */',
550 "outs" => [ "res", "M" ],
555 "comment" => "construct Decrement: Dec(a) = a--",
556 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
557 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
558 "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */',
559 "outs" => [ "res", "M" ],
564 "comment" => "construct Not: Not(a) = !a",
565 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
566 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
567 "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */',
568 "outs" => [ "res", "M" ],
574 "op_flags" => "L|X|Y",
575 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
576 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
577 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
578 "outs" => [ "false", "true" ],
582 "op_flags" => "L|X|Y",
583 "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
584 "reg_req" => { "in" => [ "gp", "gp" ] },
585 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
586 "outs" => [ "false", "true" ],
590 "op_flags" => "L|X|Y",
591 "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
592 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
593 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
594 "outs" => [ "false", "true" ],
598 "op_flags" => "L|X|Y",
599 "comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
600 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
601 "reg_req" => { "in" => [ "gp", "gp" ] },
605 "op_flags" => "L|X|Y",
606 "comment" => "construct switch",
607 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
608 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
614 "comment" => "represents an integer constant",
615 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
616 "reg_req" => { "in" => [ "none" ], "out" => [ "gp" ] },
621 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
622 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
623 "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */',
624 "outs" => [ "EAX", "EDX" ],
631 "state" => "exc_pinned",
632 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
633 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
634 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
636 ' if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) {
637 4. mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
640 4. mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
643 "outs" => [ "res", "M" ],
648 "cmp_attr" => " return 1;\n",
649 "comment" => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg",
650 "outs" => [ "res", "M" ],
656 "cmp_attr" => " return 1;\n",
657 "state" => "exc_pinned",
658 "comment" => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val",
665 "state" => "exc_pinned",
666 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
667 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
668 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
669 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
675 "state" => "exc_pinned",
676 "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
677 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
678 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
679 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
685 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
686 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
687 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
688 "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */'
692 "comment" => "push a gp register on the stack",
693 "reg_req" => { "in" => [ "esp", "gp", "none" ], "out" => [ "esp" ] },
695 if (get_ia32_id_cnst(n)) {
696 if (get_ia32_immop_type(n) == ia32_ImmConst) {
697 4. push %C /* Push const on stack */
699 4. push OFFSET FLAT:%C /* Push symconst on stack */
702 else if (get_ia32_op_type(n) == ia32_Normal) {
703 2. push %S2 /* Push(%A2) */
706 2. push %ia32_emit_am /* Push memory to stack */
709 "outs" => [ "stack", "M" ],
713 "comment" => "pop a gp register from the stack",
714 "reg_req" => { "in" => [ "esp", "none" ], "out" => [ "gp", "esp" ] },
716 if (get_ia32_op_type(n) == ia32_Normal) {
717 2. pop %D1 /* Pop from stack into %D1 */
720 2. pop %ia32_emit_am /* Pop from stack into memory */
723 "outs" => [ "res", "stack", "M" ],
727 "comment" => "create stack frame",
728 "reg_req" => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] },
729 "emit" => '. enter /* Enter */',
730 "outs" => [ "frame", "stack", "M" ],
734 "comment" => "destroy stack frame",
735 "reg_req" => { "in" => [ "esp", "ebp" ], "out" => [ "ebp", "esp" ] },
736 "emit" => '. leave /* Leave */',
737 "outs" => [ "frame", "stack", "M" ],
742 "comment" => "allocate space on stack",
743 "reg_req" => { "in" => [ "esp", "gp" ], "out" => [ "esp", "none" ] },
744 "outs" => [ "stack", "M" ],
747 #-----------------------------------------------------------------------------#
748 # _____ _____ ______ __ _ _ _ #
749 # / ____/ ____| ____| / _| | | | | | #
750 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
751 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
752 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
753 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
754 #-----------------------------------------------------------------------------#
756 # commutative operations
760 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
761 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
762 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
763 "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */',
764 "outs" => [ "res", "M" ],
769 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
770 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
771 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
772 "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */',
773 "outs" => [ "res", "M" ],
778 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
779 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
780 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
781 "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */',
782 "outs" => [ "res", "M" ],
787 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
788 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
789 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
790 "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */',
791 "outs" => [ "res", "M" ],
796 "comment" => "construct SSE And: And(a, b) = a AND b",
797 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
798 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
799 "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */',
800 "outs" => [ "res", "M" ],
805 "comment" => "construct SSE Or: Or(a, b) = a OR b",
806 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
807 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
808 "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */',
809 "outs" => [ "res", "M" ],
814 "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
815 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
816 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
817 "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */',
818 "outs" => [ "res", "M" ],
821 # not commutative operations
825 "comment" => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
826 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
827 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
828 "emit" => '. andnp%M %ia32_emit_binop /* SSE AndNot(%A3, %A4) -> %D1 */',
829 "outs" => [ "res", "M" ],
834 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
835 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
836 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
837 "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */',
838 "outs" => [ "res", "M" ],
843 "comment" => "construct SSE Div: Div(a, b) = a / b",
844 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
845 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
846 "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */',
847 "outs" => [ "res", "M" ],
854 "comment" => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
855 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
856 "outs" => [ "res", "M" ],
860 "op_flags" => "L|X|Y",
861 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
862 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
863 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
864 "outs" => [ "false", "true" ],
870 "comment" => "represents a SSE constant",
871 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
872 "reg_req" => { "in" => [ "none" ], "out" => [ "xmm" ] },
873 "emit" => '. movs%M %D1, %C /* Load fConst into register */',
880 "state" => "exc_pinned",
881 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
882 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
883 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm" ] },
884 "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */',
885 "outs" => [ "res", "M" ],
890 "state" => "exc_pinned",
891 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
892 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
893 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
894 "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */',
900 "state" => "exc_pinned",
901 "comment" => "construct Store without index: Store(ptr, val, mem) = ST ptr,val",
902 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
903 "reg_req" => { "in" => [ "gp", "xmm", "none" ] },
904 "emit" => '. movs%M %ia32_emit_am, %S2 /* store XMM0 onto stack */',
910 "comment" => "construct: transfer a value from x87 FPU into a SSE register",
911 "cmp_attr" => " return 1;\n",
917 "comment" => "construct: transfer a value from SSE register to x87 FPU",
918 "cmp_attr" => " return 1;\n",
925 "state" => "exc_pinned",
926 "comment" => "store ST0 onto stack",
927 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
928 "reg_req" => { "in" => [ "gp", "none" ] },
929 "emit" => '. fstp %ia32_emit_am /* store ST0 onto stack */',
936 "state" => "exc_pinned",
937 "comment" => "load ST0 from stack",
938 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
939 "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "st0", "none" ] },
940 "emit" => '. fld %ia32_emit_am /* load ST0 from stack */',
941 "outs" => [ "res", "M" ],
949 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
950 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "edi", "esi", "ecx", "none" ] },
951 "outs" => [ "DST", "SRC", "CNT", "M" ],
957 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
958 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
959 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "edi", "esi", "none" ] },
960 "outs" => [ "DST", "SRC", "M" ],
966 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
967 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
968 "comment" => "construct Conv Int -> Int",
969 "outs" => [ "res", "M" ],
973 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
974 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
975 "comment" => "construct Conv Int -> Int",
976 "outs" => [ "res", "M" ],
980 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
981 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
982 "comment" => "construct Conv Int -> Floating Point",
983 "outs" => [ "res", "M" ],
987 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
988 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
989 "comment" => "construct Conv Floating Point -> Int",
990 "outs" => [ "res", "M" ],
994 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
995 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
996 "comment" => "construct Conv Floating Point -> Floating Point",
997 "outs" => [ "res", "M" ],
1002 "comment" => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
1003 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "in_r4" ] }
1008 "comment" => "check if Psi condition tree evaluates to true and move result accordingly",
1009 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r3" ] }
1014 "comment" => "construct Conditional Move: SSE Compare + int CMov ",
1015 "reg_req" => { "in" => [ "xmm", "xmm", "gp", "gp" ], "out" => [ "in_r4" ] }
1020 "comment" => "construct Conditional Move: x87 Compare + int CMov",
1021 "reg_req" => { "in" => [ "vfp", "vfp", "gp", "gp" ], "out" => [ "in_r4" ] }
1026 "comment" => "construct Set: Set(sel) == sel ? 1 : 0",
1027 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1028 "outs" => [ "res", "M" ],
1033 "comment" => "check if Psi condition tree evaluates to true and set result accordingly",
1034 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax ebx ecx edx" ] },
1039 "comment" => "construct Set: SSE Compare + int Set",
1040 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1041 "outs" => [ "res", "M" ],
1046 "comment" => "construct Set: x87 Compare + int Set",
1047 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1048 "outs" => [ "res", "M" ],
1053 "comment" => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
1054 "reg_req" => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] }
1057 #----------------------------------------------------------#
1059 # (_) | | | | / _| | | | #
1060 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
1061 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
1062 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
1063 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
1065 # _ __ ___ __| | ___ ___ #
1066 # | '_ \ / _ \ / _` |/ _ \/ __| #
1067 # | | | | (_) | (_| | __/\__ \ #
1068 # |_| |_|\___/ \__,_|\___||___/ #
1069 #----------------------------------------------------------#
1073 "comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
1074 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1075 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1076 "outs" => [ "res", "M" ],
1081 "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1082 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1083 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1084 "outs" => [ "res", "M" ],
1089 "cmp_attr" => " return 1;\n",
1090 "comment" => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1096 "comment" => "virtual fp Sub: Sub(a, b) = a - b",
1097 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1098 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1099 "outs" => [ "res", "M" ],
1103 "cmp_attr" => " return 1;\n",
1104 "comment" => "lowered virtual fp Sub: Sub(a, b) = a - b",
1109 "comment" => "virtual fp Div: Div(a, b) = a / b",
1110 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1111 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1112 "outs" => [ "res", "M" ],
1116 "cmp_attr" => " return 1;\n",
1117 "comment" => "lowered virtual fp Div: Div(a, b) = a / b",
1123 "comment" => "virtual fp Abs: Abs(a) = |a|",
1124 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1129 "comment" => "virtual fp Chs: Chs(a) = -a",
1130 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1135 "comment" => "virtual fp Sin: Sin(a) = sin(a)",
1136 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1141 "comment" => "virtual fp Cos: Cos(a) = cos(a)",
1142 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1147 "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
1148 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1151 # virtual Load and Store
1154 "op_flags" => "L|F",
1155 "state" => "exc_pinned",
1156 "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
1157 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1158 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1159 "outs" => [ "res", "M" ],
1163 "op_flags" => "L|F",
1164 "state" => "exc_pinned",
1165 "comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
1166 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1167 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1174 "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1175 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1176 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1177 "outs" => [ "res", "M" ],
1181 "cmp_attr" => " return 1;\n",
1182 "comment" => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1183 "outs" => [ "res", "M" ],
1188 "comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1189 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1190 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1195 "cmp_attr" => " return 1;\n",
1196 "comment" => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1206 "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg",
1207 "reg_req" => { "out" => [ "vfp" ] },
1212 "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg",
1213 "reg_req" => { "out" => [ "vfp" ] },
1218 "comment" => "virtual fp Load pi: Ld pi -> reg",
1219 "reg_req" => { "out" => [ "vfp" ] },
1224 "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg",
1225 "reg_req" => { "out" => [ "vfp" ] },
1230 "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg",
1231 "reg_req" => { "out" => [ "vfp" ] },
1236 "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg",
1237 "reg_req" => { "out" => [ "vfp" ] },
1242 "comment" => "virtual fp Load ld e: Ld ld e -> reg",
1243 "reg_req" => { "out" => [ "vfp" ] },
1249 "init_attr" => " set_ia32_ls_mode(res, mode);",
1250 "comment" => "represents a virtual floating point constant",
1251 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1252 "reg_req" => { "in" => [ "none" ], "out" => [ "vfp" ] },
1258 "op_flags" => "L|X|Y",
1259 "comment" => "represents a virtual floating point compare",
1260 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1261 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] },
1262 "outs" => [ "false", "true", "temp_reg_eax" ],
1265 #------------------------------------------------------------------------#
1266 # ___ _____ __ _ _ _ #
1267 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1268 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1269 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1270 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1271 #------------------------------------------------------------------------#
1275 "rd_constructor" => "NONE",
1276 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1278 "emit" => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */',
1283 "rd_constructor" => "NONE",
1284 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1286 "emit" => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */',
1291 "rd_constructor" => "NONE",
1292 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1294 "emit" => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */',
1299 "rd_constructor" => "NONE",
1300 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1302 "emit" => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */',,
1307 "rd_constructor" => "NONE",
1308 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1310 "emit" => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */',
1315 "rd_constructor" => "NONE",
1316 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1318 "emit" => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */',
1323 "rd_constructor" => "NONE",
1325 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1327 "emit" => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */',
1332 "rd_constructor" => "NONE",
1334 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1336 "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */',
1341 "rd_constructor" => "NONE",
1342 "comment" => "x87 fp Div: Div(a, b) = a / b",
1344 "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */',
1349 "rd_constructor" => "NONE",
1350 "comment" => "x87 fp Div: Div(a, b) = a / b",
1352 "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */',
1357 "rd_constructor" => "NONE",
1358 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1360 "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */',
1365 "rd_constructor" => "NONE",
1366 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1368 "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */',
1373 "rd_constructor" => "NONE",
1374 "comment" => "x87 fp Abs: Abs(a) = |a|",
1376 "emit" => '. fabs /* x87 fabs(%S1) -> %D1 */',
1381 "rd_constructor" => "NONE",
1382 "comment" => "x87 fp Chs: Chs(a) = -a",
1384 "emit" => '. fchs /* x87 fchs(%S1) -> %D1 */',
1389 "rd_constructor" => "NONE",
1390 "comment" => "x87 fp Sin: Sin(a) = sin(a)",
1392 "emit" => '. fsin /* x87 sin(%S1) -> %D1 */',
1397 "rd_constructor" => "NONE",
1398 "comment" => "x87 fp Cos: Cos(a) = cos(a)",
1400 "emit" => '. fcos /* x87 cos(%S1) -> %D1 */',
1405 "rd_constructor" => "NONE",
1406 "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1408 "emit" => '. fsqrt $ /* x87 sqrt(%S1) -> %D1 */',
1411 # x87 Load and Store
1414 "rd_constructor" => "NONE",
1415 "op_flags" => "R|L|F",
1416 "state" => "exc_pinned",
1417 "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1419 "emit" => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */',
1423 "rd_constructor" => "NONE",
1424 "op_flags" => "R|L|F",
1425 "state" => "exc_pinned",
1426 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1428 "emit" => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */',
1432 "rd_constructor" => "NONE",
1433 "op_flags" => "R|L|F",
1434 "state" => "exc_pinned",
1435 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1437 "emit" => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */',
1444 "rd_constructor" => "NONE",
1445 "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1447 "emit" => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */',
1452 "rd_constructor" => "NONE",
1453 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1455 "emit" => '. fist %ia32_emit_am /* integer Store(%A3) -> (%A1) */',
1460 "rd_constructor" => "NONE",
1461 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1463 "emit" => '. fistp %ia32_emit_am /* integer Store(%A3) -> (%A1) and pop */',
1471 "rd_constructor" => "NONE",
1472 "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
1474 "emit" => '. fldz /* x87 0.0 -> %D1 */',
1480 "rd_constructor" => "NONE",
1481 "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
1483 "emit" => '. fld1 /* x87 1.0 -> %D1 */',
1489 "rd_constructor" => "NONE",
1490 "comment" => "x87 fp Load pi: Ld pi -> reg",
1492 "emit" => '. fldpi /* x87 pi -> %D1 */',
1498 "rd_constructor" => "NONE",
1499 "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
1501 "emit" => '. fldln2 /* x87 ln(2) -> %D1 */',
1507 "rd_constructor" => "NONE",
1508 "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
1510 "emit" => '. fldlg2 /* x87 log(2) -> %D1 */',
1516 "rd_constructor" => "NONE",
1517 "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
1519 "emit" => '. fldll2t /* x87 ld(10) -> %D1 */',
1525 "rd_constructor" => "NONE",
1526 "comment" => "x87 fp Load ld e: Ld ld e -> reg",
1528 "emit" => '. fldl2e /* x87 ld(e) -> %D1 */',
1532 "op_flags" => "R|c",
1534 "rd_constructor" => "NONE",
1535 "comment" => "represents a x87 constant",
1536 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1537 "reg_req" => { "out" => [ "st" ] },
1538 "emit" => '. fld %ia32_emit_adr /* Load fConst into register -> %D1 */',
1542 # Note that it is NEVER allowed to do CSE on these nodes
1545 "op_flags" => "R|K",
1546 "comment" => "x87 stack exchange",
1547 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1548 "cmp_attr" => " return 1;\n",
1549 "emit" => '. fxch %X1 /* x87 swap %X1, %X3 */',
1554 "comment" => "x87 stack push",
1555 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1556 "cmp_attr" => " return 1;\n",
1557 "emit" => '. fld %X1 /* x87 push %X1 */',
1561 "op_flags" => "R|K",
1562 "comment" => "x87 stack pop",
1563 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1564 "cmp_attr" => " return 1;\n",
1565 "emit" => '. fstp %X1 /* x87 pop %X1 */',
1571 "op_flags" => "L|X|Y",
1572 "comment" => "floating point compare",
1573 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1578 "op_flags" => "L|X|Y",
1579 "comment" => "floating point compare and pop",
1580 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1585 "op_flags" => "L|X|Y",
1586 "comment" => "floating point compare and pop twice",
1587 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1592 "op_flags" => "L|X|Y",
1593 "comment" => "floating point compare reverse",
1594 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1599 "op_flags" => "L|X|Y",
1600 "comment" => "floating point compare reverse and pop",
1601 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1606 "op_flags" => "L|X|Y",
1607 "comment" => "floating point compare reverse and pop twice",
1608 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",