3 # This is the specification for the ia32 assembler Firm-operations
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
8 # this string marks the beginning of a comment in emit
9 $comment_string = "/*";
11 # the number of additional opcodes you want to register
12 #$additional_opcodes = 0;
14 # The node description is done as a perl hash initializer with the
15 # following structure:
20 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
21 # "irn_flags" => "R|N|I"
22 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
23 # "state" => "floats|pinned|mem_pinned|exc_pinned",
25 # { "type" => "type 1", "name" => "name 1" },
26 # { "type" => "type 2", "name" => "name 2" },
29 # "comment" => "any comment for constructor",
30 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
31 # "cmp_attr" => "c source code for comparing node attributes",
32 # "emit" => "emit code with templates",
33 # "attr" => "attitional attribute arguments for constructor"
34 # "init_attr" => "emit attribute initialization template"
35 # "rd_constructor" => "c source code which constructs an ir_node"
38 # ... # (all nodes you need to describe)
40 # ); # close the %nodes initializer
42 # op_flags: flags for the operation, OPTIONAL (default is "N")
43 # the op_flags correspond to the firm irop_flags:
46 # C irop_flag_commutative
47 # X irop_flag_cfopcode
48 # I irop_flag_ip_cfopcode
51 # H irop_flag_highlevel
52 # c irop_flag_constlike
55 # irn_flags: special node flags, OPTIONAL (default is 0)
56 # following irn_flags are supported:
59 # I ignore for register allocation
61 # state: state of the operation, OPTIONAL (default is "floats")
63 # arity: arity of the operation, MUST NOT BE OMITTED
65 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
66 # are always the first 3 arguments and are always autmatically
68 # If this key is missing the following arguments will be created:
69 # for i = 1 .. arity: ir_node *op_i
72 # outs: if a node defines more than one output, the names of the projections
73 # nodes having outs having automatically the mode mode_T
75 # comment: OPTIONAL comment for the node constructor
77 # rd_constructor: for every operation there will be a
78 # new_rd_<arch>_<op-name> function with the arguments from above
79 # which creates the ir_node corresponding to the defined operation
80 # you can either put the complete source code of this function here
82 # This key is OPTIONAL. If omitted, the following constructor will
84 # if (!op_<arch>_<op-name>) assert(0);
88 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
91 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
95 # 1 - caller save (register must be saved by the caller of a function)
96 # 2 - callee save (register must be saved by the called function)
97 # 4 - ignore (do not assign this register)
98 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
101 { "name" => "eax", "type" => 1 },
102 { "name" => "edx", "type" => 1 },
103 { "name" => "ebx", "type" => 2 },
104 { "name" => "ecx", "type" => 1 },
105 { "name" => "esi", "type" => 2 },
106 { "name" => "edi", "type" => 2 },
107 # { "name" => "r11", "type" => 1 },
108 # { "name" => "r12", "type" => 1 },
109 # { "name" => "r13", "type" => 1 },
110 # { "name" => "r14", "type" => 1 },
111 # { "name" => "r15", "type" => 1 },
112 # { "name" => "r16", "type" => 1 },
113 # { "name" => "r17", "type" => 1 },
114 # { "name" => "r18", "type" => 1 },
115 # { "name" => "r19", "type" => 1 },
116 # { "name" => "r20", "type" => 1 },
117 # { "name" => "r21", "type" => 1 },
118 # { "name" => "r22", "type" => 1 },
119 # { "name" => "r23", "type" => 1 },
120 # { "name" => "r24", "type" => 1 },
121 # { "name" => "r25", "type" => 1 },
122 # { "name" => "r26", "type" => 1 },
123 # { "name" => "r27", "type" => 1 },
124 # { "name" => "r28", "type" => 1 },
125 # { "name" => "r29", "type" => 1 },
126 # { "name" => "r30", "type" => 1 },
127 # { "name" => "r31", "type" => 1 },
128 # { "name" => "r32", "type" => 1 },
129 { "name" => "ebp", "type" => 2 },
130 { "name" => "esp", "type" => 4 },
131 { "name" => "gp_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
132 { "name" => "gp_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
133 { "mode" => "mode_P" }
136 { "name" => "xmm0", "type" => 1 },
137 { "name" => "xmm1", "type" => 1 },
138 { "name" => "xmm2", "type" => 1 },
139 { "name" => "xmm3", "type" => 1 },
140 { "name" => "xmm4", "type" => 1 },
141 { "name" => "xmm5", "type" => 1 },
142 { "name" => "xmm6", "type" => 1 },
143 { "name" => "xmm7", "type" => 1 },
144 { "name" => "xmm_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
145 { "name" => "xmm_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
146 { "mode" => "mode_D" }
149 { "name" => "vf0", "type" => 1 },
150 { "name" => "vf1", "type" => 1 },
151 { "name" => "vf2", "type" => 1 },
152 { "name" => "vf3", "type" => 1 },
153 { "name" => "vf4", "type" => 1 },
154 { "name" => "vf5", "type" => 1 },
155 { "name" => "vf6", "type" => 1 },
156 { "name" => "vf7", "type" => 1 },
157 { "name" => "vfp_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
158 { "name" => "vfp_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
159 { "mode" => "mode_E" }
162 { "name" => "st0", "type" => 1 },
163 { "name" => "st1", "type" => 1 },
164 { "name" => "st2", "type" => 1 },
165 { "name" => "st3", "type" => 1 },
166 { "name" => "st4", "type" => 1 },
167 { "name" => "st5", "type" => 1 },
168 { "name" => "st6", "type" => 1 },
169 { "name" => "st7", "type" => 1 },
170 { "mode" => "mode_E" }
174 #--------------------------------------------------#
177 # _ __ _____ __ _ _ __ ___ _ __ ___ #
178 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
179 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
180 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
183 #--------------------------------------------------#
190 #-----------------------------------------------------------------#
193 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
194 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
195 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
196 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
199 #-----------------------------------------------------------------#
201 # commutative operations
204 # All nodes supporting Addressmode have 5 INs:
205 # 1 - base r1 == NoReg in case of no AM or no base
206 # 2 - index r2 == NoReg in case of no AM or no index
207 # 3 - op1 r3 == always present
208 # 4 - op2 r4 == NoReg in case of immediate operation
209 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
213 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
214 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
215 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
216 "emit" => '. add %ia32_emit_binop /* Add(%A1, %A2) -> %D1 */',
217 "outs" => [ "res", "M" ],
222 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
223 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
224 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
225 "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */',
226 "outs" => [ "res", "M" ],
229 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
231 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
232 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
233 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r3", "edx in_r4" ] },
234 "emit" => '. imul %ia32_emit_binop /* Mulh(%A1, %A2) -> %D1 */',
235 "outs" => [ "EAX", "EDX", "M" ],
240 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
241 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
242 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
243 "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */',
244 "outs" => [ "res", "M" ],
249 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
250 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
251 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
252 "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */',
253 "outs" => [ "res", "M" ],
258 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
259 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
260 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
261 "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */',
262 "outs" => [ "res", "M" ],
267 "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
268 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
270 '2. cmp %S1, %S2 /* prepare Max (%S1 - %S2), (%A1, %A2) */
271 if (mode_is_signed(get_irn_mode(n))) {
272 4. cmovl %D1, %S2 /* %S1 is less %S2 */
275 4. cmovb %D1, %S2 /* %S1 is below %S2 */
282 "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
283 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
285 '2. cmp %S1, %S2 /* prepare Min (%S1 - %S2), (%A1, %A2) */
286 if (mode_is_signed(get_irn_mode(n))) {
287 2. cmovg %D1, %S2 /* %S1 is greater %S2 */
290 2. cmova %D1, %S2, %D1 /* %S1 is above %S2 */
295 # not commutative operations
299 "comment" => "construct Sub: Sub(a, b) = a - b",
300 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
301 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
302 "emit" => '. sub %ia32_emit_binop /* Sub(%A1, %A2) -> %D1 */',
303 "outs" => [ "res", "M" ],
308 "state" => "exc_pinned",
309 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "eax in_r1", "edx in_r3" ] },
310 "attr" => "ia32_op_flavour_t dm_flav",
311 "init_attr" => " attr->data.op_flav = dm_flav;",
312 "cmp_attr" => " return attr_a->data.op_flav != attr_b->data.op_flav;\n",
314 ' if (mode_is_signed(get_irn_mode(n))) {
315 4. idiv %S2 /* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
318 4. div %S2 /* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
321 "outs" => [ "div_res", "mod_res", "M" ],
326 "comment" => "construct Shl: Shl(a, b) = a << b",
327 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
328 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
329 "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */',
330 "outs" => [ "res", "M" ],
335 "comment" => "construct Shr: Shr(a, b) = a >> b",
336 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
337 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
338 "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */',
339 "outs" => [ "res", "M" ],
344 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
345 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
346 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
347 "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */',
348 "outs" => [ "res", "M" ],
353 "comment" => "construct RotR: RotR(a, b) = a ROTR b",
354 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
355 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
356 "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */',
357 "outs" => [ "res", "M" ],
362 "comment" => "construct RotL: RotL(a, b) = a ROTL b",
363 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
364 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
365 "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */',
366 "outs" => [ "res", "M" ],
373 "comment" => "construct Minus: Minus(a) = -a",
374 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
375 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
376 "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */',
377 "outs" => [ "res", "M" ],
382 "comment" => "construct Increment: Inc(a) = a++",
383 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
384 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
385 "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */',
386 "outs" => [ "res", "M" ],
391 "comment" => "construct Decrement: Dec(a) = a--",
392 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
393 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
394 "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */',
395 "outs" => [ "res", "M" ],
400 "comment" => "construct Not: Not(a) = !a",
401 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
402 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
403 "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */',
404 "outs" => [ "res", "M" ],
410 "op_flags" => "L|X|Y",
411 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
412 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
413 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
414 "outs" => [ "false", "true" ],
418 "op_flags" => "L|X|Y",
419 "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
420 "reg_req" => { "in" => [ "gp", "gp" ] },
421 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
422 "outs" => [ "false", "true" ],
426 "op_flags" => "L|X|Y",
427 "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
428 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
429 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
430 "outs" => [ "false", "true" ],
434 "op_flags" => "L|X|Y",
435 "comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
436 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
437 "reg_req" => { "in" => [ "gp", "gp" ] },
441 "op_flags" => "L|X|Y",
442 "comment" => "construct switch",
443 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
444 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
450 "comment" => "represents an integer constant",
451 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
452 "reg_req" => { "in" => [ "none" ], "out" => [ "gp" ] },
457 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
458 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
459 "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */',
460 "outs" => [ "EAX", "EDX" ],
468 "state" => "exc_pinned",
469 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
470 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
471 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
473 ' if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) {
474 4. mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
477 4. mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
480 "outs" => [ "res", "M" ],
485 "state" => "exc_pinned",
486 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
487 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
488 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
489 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
495 "state" => "exc_pinned",
496 "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
497 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
498 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
499 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
505 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
506 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
507 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
508 "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */'
512 "comment" => "push a gp register on the stack",
513 "reg_req" => { "in" => [ "esp", "gp", "none" ], "out" => [ "esp" ] },
515 if (get_ia32_id_cnst(n)) {
516 if (get_ia32_immop_type(n) == ia32_ImmConst) {
517 . push %C /* Push(%A2) */
519 . push OFFSET FLAT:%C /* Push(%A2) */
523 . push %S2 /* Push(%A2) */
526 "outs" => [ "stack", "M" ],
530 "comment" => "pop a gp register from the stack",
531 "reg_req" => { "in" => [ "esp", "none" ], "out" => [ "gp", "esp" ] },
532 "emit" => '. pop %D1 /* Pop -> %D1 */',
533 "outs" => [ "res", "stack", "M" ],
537 "comment" => "create stack frame",
538 "reg_req" => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] },
539 "emit" => '. enter /* Enter */',
540 "outs" => [ "frame", "stack", "M" ],
544 "comment" => "destroy stack frame",
545 "reg_req" => { "in" => [ "esp", "ebp" ], "out" => [ "ebp", "esp" ] },
546 "emit" => '. leave /* Leave */',
547 "outs" => [ "frame", "stack", "M" ],
550 #-----------------------------------------------------------------------------#
551 # _____ _____ ______ __ _ _ _ #
552 # / ____/ ____| ____| / _| | | | | | #
553 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
554 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
555 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
556 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
557 #-----------------------------------------------------------------------------#
559 # commutative operations
563 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
564 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
565 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
566 "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */',
567 "outs" => [ "res", "M" ],
572 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
573 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
574 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
575 "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */',
576 "outs" => [ "res", "M" ],
581 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
582 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
583 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
584 "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */',
585 "outs" => [ "res", "M" ],
590 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
591 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
592 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
593 "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */',
594 "outs" => [ "res", "M" ],
599 "comment" => "construct SSE And: And(a, b) = a AND b",
600 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
601 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
602 "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */',
603 "outs" => [ "res", "M" ],
608 "comment" => "construct SSE Or: Or(a, b) = a OR b",
609 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
610 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
611 "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */',
612 "outs" => [ "res", "M" ],
617 "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
618 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
619 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
620 "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */',
621 "outs" => [ "res", "M" ],
624 # not commutative operations
628 "comment" => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
629 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
630 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
631 "emit" => '. andnp%M %ia32_emit_binop /* SSE AndNot(%A3, %A4) -> %D1 */',
632 "outs" => [ "res", "M" ],
637 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
638 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
639 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
640 "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */',
641 "outs" => [ "res", "M" ],
646 "comment" => "construct SSE Div: Div(a, b) = a / b",
647 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
648 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
649 "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */',
650 "outs" => [ "res", "M" ],
657 "comment" => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
658 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
659 "outs" => [ "res", "M" ],
663 "op_flags" => "L|X|Y",
664 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
665 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
666 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
667 "outs" => [ "false", "true" ],
673 "comment" => "represents a SSE constant",
674 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
675 "reg_req" => { "in" => [ "none" ], "out" => [ "xmm" ] },
676 "emit" => '. movs%M %D1, %C /* Load fConst into register */',
684 "state" => "exc_pinned",
685 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
686 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
687 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm" ] },
688 "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */',
689 "outs" => [ "res", "M" ],
694 "state" => "exc_pinned",
695 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
696 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
697 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
698 "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */',
707 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
708 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "none" ] },
714 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
715 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
716 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "none" ] },
722 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
723 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
724 "comment" => "construct Conv Int -> Int",
725 "outs" => [ "res", "M" ],
729 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
730 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
731 "comment" => "construct Conv Int -> Int",
732 "outs" => [ "res", "M" ],
736 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
737 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
738 "comment" => "construct Conv Int -> Floating Point",
739 "outs" => [ "res", "M" ],
743 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
744 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
745 "comment" => "construct Conv Floating Point -> Int",
746 "outs" => [ "res", "M" ],
750 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
751 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
752 "comment" => "construct Conv Floating Point -> Floating Point",
753 "outs" => [ "res", "M" ],
758 "comment" => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
759 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "in_r4" ] }
764 "comment" => "construct Conditional Move: SSE Compare + int CMov ",
765 "reg_req" => { "in" => [ "xmm", "xmm", "gp", "gp" ], "out" => [ "in_r4" ] }
770 "comment" => "construct Conditional Move: x87 Compare + int CMov",
771 "reg_req" => { "in" => [ "vfp", "vfp", "gp", "gp" ], "out" => [ "in_r4" ] }
776 "comment" => "construct Set: Set(sel) == sel ? 1 : 0",
777 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
778 "outs" => [ "res", "M" ],
783 "comment" => "construct Set: SSE Compare + int Set",
784 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
785 "outs" => [ "res", "M" ],
790 "comment" => "construct Set: x87 Compare + int Set",
791 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
792 "outs" => [ "res", "M" ],
797 "comment" => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
798 "reg_req" => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] }
801 #----------------------------------------------------------#
803 # (_) | | | | / _| | | | #
804 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
805 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
806 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
807 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
809 # _ __ ___ __| | ___ ___ #
810 # | '_ \ / _ \ / _` |/ _ \/ __| #
811 # | | | | (_) | (_| | __/\__ \ #
812 # |_| |_|\___/ \__,_|\___||___/ #
813 #----------------------------------------------------------#
817 "comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
818 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
819 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
820 "outs" => [ "res", "M" ],
825 "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a + b",
826 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
827 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
828 "outs" => [ "res", "M" ],
833 "comment" => "virtual fp Sub: Sub(a, b) = a - b",
834 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
835 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
836 "outs" => [ "res", "M" ],
840 "comment" => "virtual fp Div: Div(a, b) = a / b",
841 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
842 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
843 "outs" => [ "res", "M" ],
848 "comment" => "virtual fp Abs: Abs(a) = |a|",
849 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
854 "comment" => "virtual fp Chs: Chs(a) = -a",
855 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
860 "comment" => "virtual fp Sin: Sin(a) = sin(a)",
861 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
866 "comment" => "virtual fp Cos: Cos(a) = cos(a)",
867 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
872 "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
873 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
876 # virtual Load and Store
881 "state" => "exc_pinned",
882 "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
883 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
884 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
885 "outs" => [ "res", "M" ],
890 "state" => "exc_pinned",
891 "comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
892 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
893 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
901 "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
902 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
903 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
904 "outs" => [ "res", "M" ],
908 "comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
909 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
910 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
918 "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg",
919 "reg_req" => { "out" => [ "vfp" ] },
924 "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg",
925 "reg_req" => { "out" => [ "vfp" ] },
930 "comment" => "virtual fp Load pi: Ld pi -> reg",
931 "reg_req" => { "out" => [ "vfp" ] },
936 "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg",
937 "reg_req" => { "out" => [ "vfp" ] },
942 "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg",
943 "reg_req" => { "out" => [ "vfp" ] },
948 "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg",
949 "reg_req" => { "out" => [ "vfp" ] },
954 "comment" => "virtual fp Load ld e: Ld ld e -> reg",
955 "reg_req" => { "out" => [ "vfp" ] },
961 "init_attr" => " set_ia32_ls_mode(res, mode);",
962 "comment" => "represents a virtual floating point constant",
963 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
964 "reg_req" => { "in" => [ "none" ], "out" => [ "vfp" ] },
970 "op_flags" => "L|X|Y",
971 "comment" => "represents a virtual floating point compare",
972 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
973 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] },
974 "outs" => [ "false", "true", "temp_reg_eax" ],
977 #------------------------------------------------------------------------#
978 # ___ _____ __ _ _ _ #
979 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
980 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
981 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
982 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
983 #------------------------------------------------------------------------#
987 "rd_constructor" => "NONE",
988 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
990 "emit" => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */',
995 "rd_constructor" => "NONE",
996 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
998 "emit" => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */',
1003 "rd_constructor" => "NONE",
1004 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1006 "emit" => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */',
1011 "rd_constructor" => "NONE",
1012 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1014 "emit" => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */',,
1019 "rd_constructor" => "NONE",
1020 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1022 "emit" => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */',
1027 "rd_constructor" => "NONE",
1028 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1030 "emit" => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */',
1035 "rd_constructor" => "NONE",
1037 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1039 "emit" => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */',
1044 "rd_constructor" => "NONE",
1046 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1048 "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */',
1053 "rd_constructor" => "NONE",
1054 "comment" => "x87 fp Div: Div(a, b) = a / b",
1056 "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */',
1061 "rd_constructor" => "NONE",
1062 "comment" => "x87 fp Div: Div(a, b) = a / b",
1064 "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */',
1069 "rd_constructor" => "NONE",
1070 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1072 "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */',
1077 "rd_constructor" => "NONE",
1078 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1080 "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */',
1085 "rd_constructor" => "NONE",
1086 "comment" => "x87 fp Abs: Abs(a) = |a|",
1088 "emit" => '. fabs /* x87 fabs(%S1) -> %D1 */',
1093 "rd_constructor" => "NONE",
1094 "comment" => "x87 fp Chs: Chs(a) = -a",
1096 "emit" => '. fchs /* x87 fchs(%S1) -> %D1 */',
1101 "rd_constructor" => "NONE",
1102 "comment" => "x87 fp Sin: Sin(a) = sin(a)",
1104 "emit" => '. fsin /* x87 sin(%S1) -> %D1 */',
1109 "rd_constructor" => "NONE",
1110 "comment" => "x87 fp Cos: Cos(a) = cos(a)",
1112 "emit" => '. fcos /* x87 cos(%S1) -> %D1 */',
1117 "rd_constructor" => "NONE",
1118 "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1120 "emit" => '. fsqrt $ /* x87 sqrt(%S1) -> %D1 */',
1123 # x87 Load and Store
1126 "rd_constructor" => "NONE",
1127 "op_flags" => "R|L|F",
1128 "state" => "exc_pinned",
1129 "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1131 "emit" => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */',
1135 "rd_constructor" => "NONE",
1136 "op_flags" => "R|L|F",
1137 "state" => "exc_pinned",
1138 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1140 "emit" => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */',
1144 "rd_constructor" => "NONE",
1145 "op_flags" => "R|L|F",
1146 "state" => "exc_pinned",
1147 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1149 "emit" => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */',
1157 "rd_constructor" => "NONE",
1158 "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1160 "emit" => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */',
1165 "rd_constructor" => "NONE",
1166 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1168 "emit" => '. fist %ia32_emit_am /* integer Store(%A3) -> (%A1) */',
1173 "rd_constructor" => "NONE",
1174 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1176 "emit" => '. fistp %ia32_emit_am /* integer Store(%A3) -> (%A1) and pop */',
1183 "rd_constructor" => "NONE",
1184 "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
1186 "emit" => '. fldz /* x87 0.0 -> %D1 */',
1191 "rd_constructor" => "NONE",
1192 "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
1194 "emit" => '. fld1 /* x87 1.0 -> %D1 */',
1199 "rd_constructor" => "NONE",
1200 "comment" => "x87 fp Load pi: Ld pi -> reg",
1202 "emit" => '. fldpi /* x87 pi -> %D1 */',
1207 "rd_constructor" => "NONE",
1208 "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
1210 "emit" => '. fldln2 /* x87 ln(2) -> %D1 */',
1215 "rd_constructor" => "NONE",
1216 "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
1218 "emit" => '. fldlg2 /* x87 log(2) -> %D1 */',
1223 "rd_constructor" => "NONE",
1224 "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
1226 "emit" => '. fldll2t /* x87 ld(10) -> %D1 */',
1231 "rd_constructor" => "NONE",
1232 "comment" => "x87 fp Load ld e: Ld ld e -> reg",
1234 "emit" => '. fldl2e /* x87 ld(e) -> %D1 */',
1238 "op_flags" => "R|c",
1240 "rd_constructor" => "NONE",
1241 "comment" => "represents a x87 constant",
1242 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1243 "reg_req" => { "out" => [ "st" ] },
1244 "emit" => '. fld %ia32_emit_adr /* Load fConst into register -> %D1 */',
1248 # Note that it is NEVER allowed to do CSE on these nodes
1251 "op_flags" => "R|K",
1252 "comment" => "x87 stack exchange",
1253 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1254 "cmp_attr" => " return 1;\n",
1255 "emit" => '. fxch %X1 /* x87 swap %X1, %X3 */',
1260 "comment" => "x87 stack push",
1261 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1262 "cmp_attr" => " return 1;\n",
1263 "emit" => '. fld %X1 /* x87 push %X1 */',
1267 "op_flags" => "R|K",
1268 "comment" => "x87 stack pop",
1269 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1270 "cmp_attr" => " return 1;\n",
1271 "emit" => '. fstp %X1 /* x87 pop %X1 */',
1277 "op_flags" => "L|X|Y",
1278 "comment" => "floating point compare",
1279 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1284 "op_flags" => "L|X|Y",
1285 "comment" => "floating point compare and pop",
1286 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1291 "op_flags" => "L|X|Y",
1292 "comment" => "floating point compare and pop twice",
1293 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1298 "op_flags" => "L|X|Y",
1299 "comment" => "floating point compare reverse",
1300 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1305 "op_flags" => "L|X|Y",
1306 "comment" => "floating point compare reverse and pop",
1307 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1312 "op_flags" => "L|X|Y",
1313 "comment" => "floating point compare reverse and pop twice",
1314 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",