3 # This is the specification for the ia32 assembler Firm-operations
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
8 # this string marks the beginning of a comment in emit
9 $comment_string = "/*";
11 # the number of additional opcodes you want to register
12 $additional_opcodes = 0;
14 # The node description is done as a perl hash initializer with the
15 # following structure:
20 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
21 # "irn_flags" => "R|N|I"
22 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
23 # "state" => "floats|pinned|mem_pinned|exc_pinned",
25 # { "type" => "type 1", "name" => "name 1" },
26 # { "type" => "type 2", "name" => "name 2" },
29 # "comment" => "any comment for constructor",
30 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
31 # "cmp_attr" => "c source code for comparing node attributes",
32 # "emit" => "emit code with templates",
33 # "rd_constructor" => "c source code which constructs an ir_node"
36 # ... # (all nodes you need to describe)
38 # ); # close the %nodes initializer
40 # op_flags: flags for the operation, OPTIONAL (default is "N")
41 # the op_flags correspond to the firm irop_flags:
44 # C irop_flag_commutative
45 # X irop_flag_cfopcode
46 # I irop_flag_ip_cfopcode
49 # H irop_flag_highlevel
50 # c irop_flag_constlike
53 # irn_flags: special node flags, OPTIONAL (default is 0)
54 # following irn_flags are supported:
57 # I ignore for register allocation
59 # state: state of the operation, OPTIONAL (default is "floats")
61 # arity: arity of the operation, MUST NOT BE OMITTED
63 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
64 # are always the first 3 arguments and are always autmatically
66 # If this key is missing the following arguments will be created:
67 # for i = 1 .. arity: ir_node *op_i
70 # comment: OPTIONAL comment for the node constructor
72 # rd_constructor: for every operation there will be a
73 # new_rd_<arch>_<op-name> function with the arguments from above
74 # which creates the ir_node corresponding to the defined operation
75 # you can either put the complete source code of this function here
77 # This key is OPTIONAL. If omitted, the following constructor will
79 # if (!op_<arch>_<op-name>) assert(0);
83 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
86 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
90 # 1 - caller save (register must be saved by the caller of a function)
91 # 2 - callee save (register must be saved by the called function)
92 # 4 - ignore (do not assign this register)
93 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
96 { "name" => "eax", "type" => 1 },
97 { "name" => "edx", "type" => 1 },
98 { "name" => "ebx", "type" => 2 },
99 { "name" => "ecx", "type" => 1 },
100 { "name" => "esi", "type" => 2 },
101 { "name" => "edi", "type" => 2 },
102 { "name" => "ebp", "type" => 2 },
103 { "name" => "esp", "type" => 4 },
104 { "name" => "xxx", "type" => 6 }, # we need a dummy register for NoReg and Unknown nodes
105 { "mode" => "mode_P" }
108 { "name" => "xmm0", "type" => 1 },
109 { "name" => "xmm1", "type" => 1 },
110 { "name" => "xmm2", "type" => 1 },
111 { "name" => "xmm3", "type" => 1 },
112 { "name" => "xmm4", "type" => 1 },
113 { "name" => "xmm5", "type" => 1 },
114 { "name" => "xmm6", "type" => 1 },
115 { "name" => "xmm7", "type" => 1 },
116 { "name" => "xxxx", "type" => 6 }, # we need a dummy register for NoReg and Unknown nodes
117 { "mode" => "mode_D" }
121 #--------------------------------------------------#
124 # _ __ _____ __ _ _ __ ___ _ __ ___ #
125 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
126 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
127 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
130 #--------------------------------------------------#
134 #-----------------------------------------------------------------#
137 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
138 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
139 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
140 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
143 #-----------------------------------------------------------------#
145 # commutative operations
148 # All nodes supporting Addressmode have 5 INs:
149 # 1 - base r1 == NoReg in case of no AM or no base
150 # 2 - index r2 == NoReg in case of no AM or no index
151 # 3 - op1 r3 == always present
152 # 4 - op2 r4 == NoReg in case of immediate operation
153 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
157 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
158 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
159 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
160 "emit" => '. add %ia32_emit_binop /* Add(%A1, %A2) -> %D1 */',
165 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
166 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
167 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
168 "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */'
171 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
173 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
174 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
175 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r3", "edx in_r4" ] },
176 "emit" => '. imul %ia32_emit_unop /* Mulh(%A1, %A2) -> %D1 */'
181 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
182 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
183 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
184 "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */'
189 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
190 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
191 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
192 "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */'
197 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
198 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
199 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
200 "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */'
205 "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
206 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
208 '2. cmp %S1, %S2 /* prepare Max (%S1 - %S2), (%A1, %A2) */
209 if (mode_is_signed(get_irn_mode(n))) {
210 4. cmovl %D1, %S2 /* %S1 is less %S2 */
213 4. cmovb %D1, %S2 /* %S1 is below %S2 */
220 "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
221 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
223 '2. cmp %S1, %S2 /* prepare Min (%S1 - %S2), (%A1, %A2) */
224 if (mode_is_signed(get_irn_mode(n))) {
225 2. cmovg %D1, %S2 /* %S1 is greater %S2 */
228 2. cmova %D1, %S2, %D1 /* %S1 is above %S2 */
235 "comment" => "construct Mux: Mux(sel, a, b) == sel ? a : b",
236 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r2" ] },
238 '. cmp %S1, 0 /* compare Sel for CMov (%A2, %A3) */
239 . cmovne %D1, %S3 /* sel == true -> return %S3 */
243 # not commutative operations
247 "comment" => "construct Sub: Sub(a, b) = a - b",
248 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
249 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
250 "emit" => '. sub %ia32_emit_binop /* Sub(%A1, %A2) -> %D1 */'
255 "state" => "exc_pinned",
256 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "eax in_r1", "edx in_r3" ] },
258 ' if (mode_is_signed(get_irn_mode(n))) {
259 4. idiv %S2 /* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
262 4. div %S2 /* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
269 "comment" => "construct Shl: Shl(a, b) = a << b",
270 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
271 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
272 "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */'
277 "comment" => "construct Shr: Shr(a, b) = a >> b",
278 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
279 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
280 "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */'
285 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
286 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
287 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
288 "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */'
293 "comment" => "construct RotR: RotR(a, b) = a ROTR b",
294 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
295 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
296 "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */'
301 "comment" => "construct RotL: RotL(a, b) = a ROTL b",
302 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
303 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
304 "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */'
311 "comment" => "construct Minus: Minus(a) = -a",
312 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
313 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
314 "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */'
319 "comment" => "construct Increment: Inc(a) = a++",
320 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
321 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
322 "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */'
327 "comment" => "construct Decrement: Dec(a) = a--",
328 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
329 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
330 "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */'
335 "comment" => "construct Not: Not(a) = !a",
336 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
337 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
338 "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */'
344 "op_flags" => "L|X|Y",
345 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
346 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
347 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
351 "op_flags" => "L|X|Y",
352 "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
353 "reg_req" => { "in" => [ "gp", "gp" ] },
354 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
358 "op_flags" => "L|X|Y",
359 "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
360 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
361 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
365 "op_flags" => "L|X|Y",
366 "comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
367 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
368 "reg_req" => { "in" => [ "gp", "gp" ] },
372 "op_flags" => "L|X|Y",
373 "comment" => "construct switch",
374 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
375 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
381 "comment" => "represents an integer constant",
382 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
383 "reg_req" => { "out" => [ "gp" ] },
385 ' if (get_ia32_Immop_tarval(n) == get_tarval_null(get_irn_mode(n))) {
386 4. sub %D1, %D1 /* optimized mov 0 to register */
389 if (get_ia32_op_type(n) == ia32_SymConst) {
390 6. mov %D1, OFFSET FLAT:%C /* Move address of SymConst into register */
393 6. mov %D1, %C /* Mov Const into register */
401 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
402 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
403 "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */'
411 "state" => "exc_pinned",
412 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
413 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
414 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
416 ' if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) {
417 4. mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
420 4. mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
427 "state" => "exc_pinned",
428 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
429 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
430 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
431 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */'
436 "state" => "exc_pinned",
437 "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
438 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
439 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
440 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */'
445 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
446 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
447 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
448 "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */'
451 #--------------------------------------------------------#
454 # | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
455 # | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
456 # | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
457 # |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
458 #--------------------------------------------------------#
460 # commutative operations
464 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
465 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
466 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
467 "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */'
472 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
473 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
474 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
475 "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */'
480 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
481 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
482 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
483 "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */'
488 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
489 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
490 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
491 "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */'
496 "comment" => "construct SSE And: And(a, b) = a AND b",
497 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
498 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
499 "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */'
504 "comment" => "construct SSE Or: Or(a, b) = a OR b",
505 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
506 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
507 "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */'
512 "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
513 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
514 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
515 "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */'
518 # not commutative operations
522 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
523 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
524 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
525 "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */'
530 "comment" => "construct SSE Div: Div(a, b) = a / b",
531 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
532 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3 !in_r4" ] },
533 "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */'
539 "op_flags" => "L|X|Y",
540 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
541 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
542 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "none", "none" ] },
548 "comment" => "represents a SSE constant",
549 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
550 "reg_req" => { "out" => [ "fp" ] },
551 "emit" => '. mov%M %D1, %C /* Load fConst into register */',
559 "state" => "exc_pinned",
560 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
561 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
562 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "fp" ] },
563 "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */'
568 "state" => "exc_pinned",
569 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
570 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
571 "reg_req" => { "in" => [ "gp", "gp", "fp", "none" ] },
572 "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */'
580 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
581 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "none" ] },
587 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
588 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
589 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "none" ] },
595 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
596 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
597 "comment" => "construct Conv Int -> Int"
601 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
602 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
603 "comment" => "construct Conv Int -> Int"
607 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "fp", "none" ] },
608 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
609 "comment" => "construct Conv Int -> Floating Point"
613 "reg_req" => { "in" => [ "gp", "gp", "fp", "none" ], "out" => [ "gp", "none" ] },
614 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
615 "comment" => "construct Conv Floating Point -> Int"
619 "reg_req" => { "in" => [ "gp", "gp", "fp", "none" ], "out" => [ "fp", "none" ] },
620 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
621 "comment" => "construct Conv Floating Point -> Floating Point",