3 # This is the specification for the ia32 assembler Firm-operations
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
8 # this strings mark the beginning and the end of a comment in emit
9 $comment_string = "/*";
10 $comment_string_end = "*/";
12 # the number of additional opcodes you want to register
13 #$additional_opcodes = 0;
15 # The node description is done as a perl hash initializer with the
16 # following structure:
21 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
22 # "irn_flags" => "R|N|I|S"
23 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
24 # "state" => "floats|pinned|mem_pinned|exc_pinned",
26 # { "type" => "type 1", "name" => "name 1" },
27 # { "type" => "type 2", "name" => "name 2" },
30 # "comment" => "any comment for constructor",
31 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
32 # "cmp_attr" => "c source code for comparing node attributes",
33 # "emit" => "emit code with templates",
34 # "attr" => "attitional attribute arguments for constructor"
35 # "init_attr" => "emit attribute initialization template"
36 # "rd_constructor" => "c source code which constructs an ir_node"
37 # "latency" => "latency of this operation (can be float)"
40 # ... # (all nodes you need to describe)
42 # ); # close the %nodes initializer
44 # op_flags: flags for the operation, OPTIONAL (default is "N")
45 # the op_flags correspond to the firm irop_flags:
48 # C irop_flag_commutative
49 # X irop_flag_cfopcode
50 # I irop_flag_ip_cfopcode
53 # H irop_flag_highlevel
54 # c irop_flag_constlike
57 # irn_flags: special node flags, OPTIONAL (default is 0)
58 # following irn_flags are supported:
61 # I ignore for register allocation
62 # S modifies stack pointer
64 # state: state of the operation, OPTIONAL (default is "floats")
66 # arity: arity of the operation, MUST NOT BE OMITTED
68 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
69 # are always the first 3 arguments and are always autmatically
71 # If this key is missing the following arguments will be created:
72 # for i = 1 .. arity: ir_node *op_i
75 # outs: if a node defines more than one output, the names of the projections
76 # nodes having outs having automatically the mode mode_T
77 # One can also annotate some flags for each out, additional to irn_flags.
78 # They are separated from name with a colon ':', and concatenated by pipe '|'
79 # Only I and S are available at the moment (same meaning as in irn_flags).
80 # example: [ "frame:I", "stack:I|S", "M" ]
82 # comment: OPTIONAL comment for the node constructor
84 # rd_constructor: for every operation there will be a
85 # new_rd_<arch>_<op-name> function with the arguments from above
86 # which creates the ir_node corresponding to the defined operation
87 # you can either put the complete source code of this function here
89 # This key is OPTIONAL. If omitted, the following constructor will
91 # if (!op_<arch>_<op-name>) assert(0);
95 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
98 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
100 # latency: the latency of the operation, default is 1
104 # 0 - no special type
105 # 1 - caller save (register must be saved by the caller of a function)
106 # 2 - callee save (register must be saved by the called function)
107 # 4 - ignore (do not assign this register)
108 # 8 - emitter can choose an arbitrary register of this class
109 # 16 - the register is a virtual one
110 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
113 { "name" => "eax", "type" => 1 },
114 { "name" => "edx", "type" => 1 },
115 { "name" => "ebx", "type" => 2 },
116 { "name" => "ecx", "type" => 1 },
117 { "name" => "esi", "type" => 2 },
118 { "name" => "edi", "type" => 2 },
119 { "name" => "ebp", "type" => 2 },
120 { "name" => "esp", "type" => 4 },
121 { "name" => "gp_NOREG", "type" => 4 | 16 }, # we need a dummy register for NoReg nodes
122 { "name" => "gp_UKNWN", "type" => 4 | 8 | 16}, # we need a dummy register for Unknown nodes
123 { "mode" => "mode_Iu" }
126 { "name" => "xmm0", "type" => 1 },
127 { "name" => "xmm1", "type" => 1 },
128 { "name" => "xmm2", "type" => 1 },
129 { "name" => "xmm3", "type" => 1 },
130 { "name" => "xmm4", "type" => 1 },
131 { "name" => "xmm5", "type" => 1 },
132 { "name" => "xmm6", "type" => 1 },
133 { "name" => "xmm7", "type" => 1 },
134 { "name" => "xmm_NOREG", "type" => 4 | 16 }, # we need a dummy register for NoReg nodes
135 { "name" => "xmm_UKNWN", "type" => 4 | 8 | 16}, # we need a dummy register for Unknown nodes
136 { "mode" => "mode_D" }
139 { "name" => "vf0", "type" => 1 | 16 },
140 { "name" => "vf1", "type" => 1 | 16 },
141 { "name" => "vf2", "type" => 1 | 16 },
142 { "name" => "vf3", "type" => 1 | 16 },
143 { "name" => "vf4", "type" => 1 | 16 },
144 { "name" => "vf5", "type" => 1 | 16 },
145 { "name" => "vf6", "type" => 1 | 16 },
146 { "name" => "vf7", "type" => 1 | 16 },
147 { "name" => "vfp_NOREG", "type" => 4 | 16 }, # we need a dummy register for NoReg nodes
148 { "name" => "vfp_UKNWN", "type" => 4 | 8 | 16}, # we need a dummy register for Unknown nodes
149 { "mode" => "mode_D" }
152 { "name" => "st0", "type" => 1 },
153 { "name" => "st1", "type" => 1 },
154 { "name" => "st2", "type" => 1 },
155 { "name" => "st3", "type" => 1 },
156 { "name" => "st4", "type" => 1 },
157 { "name" => "st5", "type" => 1 },
158 { "name" => "st6", "type" => 1 },
159 { "name" => "st7", "type" => 1 },
160 { "mode" => "mode_E" }
162 "fp_cw" => [ # the floating point control word
163 { "name" => "fpcw", "type" => 0 },
164 { "mode" => "mode_Hu" },
169 "GP" => [ 1, "GP_EAX", "GP_EBX", "GP_ECX", "GP_EDX", "GP_ESI", "GP_EDI", "GP_EBP" ],
170 "SSE" => [ 1, "SSE_XMM0", "SSE_XMM1", "SSE_XMM2", "SSE_XMM3", "SSE_XMM4", "SSE_XMM5", "SSE_XMM6", "SSE_XMM7" ],
171 "VFP" => [ 1, "VFP_VF0", "VFP_VF1", "VFP_VF2", "VFP_VF3", "VFP_VF4", "VFP_VF5", "VFP_VF6", "VFP_VF7" ],
172 "BRANCH" => [ 1, "BRANCH1", "BRANCH2" ],
177 "bundels_per_cycle" => 1
180 #--------------------------------------------------#
183 # _ __ _____ __ _ _ __ ___ _ __ ___ #
184 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
185 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
186 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
189 #--------------------------------------------------#
191 $default_cmp_attr = "return ia32_compare_attr(attr_a, attr_b);";
198 #-----------------------------------------------------------------#
201 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
202 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
203 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
204 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
207 #-----------------------------------------------------------------#
209 # commutative operations
212 # All nodes supporting Addressmode have 5 INs:
213 # 1 - base r1 == NoReg in case of no AM or no base
214 # 2 - index r2 == NoReg in case of no AM or no index
215 # 3 - op1 r3 == always present
216 # 4 - op2 r4 == NoReg in case of immediate operation
217 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
221 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
222 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
223 "emit" => '. add %ia32_emit_binop /* Add(%A3, %A4) -> %D1 */',
229 "comment" => "construct Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
230 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
231 "emit" => '. adc %ia32_emit_binop /* AddC(%A3, %A4) -> %D1 */',
238 "comment" => "construct 64Bit Add: Add(a_l, a_h, b_l, b_h) = a_l + b_l; a_h + b_h + carry",
240 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
242 . mov %D1, %S1 /* mov a_l into assigned l_res register */
243 . mov %D2, %S2 /* mov a_h into assigned h_res register */
244 . add %D1, %S3 /* a_l + b_l */
245 . adc %D2, %S4 /* a_h + b_h + carry */
247 "outs" => [ "low_res", "high_res" ],
254 "cmp_attr" => "return 1;",
255 "comment" => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
261 "cmp_attr" => "return 1;",
262 "comment" => "construct lowered Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
267 # we should not rematrialize this node. It produces 2 results and has
268 # very strict constrains
269 "comment" => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
270 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx", "none" ] },
271 "emit" => '. mul %ia32_emit_unop /* Mul(%A1, %A2) -> %D1 */',
272 "outs" => [ "EAX", "EDX", "M" ],
278 # we should not rematrialize this node. It produces 2 results and has
279 # very strict constrains
281 "cmp_attr" => "return 1;",
282 "comment" => "construct lowered MulS: MulS(a, b) = MulS(b, a) = a * b",
283 "outs" => [ "EAX", "EDX", "M" ],
289 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
290 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
291 "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */',
299 "cmp_attr" => "return 1;",
300 "comment" => "construct lowered Mul: Mul(a, b) = Mul(b, a) = a * b",
304 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
306 # we should not rematrialize this node. It produces 2 results and has
307 # very strict constrains
308 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
309 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] },
310 "emit" => '. imul %ia32_emit_unop /* Mulh(%A1, %A2) -> %D1 */',
311 "outs" => [ "EAX", "EDX", "M" ],
318 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
319 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
320 "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */',
327 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
328 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
329 "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */',
336 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
337 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
338 "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */',
345 "cmp_attr" => "return 1;",
346 "comment" => "construct lowered Eor: Eor(a, b) = Eor(b, a) = a EOR b",
350 # not commutative operations
354 "comment" => "construct Sub: Sub(a, b) = a - b",
355 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
356 "emit" => '. sub %ia32_emit_binop /* Sub(%A3, %A4) -> %D1 */',
362 "comment" => "construct Sub with Carry: SubC(a, b) = a - b - carry",
363 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3 !in_r4" ] },
364 "emit" => '. sbb %ia32_emit_binop /* SubC(%A3, %A4) -> %D1 */',
371 "comment" => "construct 64Bit Sub: Sub(a_l, a_h, b_l, b_h) = a_l - b_l; a_h - b_h - borrow",
373 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
375 . mov %D1, %S1 /* mov a_l into assigned l_res register */
376 . mov %D2, %S2 /* mov a_h into assigned h_res register */
377 . sub %D1, %S3 /* a_l - b_l */
378 . sbb %D2, %S4 /* a_h - b_h - borrow */
380 "outs" => [ "low_res", "high_res" ],
386 "cmp_attr" => "return 1;",
387 "comment" => "construct lowered Sub: Sub(a, b) = a - b",
392 "cmp_attr" => "return 1;",
393 "comment" => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
399 "state" => "exc_pinned",
400 "reg_req" => { "in" => [ "eax", "gp", "edx", "none" ], "out" => [ "eax", "edx" ] },
401 "attr" => "ia32_op_flavour_t dm_flav",
402 "init_attr" => "attr->data.op_flav = dm_flav;",
403 "emit" => ". idiv %S2 /* signed IDiv(%S1, %S2) -> %D1, (%A1, %A2, %A3) */",
404 "outs" => [ "div_res", "mod_res", "M" ],
411 "state" => "exc_pinned",
412 "reg_req" => { "in" => [ "eax", "gp", "edx", "none" ], "out" => [ "eax", "edx" ] },
413 "attr" => "ia32_op_flavour_t dm_flav",
414 "init_attr" => "attr->data.op_flav = dm_flav;",
415 "emit" => ". div %S2 /* unsigned Div(%S1, %S2) -> %D1, (%A1, %A2, %A3) */",
416 "outs" => [ "div_res", "mod_res", "M" ],
423 "comment" => "construct Shl: Shl(a, b) = a << b",
424 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
425 "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */',
431 "cmp_attr" => "return 1;",
432 "comment" => "construct lowered Shl: Shl(a, b) = a << b",
438 "comment" => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
439 # Out requirements is: different from all in
440 # This is because, out must be different from LowPart and ShiftCount.
441 # We could say "!ecx !in_r4" but it can occur, that all values live through
442 # this Shift and the only value dying is the ShiftCount. Then there would be a
443 # register missing, as result must not be ecx and all other registers are
444 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
445 # (and probably never will). So we create artificial interferences of the result
446 # with all inputs, so the spiller can always assure a free register.
447 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!in" ] },
450 if (get_ia32_immop_type(n) == ia32_ImmNone) {
451 if (get_ia32_op_type(n) == ia32_AddrModeD) {
452 4. shld %ia32_emit_am, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
455 4. shld %S3, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
459 if (get_ia32_op_type(n) == ia32_AddrModeD) {
460 4. shld %ia32_emit_am, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
463 4. shld %S3, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
473 "cmp_attr" => "return 1;",
474 "comment" => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
480 "comment" => "construct Shr: Shr(a, b) = a >> b",
481 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
482 "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */',
488 "cmp_attr" => "return 1;",
489 "comment" => "construct lowered Shr: Shr(a, b) = a << b",
495 "comment" => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
496 # Out requirements is: different from all in
497 # This is because, out must be different from LowPart and ShiftCount.
498 # We could say "!ecx !in_r4" but it can occur, that all values live through
499 # this Shift and the only value dying is the ShiftCount. Then there would be a
500 # register missing, as result must not be ecx and all other registers are
501 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
502 # (and probably never will). So we create artificial interferences of the result
503 # with all inputs, so the spiller can always assure a free register.
504 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!in" ] },
507 if (get_ia32_immop_type(n) == ia32_ImmNone) {
508 if (get_ia32_op_type(n) == ia32_AddrModeD) {
509 4. shrd %ia32_emit_am, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
512 4. shrd %S3, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
516 if (get_ia32_op_type(n) == ia32_AddrModeD) {
517 4. shrd %ia32_emit_am, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
520 4. shrd %S3, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
530 "cmp_attr" => "return 1;",
531 "comment" => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
537 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
538 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
539 "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */',
545 "cmp_attr" => "return 1;",
546 "comment" => "construct lowered Shrs: Shrs(a, b) = a << b",
552 "comment" => "construct RotR: RotR(a, b) = a ROTR b",
553 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
554 "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */',
561 "comment" => "construct RotL: RotL(a, b) = a ROTL b",
562 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
563 "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */',
572 "comment" => "construct Minus: Minus(a) = -a",
573 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
574 "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */',
581 "comment" => "construct 64Bit Minus: Minus(a_l, a_h, 0) = 0 - a_l; 0 - a_h - borrow",
583 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
585 . mov %D1, %S1 /* l_res */
586 . mov %D2, %S1 /* h_res */
587 . sub %D1, %S2 /* 0 - a_l -> low_res */
588 . sbb %D2, %S3 /* 0 - a_h - borrow -> high_res */
590 "outs" => [ "low_res", "high_res" ],
596 "cmp_attr" => "return 1;",
597 "comment" => "construct lowered Minus: Minus(a) = -a",
603 "comment" => "construct Increment: Inc(a) = a++",
604 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
605 "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */',
612 "comment" => "construct Decrement: Dec(a) = a--",
613 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
614 "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */',
621 "comment" => "construct Not: Not(a) = !a",
622 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
623 "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */',
631 "op_flags" => "L|X|Y",
632 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
633 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
634 "outs" => [ "false", "true" ],
636 "units" => [ "BRANCH" ],
640 "op_flags" => "L|X|Y",
641 "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
642 "reg_req" => { "in" => [ "gp", "gp" ] },
643 "outs" => [ "false", "true" ],
645 "units" => [ "BRANCH" ],
649 "op_flags" => "L|X|Y",
650 "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
651 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
652 "outs" => [ "false", "true" ],
653 "units" => [ "BRANCH" ],
657 "op_flags" => "L|X|Y",
658 "comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
659 "reg_req" => { "in" => [ "gp", "gp" ] },
660 "units" => [ "BRANCH" ],
664 "op_flags" => "L|X|Y",
665 "comment" => "construct switch",
666 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
668 "units" => [ "BRANCH" ],
674 "comment" => "represents an integer constant",
675 "reg_req" => { "out" => [ "gp" ] },
683 "comment" => "unknown value",
684 "reg_req" => { "out" => [ "gp_UKNWN" ] },
693 "comment" => "unknown value",
694 "reg_req" => { "out" => [ "vfp_UKNWN" ] },
703 "comment" => "unknown value",
704 "reg_req" => { "out" => [ "xmm_UKNWN" ] },
713 "comment" => "unknown GP value",
714 "reg_req" => { "out" => [ "gp_NOREG" ] },
723 "comment" => "unknown VFP value",
724 "reg_req" => { "out" => [ "vfp_NOREG" ] },
733 "comment" => "unknown XMM value",
734 "reg_req" => { "out" => [ "xmm_NOREG" ] },
742 "comment" => "change floating point control word",
743 "reg_req" => { "out" => [ "fp_cw" ] },
751 "state" => "exc_pinned",
752 "comment" => "load floating point control word FldCW(ptr, mem) = LD ptr -> reg",
753 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "fp_cw" ] },
755 "emit" => ". fldcw %ia32_emit_am /* FldCW(%A1) -> %D1 */",
762 "state" => "exc_pinned",
763 "comment" => "store floating point control word: FstCW(ptr, mem) = ST ptr -> reg",
764 "reg_req" => { "in" => [ "gp", "gp", "fp_cw", "none" ] },
766 "emit" => ". fstcw %ia32_emit_am /* FstCW(%A3) -> %A1 */",
772 # we should not rematrialize this node. It produces 2 results and has
773 # very strict constrains
774 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
775 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
776 "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */',
777 "outs" => [ "EAX", "EDX" ],
785 "state" => "exc_pinned",
786 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
787 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp", "none" ] },
790 ' if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) {
791 4. mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
794 4. mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
797 "outs" => [ "res", "M" ],
803 "cmp_attr" => "return 1;",
804 "comment" => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg",
805 "outs" => [ "res", "M" ],
811 "cmp_attr" => "return 1;",
812 "state" => "exc_pinned",
813 "comment" => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val",
820 "state" => "exc_pinned",
821 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
822 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
823 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
831 "state" => "exc_pinned",
832 "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
833 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
834 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
842 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
843 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
844 "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */',
851 "comment" => "push on the stack",
852 "reg_req" => { "in" => [ "gp", "gp", "gp", "esp", "none" ], "out" => [ "esp" ] },
853 "emit" => '. push %ia32_emit_unop /* PUSH(%A1) */',
854 "outs" => [ "stack:I|S", "M" ],
860 "comment" => "pop a gp register from the stack",
861 "reg_req" => { "in" => [ "gp", "gp", "esp", "none" ], "out" => [ "esp", "gp" ] },
862 "emit" => '. pop %ia32_emit_unop /* POP(%A1) */',
863 "outs" => [ "stack:I|S", "res", "M" ],
869 "comment" => "create stack frame",
870 "reg_req" => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] },
871 "emit" => '. enter /* Enter */',
872 "outs" => [ "frame:I", "stack:I|S", "M" ],
878 "comment" => "destroy stack frame",
879 "reg_req" => { "in" => [ "esp", "ebp" ], "out" => [ "ebp", "esp" ] },
880 "emit" => '. leave /* Leave */',
881 "outs" => [ "frame:I", "stack:I|S" ],
888 "comment" => "allocate space on stack",
889 "reg_req" => { "in" => [ "esp", "gp" ], "out" => [ "esp", "none" ] },
890 "outs" => [ "stack:S", "M" ],
896 "comment" => "free space on stack",
897 "reg_req" => { "in" => [ "esp", "gp" ], "out" => [ "esp", "none" ] },
898 "outs" => [ "stack:S", "M" ],
904 "comment" => "get the TLS base address",
905 "reg_req" => { "out" => [ "gp" ] },
911 #-----------------------------------------------------------------------------#
912 # _____ _____ ______ __ _ _ _ #
913 # / ____/ ____| ____| / _| | | | | | #
914 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
915 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
916 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
917 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
918 #-----------------------------------------------------------------------------#
920 # commutative operations
924 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
925 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
926 "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */',
928 "units" => [ "SSE" ],
934 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
935 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
936 "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */',
938 "units" => [ "SSE" ],
944 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
945 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
946 "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */',
948 "units" => [ "SSE" ],
954 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
955 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
956 "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */',
958 "units" => [ "SSE" ],
964 "comment" => "construct SSE And: And(a, b) = a AND b",
965 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
966 "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */',
968 "units" => [ "SSE" ],
974 "comment" => "construct SSE Or: Or(a, b) = a OR b",
975 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
976 "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */',
977 "units" => [ "SSE" ],
983 "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
984 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
985 "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */',
987 "units" => [ "SSE" ],
991 # not commutative operations
995 "comment" => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
996 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
997 "emit" => '. andnp%M %ia32_emit_binop /* SSE AndNot(%A3, %A4) -> %D1 */',
999 "units" => [ "SSE" ],
1005 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
1006 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
1007 "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */',
1009 "units" => [ "SSE" ],
1015 "comment" => "construct SSE Div: Div(a, b) = a / b",
1016 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
1017 "outs" => [ "res", "M" ],
1018 "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */',
1020 "units" => [ "SSE" ],
1027 "comment" => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
1028 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
1030 "units" => [ "SSE" ],
1035 "op_flags" => "L|X|Y",
1036 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
1037 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
1038 "outs" => [ "false", "true" ],
1040 "units" => [ "SSE" ],
1046 "comment" => "represents a SSE constant",
1047 "reg_req" => { "out" => [ "xmm" ] },
1048 "emit" => '. movs%M %D1, %C /* Load fConst into register */',
1050 "units" => [ "SSE" ],
1057 "op_flags" => "L|F",
1058 "state" => "exc_pinned",
1059 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
1060 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
1061 "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */',
1062 "outs" => [ "res", "M" ],
1064 "units" => [ "SSE" ],
1068 "op_flags" => "L|F",
1069 "state" => "exc_pinned",
1070 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
1071 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
1072 "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */',
1074 "units" => [ "SSE" ],
1079 "op_flags" => "L|F",
1080 "state" => "exc_pinned",
1081 "comment" => "construct Store without index: Store(ptr, val, mem) = ST ptr,val",
1082 "reg_req" => { "in" => [ "gp", "xmm", "none" ] },
1083 "emit" => '. movs%M %ia32_emit_am, %S2 /* store XMM0 onto stack */',
1085 "units" => [ "SSE" ],
1090 "op_flags" => "L|F",
1091 "comment" => "construct: transfer a value from x87 FPU into a SSE register",
1092 "cmp_attr" => "return 1;",
1097 "op_flags" => "L|F",
1098 "comment" => "construct: transfer a value from SSE register to x87 FPU",
1099 "cmp_attr" => "return 1;",
1104 "op_flags" => "L|F",
1106 "state" => "exc_pinned",
1107 "comment" => "store ST0 onto stack",
1108 "reg_req" => { "in" => [ "gp", "gp", "none" ] },
1109 "emit" => '. fstp %ia32_emit_am /* store ST0 onto stack */',
1111 "units" => [ "SSE" ],
1116 "op_flags" => "L|F",
1118 "state" => "exc_pinned",
1119 "comment" => "load ST0 from stack",
1120 "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "vf0", "none" ] },
1121 "emit" => '. fld %ia32_emit_am /* load ST0 from stack */',
1122 "outs" => [ "res", "M" ],
1124 "units" => [ "SSE" ],
1130 "op_flags" => "F|H",
1131 "state" => "pinned",
1132 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
1133 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "edi", "esi", "ecx", "none" ] },
1134 "outs" => [ "DST", "SRC", "CNT", "M" ],
1135 "units" => [ "GP" ],
1139 "op_flags" => "F|H",
1140 "state" => "pinned",
1141 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
1142 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "edi", "esi", "none" ] },
1143 "outs" => [ "DST", "SRC", "M" ],
1144 "units" => [ "GP" ],
1150 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
1151 "comment" => "construct Conv Int -> Int",
1152 "units" => [ "GP" ],
1153 "mode" => "mode_Iu",
1157 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
1158 "comment" => "construct Conv Int -> Int",
1159 "units" => [ "GP" ],
1160 "mode" => "mode_Iu",
1164 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
1165 "comment" => "construct Conv Int -> Floating Point",
1167 "units" => [ "SSE" ],
1172 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
1173 "comment" => "construct Conv Floating Point -> Int",
1175 "units" => [ "SSE" ],
1176 "mode" => "mode_Iu",
1180 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
1181 "comment" => "construct Conv Floating Point -> Floating Point",
1183 "units" => [ "SSE" ],
1189 "comment" => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
1190 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "in_r4" ] },
1192 "units" => [ "GP" ],
1193 "mode" => "mode_Iu",
1198 "comment" => "check if Psi condition tree evaluates to true and move result accordingly",
1199 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r3" ] },
1201 "units" => [ "GP" ],
1202 "mode" => "mode_Iu",
1207 "comment" => "construct Conditional Move: SSE Compare + int CMov ",
1208 "reg_req" => { "in" => [ "xmm", "xmm", "gp", "gp" ], "out" => [ "in_r4" ] },
1210 "units" => [ "SSE" ],
1211 "mode" => "mode_Iu",
1216 "comment" => "construct Conditional Move: x87 Compare + int CMov",
1217 "reg_req" => { "in" => [ "vfp", "vfp", "gp", "gp" ], "out" => [ "in_r4" ] },
1219 "units" => [ "VFP" ],
1220 "mode" => "mode_Iu",
1225 "comment" => "construct Set: Set(sel) == sel ? 1 : 0",
1226 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax ebx ecx edx" ] },
1228 "units" => [ "GP" ],
1229 "mode" => "mode_Iu",
1234 "comment" => "check if Psi condition tree evaluates to true and set result accordingly",
1235 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax ebx ecx edx" ] },
1237 "units" => [ "GP" ],
1238 "mode" => "mode_Iu",
1243 "comment" => "construct Set: SSE Compare + int Set",
1244 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "eax ebx ecx edx" ] },
1246 "units" => [ "SSE" ],
1247 "mode" => "mode_Iu",
1252 "comment" => "construct Set: x87 Compare + int Set",
1253 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "eax ebx ecx edx" ] },
1255 "units" => [ "VFP" ],
1256 "mode" => "mode_Iu",
1261 "comment" => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
1262 "reg_req" => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] },
1264 "units" => [ "VFP" ],
1268 #----------------------------------------------------------#
1270 # (_) | | | | / _| | | | #
1271 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
1272 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
1273 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
1274 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
1276 # _ __ ___ __| | ___ ___ #
1277 # | '_ \ / _ \ / _` |/ _ \/ __| #
1278 # | | | | (_) | (_| | __/\__ \ #
1279 # |_| |_|\___/ \__,_|\___||___/ #
1280 #----------------------------------------------------------#
1284 "comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
1285 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1287 "units" => [ "VFP" ],
1293 "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1294 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1296 "units" => [ "VFP" ],
1302 "cmp_attr" => "return 1;",
1303 "comment" => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1309 "comment" => "virtual fp Sub: Sub(a, b) = a - b",
1310 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1312 "units" => [ "VFP" ],
1317 "cmp_attr" => "return 1;",
1318 "comment" => "lowered virtual fp Sub: Sub(a, b) = a - b",
1323 "comment" => "virtual fp Div: Div(a, b) = a / b",
1324 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1325 "outs" => [ "res", "M" ],
1327 "units" => [ "VFP" ],
1331 "cmp_attr" => "return 1;",
1332 "comment" => "lowered virtual fp Div: Div(a, b) = a / b",
1333 "outs" => [ "res", "M" ],
1338 "comment" => "virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1339 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1341 "units" => [ "VFP" ],
1346 "cmp_attr" => "return 1;",
1347 "comment" => "lowered virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1353 "comment" => "virtual fp Abs: Abs(a) = |a|",
1354 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1356 "units" => [ "VFP" ],
1362 "comment" => "virtual fp Chs: Chs(a) = -a",
1363 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1365 "units" => [ "VFP" ],
1371 "comment" => "virtual fp Sin: Sin(a) = sin(a)",
1372 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1374 "units" => [ "VFP" ],
1380 "comment" => "virtual fp Cos: Cos(a) = cos(a)",
1381 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1383 "units" => [ "VFP" ],
1389 "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
1390 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1392 "units" => [ "VFP" ],
1396 # virtual Load and Store
1399 "op_flags" => "L|F",
1400 "state" => "exc_pinned",
1401 "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
1402 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1403 "outs" => [ "res", "M" ],
1405 "units" => [ "VFP" ],
1409 "op_flags" => "L|F",
1410 "state" => "exc_pinned",
1411 "comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
1412 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1414 "units" => [ "VFP" ],
1421 "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1422 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1423 "outs" => [ "res", "M" ],
1425 "units" => [ "VFP" ],
1429 "cmp_attr" => "return 1;",
1430 "comment" => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1431 "outs" => [ "res", "M" ],
1436 "comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1437 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1439 "units" => [ "VFP" ],
1444 "cmp_attr" => "return 1;",
1445 "comment" => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1455 "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg",
1456 "reg_req" => { "out" => [ "vfp" ] },
1458 "units" => [ "VFP" ],
1464 "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg",
1465 "reg_req" => { "out" => [ "vfp" ] },
1467 "units" => [ "VFP" ],
1473 "comment" => "virtual fp Load pi: Ld pi -> reg",
1474 "reg_req" => { "out" => [ "vfp" ] },
1476 "units" => [ "VFP" ],
1482 "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg",
1483 "reg_req" => { "out" => [ "vfp" ] },
1485 "units" => [ "VFP" ],
1491 "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg",
1492 "reg_req" => { "out" => [ "vfp" ] },
1494 "units" => [ "VFP" ],
1500 "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg",
1501 "reg_req" => { "out" => [ "vfp" ] },
1503 "units" => [ "VFP" ],
1509 "comment" => "virtual fp Load ld e: Ld ld e -> reg",
1510 "reg_req" => { "out" => [ "vfp" ] },
1512 "units" => [ "VFP" ],
1519 # "init_attr" => " set_ia32_ls_mode(res, mode);",
1520 "comment" => "represents a virtual floating point constant",
1521 "reg_req" => { "out" => [ "vfp" ] },
1523 "units" => [ "VFP" ],
1530 "op_flags" => "L|X|Y",
1531 "comment" => "represents a virtual floating point compare",
1532 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] },
1533 "outs" => [ "false", "true", "temp_reg_eax" ],
1535 "units" => [ "VFP" ],
1538 #------------------------------------------------------------------------#
1539 # ___ _____ __ _ _ _ #
1540 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1541 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1542 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1543 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1544 #------------------------------------------------------------------------#
1548 "rd_constructor" => "NONE",
1549 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1551 "emit" => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A3, %A4) -> %D1 */',
1556 "rd_constructor" => "NONE",
1557 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1559 "emit" => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A3, %A4) -> %D1 */',
1564 "rd_constructor" => "NONE",
1565 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1567 "emit" => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A3, %A4) -> %D1 */',
1572 "rd_constructor" => "NONE",
1573 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1575 "emit" => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A3, %A4) -> %D1 */',,
1580 "rd_constructor" => "NONE",
1581 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1583 "emit" => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A3, %A4) -> %D1 */',
1588 "rd_constructor" => "NONE",
1589 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1591 "emit" => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A3, %A4) -> %D1 */',
1596 "rd_constructor" => "NONE",
1598 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1600 "emit" => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A3, %A4) -> %D1 */',
1605 "rd_constructor" => "NONE",
1607 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1609 "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A3, %A4) -> %D1 */',
1614 "rd_constructor" => "NONE",
1615 "comment" => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1617 "emit" => '. fprem1 /* x87 fprem(%A3, %A4) -> %D1 */',
1620 # this node is just here, to keep the simulator running
1621 # we can omit this when a fprem simulation function exists
1624 "rd_constructor" => "NONE",
1625 "comment" => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1627 "emit" => '. fprem1 /* x87 fprem(%A3, %A4) -> %D1 WITH POP */',
1632 "rd_constructor" => "NONE",
1633 "comment" => "x87 fp Div: Div(a, b) = a / b",
1635 "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A3, %A4) -> %D1 */',
1640 "rd_constructor" => "NONE",
1641 "comment" => "x87 fp Div: Div(a, b) = a / b",
1643 "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A3, %A4) -> %D1 */',
1648 "rd_constructor" => "NONE",
1649 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1651 "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A3, %A4) -> %D1 */',
1656 "rd_constructor" => "NONE",
1657 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1659 "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A3, %A4) -> %D1 */',
1664 "rd_constructor" => "NONE",
1665 "comment" => "x87 fp Abs: Abs(a) = |a|",
1667 "emit" => '. fabs /* x87 fabs(%A1) -> %D1 */',
1672 "rd_constructor" => "NONE",
1673 "comment" => "x87 fp Chs: Chs(a) = -a",
1675 "emit" => '. fchs /* x87 fchs(%A1) -> %D1 */',
1680 "rd_constructor" => "NONE",
1681 "comment" => "x87 fp Sin: Sin(a) = sin(a)",
1683 "emit" => '. fsin /* x87 sin(%A1) -> %D1 */',
1688 "rd_constructor" => "NONE",
1689 "comment" => "x87 fp Cos: Cos(a) = cos(a)",
1691 "emit" => '. fcos /* x87 cos(%A1) -> %D1 */',
1696 "rd_constructor" => "NONE",
1697 "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1699 "emit" => '. fsqrt $ /* x87 sqrt(%A1) -> %D1 */',
1702 # x87 Load and Store
1705 "rd_constructor" => "NONE",
1706 "op_flags" => "R|L|F",
1707 "state" => "exc_pinned",
1708 "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1710 "emit" => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */',
1714 "rd_constructor" => "NONE",
1715 "op_flags" => "R|L|F",
1716 "state" => "exc_pinned",
1717 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1719 "emit" => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */',
1724 "rd_constructor" => "NONE",
1725 "op_flags" => "R|L|F",
1726 "state" => "exc_pinned",
1727 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1729 "emit" => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */',
1737 "rd_constructor" => "NONE",
1738 "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1740 "emit" => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */',
1745 "rd_constructor" => "NONE",
1746 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1748 "emit" => '. fist %ia32_emit_am /* integer Store(%A3) -> (%A1) */',
1754 "rd_constructor" => "NONE",
1755 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1757 "emit" => '. fistp %ia32_emit_am /* integer Store(%A3) -> (%A1) and pop */',
1764 "op_flags" => "R|c",
1766 "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
1767 "reg_req" => { "out" => [ "vfp" ] },
1768 "emit" => '. fldz /* x87 0.0 -> %D1 */',
1772 "op_flags" => "R|c",
1774 "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
1775 "reg_req" => { "out" => [ "vfp" ] },
1776 "emit" => '. fld1 /* x87 1.0 -> %D1 */',
1780 "op_flags" => "R|c",
1782 "comment" => "x87 fp Load pi: Ld pi -> reg",
1783 "reg_req" => { "out" => [ "vfp" ] },
1784 "emit" => '. fldpi /* x87 pi -> %D1 */',
1788 "op_flags" => "R|c",
1790 "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
1791 "reg_req" => { "out" => [ "vfp" ] },
1792 "emit" => '. fldln2 /* x87 ln(2) -> %D1 */',
1796 "op_flags" => "R|c",
1798 "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
1799 "reg_req" => { "out" => [ "vfp" ] },
1800 "emit" => '. fldlg2 /* x87 log(2) -> %D1 */',
1804 "op_flags" => "R|c",
1806 "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
1807 "reg_req" => { "out" => [ "vfp" ] },
1808 "emit" => '. fldll2t /* x87 ld(10) -> %D1 */',
1812 "op_flags" => "R|c",
1814 "comment" => "x87 fp Load ld e: Ld ld e -> reg",
1815 "reg_req" => { "out" => [ "vfp" ] },
1816 "emit" => '. fldl2e /* x87 ld(e) -> %D1 */',
1820 "op_flags" => "R|c",
1822 "rd_constructor" => "NONE",
1823 "comment" => "represents a x87 constant",
1824 "reg_req" => { "out" => [ "vfp" ] },
1825 "emit" => '. fld %ia32_emit_adr /* Load fConst into register -> %D1 */',
1829 # Note that it is NEVER allowed to do CSE on these nodes
1830 # Moreover, note the virtual register requierements!
1833 "op_flags" => "R|K",
1834 "comment" => "x87 stack exchange",
1836 "cmp_attr" => "return 1;",
1837 "emit" => '. fxch %X1 /* x87 swap %X1, %X3 */',
1841 "op_flags" => "R|K",
1842 "comment" => "x87 stack push",
1844 "cmp_attr" => "return 1;",
1845 "emit" => '. fld %X1 /* x87 push %X1 */',
1850 "comment" => "x87 stack push",
1851 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1852 "cmp_attr" => "return 1;",
1853 "emit" => '. fld %X1 /* x87 push %X1 */',
1857 "op_flags" => "R|K",
1858 "comment" => "x87 stack pop",
1860 "cmp_attr" => "return 1;",
1861 "emit" => '. fstp %X1 /* x87 pop %X1 */',
1867 "op_flags" => "L|X|Y",
1868 "comment" => "floating point compare",
1873 "op_flags" => "L|X|Y",
1874 "comment" => "floating point compare and pop",
1879 "op_flags" => "L|X|Y",
1880 "comment" => "floating point compare and pop twice",
1885 "op_flags" => "L|X|Y",
1886 "comment" => "floating point compare reverse",
1891 "op_flags" => "L|X|Y",
1892 "comment" => "floating point compare reverse and pop",
1897 "op_flags" => "L|X|Y",
1898 "comment" => "floating point compare reverse and pop twice",