3 # This is the specification for the ia32 assembler Firm-operations
10 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
13 # The node description is done as a perl hash initializer with the
14 # following structure:
19 # op_flags => "N|L|C|X|I|F|Y|H|c|K",
20 # irn_flags => "R|N|I|S"
21 # arity => "0|1|2|3 ... |variable|dynamic|any",
22 # state => "floats|pinned|mem_pinned|exc_pinned",
24 # { type => "type 1", name => "name 1" },
25 # { type => "type 2", name => "name 2" },
28 # comment => "any comment for constructor",
29 # reg_req => { in => [ "reg_class|register" ], out => [ "reg_class|register|in_rX" ] },
30 # cmp_attr => "c source code for comparing node attributes",
31 # emit => "emit code with templates",
32 # attr => "attitional attribute arguments for constructor"
33 # init_attr => "emit attribute initialization template"
34 # rd_constructor => "c source code which constructs an ir_node"
35 # latency => "latency of this operation (can be float)"
38 # ... # (all nodes you need to describe)
40 # ); # close the %nodes initializer
42 # op_flags: flags for the operation, OPTIONAL (default is "N")
43 # the op_flags correspond to the firm irop_flags:
46 # C irop_flag_commutative
47 # X irop_flag_cfopcode
48 # I irop_flag_ip_cfopcode
51 # H irop_flag_highlevel
52 # c irop_flag_constlike
55 # irn_flags: special node flags, OPTIONAL (default is 0)
56 # following irn_flags are supported:
59 # I ignore for register allocation
60 # S modifies stack pointer
62 # state: state of the operation, OPTIONAL (default is "floats")
64 # arity: arity of the operation, MUST NOT BE OMITTED
66 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
67 # are always the first 3 arguments and are always autmatically
69 # If this key is missing the following arguments will be created:
70 # for i = 1 .. arity: ir_node *op_i
73 # outs: if a node defines more than one output, the names of the projections
74 # nodes having outs having automatically the mode mode_T
75 # One can also annotate some flags for each out, additional to irn_flags.
76 # They are separated from name with a colon ':', and concatenated by pipe '|'
77 # Only I and S are available at the moment (same meaning as in irn_flags).
78 # example: [ "frame:I", "stack:I|S", "M" ]
80 # comment: OPTIONAL comment for the node constructor
82 # rd_constructor: for every operation there will be a
83 # new_rd_<arch>_<op-name> function with the arguments from above
84 # which creates the ir_node corresponding to the defined operation
85 # you can either put the complete source code of this function here
87 # This key is OPTIONAL. If omitted, the following constructor will
89 # if (!op_<arch>_<op-name>) assert(0);
93 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
96 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
98 # latency: the latency of the operation, default is 1
102 # 0 - no special type
103 # 1 - caller save (register must be saved by the caller of a function)
104 # 2 - callee save (register must be saved by the called function)
105 # 4 - ignore (do not assign this register)
106 # 8 - emitter can choose an arbitrary register of this class
107 # 16 - the register is a virtual one
108 # 32 - register represents a state
109 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
112 { name => "eax", type => 1 },
113 { name => "edx", type => 1 },
114 { name => "ebx", type => 2 },
115 { name => "ecx", type => 1 },
116 { name => "esi", type => 2 },
117 { name => "edi", type => 2 },
118 { name => "ebp", type => 2 },
119 { name => "esp", type => 4 },
120 { name => "gp_NOREG", type => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
121 { name => "gp_UKNWN", type => 4 | 8 | 16 }, # we need a dummy register for Unknown nodes
122 { mode => "mode_Iu" }
125 { name => "xmm0", type => 1 },
126 { name => "xmm1", type => 1 },
127 { name => "xmm2", type => 1 },
128 { name => "xmm3", type => 1 },
129 { name => "xmm4", type => 1 },
130 { name => "xmm5", type => 1 },
131 { name => "xmm6", type => 1 },
132 { name => "xmm7", type => 1 },
133 { name => "xmm_NOREG", type => 4 | 16 }, # we need a dummy register for NoReg nodes
134 { name => "xmm_UKNWN", type => 4 | 8 | 16}, # we need a dummy register for Unknown nodes
138 { name => "vf0", type => 1 | 16 },
139 { name => "vf1", type => 1 | 16 },
140 { name => "vf2", type => 1 | 16 },
141 { name => "vf3", type => 1 | 16 },
142 { name => "vf4", type => 1 | 16 },
143 { name => "vf5", type => 1 | 16 },
144 { name => "vf6", type => 1 | 16 },
145 { name => "vf7", type => 1 | 16 },
146 { name => "vfp_NOREG", type => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
147 { name => "vfp_UKNWN", type => 4 | 8 | 16 }, # we need a dummy register for Unknown nodes
151 { name => "st0", type => 1 },
152 { name => "st1", type => 1 },
153 { name => "st2", type => 1 },
154 { name => "st3", type => 1 },
155 { name => "st4", type => 1 },
156 { name => "st5", type => 1 },
157 { name => "st6", type => 1 },
158 { name => "st7", type => 1 },
161 fp_cw => [ # the floating point control word
162 { name => "fpcw", type => 32 },
163 { mode => "mode_Hu" },
169 GP => [ 1, "GP_EAX", "GP_EBX", "GP_ECX", "GP_EDX", "GP_ESI", "GP_EDI", "GP_EBP" ],
170 SSE => [ 1, "SSE_XMM0", "SSE_XMM1", "SSE_XMM2", "SSE_XMM3", "SSE_XMM4", "SSE_XMM5", "SSE_XMM6", "SSE_XMM7" ],
171 VFP => [ 1, "VFP_VF0", "VFP_VF1", "VFP_VF2", "VFP_VF3", "VFP_VF4", "VFP_VF5", "VFP_VF6", "VFP_VF7" ],
172 BRANCH => [ 1, "BRANCH1", "BRANCH2" ],
177 bundels_per_cycle => 1
181 S1 => "${arch}_emit_source_register(env, node, 0);",
182 S2 => "${arch}_emit_source_register(env, node, 1);",
183 S3 => "${arch}_emit_source_register(env, node, 2);",
184 S4 => "${arch}_emit_source_register(env, node, 3);",
185 S5 => "${arch}_emit_source_register(env, node, 4);",
186 S6 => "${arch}_emit_source_register(env, node, 5);",
187 D1 => "${arch}_emit_dest_register(env, node, 0);",
188 D2 => "${arch}_emit_dest_register(env, node, 1);",
189 D3 => "${arch}_emit_dest_register(env, node, 2);",
190 D4 => "${arch}_emit_dest_register(env, node, 3);",
191 D5 => "${arch}_emit_dest_register(env, node, 4);",
192 D6 => "${arch}_emit_dest_register(env, node, 5);",
193 A1 => "${arch}_emit_in_node_name(env, node, 0);",
194 A2 => "${arch}_emit_in_node_name(env, node, 1);",
195 A3 => "${arch}_emit_in_node_name(env, node, 2);",
196 A4 => "${arch}_emit_in_node_name(env, node, 3);",
197 A5 => "${arch}_emit_in_node_name(env, node, 4);",
198 A6 => "${arch}_emit_in_node_name(env, node, 5);",
199 X1 => "${arch}_emit_x87_name(env, node, 0);",
200 X2 => "${arch}_emit_x87_name(env, node, 1);",
201 X3 => "${arch}_emit_x87_name(env, node, 2);",
202 C => "${arch}_emit_immediate(env, node);",
203 SE => "${arch}_emit_extend_suffix(env, get_ia32_ls_mode(node));",
204 ME => "if(get_mode_size_bits(get_ia32_ls_mode(node)) != 32)\n
205 ia32_emit_mode_suffix(env, get_ia32_ls_mode(node));",
206 M => "${arch}_emit_mode_suffix(env, get_ia32_ls_mode(node));",
207 XM => "${arch}_emit_x87_mode_suffix(env, node);",
208 XXM => "${arch}_emit_xmm_mode_suffix(env, node);",
209 XSD => "${arch}_emit_xmm_mode_suffix_s(env, node);",
210 AM => "${arch}_emit_am(env, node);",
211 unop => "${arch}_emit_unop(env, node);",
212 binop => "${arch}_emit_binop(env, node);",
213 x87_binop => "${arch}_emit_x87_binop(env, node);",
216 #--------------------------------------------------#
219 # _ __ _____ __ _ _ __ ___ _ __ ___ #
220 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
221 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
222 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
225 #--------------------------------------------------#
227 $default_cmp_attr = "return ia32_compare_attr(attr_a, attr_b);";
234 #-----------------------------------------------------------------#
237 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
238 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
239 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
240 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
243 #-----------------------------------------------------------------#
245 # commutative operations
248 # All nodes supporting Addressmode have 5 INs:
249 # 1 - base r1 == NoReg in case of no AM or no base
250 # 2 - index r2 == NoReg in case of no AM or no index
251 # 3 - op1 r3 == always present
252 # 4 - op2 r4 == NoReg in case of immediate operation
253 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
257 comment => "construct Add: Add(a, b) = Add(b, a) = a + b",
258 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
259 emit => '. addl %binop',
265 comment => "construct Add with Carry: Adc(a, b) = Add(b, a) = a + b + carry",
266 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
267 emit => '. adcl %binop',
274 comment => "construct 64Bit Add: Add(a_l, a_h, b_l, b_h) = a_l + b_l; a_h + b_h + carry",
276 reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
283 outs => [ "low_res", "high_res" ],
290 cmp_attr => "return 1;",
291 comment => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
297 cmp_attr => "return 1;",
298 comment => "construct lowered Add with Carry: Adc(a, b) = Adc(b, a) = a + b + carry",
303 # we should not rematrialize this node. It produces 2 results and has
304 # very strict constrains
305 comment => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
306 reg_req => { in => [ "gp", "gp", "eax", "gp", "none" ], out => [ "eax", "edx", "none" ] },
307 emit => '. mull %unop',
308 outs => [ "EAX", "EDX", "M" ],
314 # we should not rematrialize this node. It produces 2 results and has
315 # very strict constrains
317 cmp_attr => "return 1;",
318 comment => "construct lowered MulS: Mul(a, b) = Mul(b, a) = a * b",
319 outs => [ "EAX", "EDX", "M" ],
325 comment => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
326 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
327 emit => '. imull %binop',
335 comment => "construct Mul (1 operand format): Mul(a, b) = Mul(b, a) = a * b",
336 reg_req => { in => [ "gp", "gp", "eax", "gp", "none" ], out => [ "eax", "edx", "none" ] },
337 emit => '. imull %unop',
338 outs => [ "EAX", "EDX", "M" ],
345 cmp_attr => "return 1;",
346 comment => "construct lowered IMul: IMul(a, b) = IMul(b, a) = a * b",
352 comment => "construct And: And(a, b) = And(b, a) = a AND b",
353 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
354 emit => '. andl %binop',
361 comment => "construct Or: Or(a, b) = Or(b, a) = a OR b",
362 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
363 emit => '. orl %binop',
370 comment => "construct Xor: Xor(a, b) = Xor(b, a) = a EOR b",
371 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
372 emit => '. xorl %binop',
379 cmp_attr => "return 1;",
380 comment => "construct lowered Xor: Xor(a, b) = Xor(b, a) = a XOR b",
384 # not commutative operations
388 comment => "construct Sub: Sub(a, b) = a - b",
389 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
390 emit => '. subl %binop',
396 comment => "construct Sub with Carry: SubC(a, b) = a - b - carry",
397 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3 !in_r4" ] },
398 emit => '. sbbl %binop',
405 comment => "construct 64Bit Sub: Sub(a_l, a_h, b_l, b_h) = a_l - b_l; a_h - b_h - borrow",
407 reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
414 outs => [ "low_res", "high_res" ],
420 cmp_attr => "return 1;",
421 comment => "construct lowered Sub: Sub(a, b) = a - b",
426 cmp_attr => "return 1;",
427 comment => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
433 state => "exc_pinned",
434 reg_req => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ], out => [ "eax", "edx", "none" ] },
435 attr => "ia32_op_flavour_t dm_flav",
436 init_attr => "attr->data.op_flav = dm_flav;",
437 emit => ". idivl %unop",
438 outs => [ "div_res", "mod_res", "M" ],
445 state => "exc_pinned",
446 reg_req => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ], out => [ "eax", "edx", "none" ] },
447 attr => "ia32_op_flavour_t dm_flav",
448 init_attr => "attr->data.op_flav = dm_flav;",
449 emit => ". divl %unop",
450 outs => [ "div_res", "mod_res", "M" ],
457 comment => "construct Shl: Shl(a, b) = a << b",
458 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
459 emit => '. shll %binop',
465 cmp_attr => "return 1;",
466 comment => "construct lowered Shl: Shl(a, b) = a << b",
472 comment => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
473 # Out requirements is: different from all in
474 # This is because, out must be different from LowPart and ShiftCount.
475 # We could say "!ecx !in_r4" but it can occur, that all values live through
476 # this Shift and the only value dying is the ShiftCount. Then there would be a
477 # register missing, as result must not be ecx and all other registers are
478 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
479 # (and probably never will). So we create artificial interferences of the result
480 # with all inputs, so the spiller can always assure a free register.
481 reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
484 if (get_ia32_immop_type(node) == ia32_ImmNone) {
485 if (get_ia32_op_type(node) == ia32_AddrModeD) {
486 . shldl %%cl, %S4, %AM
488 . shldl %%cl, %S4, %S3
491 if (get_ia32_op_type(node) == ia32_AddrModeD) {
492 . shldl $%C, %S4, %AM
494 . shldl $%C, %S4, %S3
504 cmp_attr => "return 1;",
505 comment => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
511 comment => "construct Shr: Shr(a, b) = a >> b",
512 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
513 emit => '. shrl %binop',
519 cmp_attr => "return 1;",
520 comment => "construct lowered Shr: Shr(a, b) = a << b",
526 comment => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
527 # Out requirements is: different from all in
528 # This is because, out must be different from LowPart and ShiftCount.
529 # We could say "!ecx !in_r4" but it can occur, that all values live through
530 # this Shift and the only value dying is the ShiftCount. Then there would be a
531 # register missing, as result must not be ecx and all other registers are
532 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
533 # (and probably never will). So we create artificial interferences of the result
534 # with all inputs, so the spiller can always assure a free register.
535 reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
537 if (get_ia32_immop_type(node) == ia32_ImmNone) {
538 if (get_ia32_op_type(node) == ia32_AddrModeD) {
539 . shrdl %%cl, %S4, %AM
541 . shrdl %%cl, %S4, %S3
544 if (get_ia32_op_type(node) == ia32_AddrModeD) {
545 . shrdl $%C, %S4, %AM
547 . shrdl $%C, %S4, %S3
557 cmp_attr => "return 1;",
558 comment => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
564 comment => "construct Shrs: Shrs(a, b) = a >> b",
565 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
566 emit => '. sarl %binop',
572 cmp_attr => "return 1;",
573 comment => "construct lowered Sar: Sar(a, b) = a << b",
579 comment => "construct Ror: Ror(a, b) = a ROR b",
580 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
581 emit => '. rorl %binop',
588 comment => "construct Rol: Rol(a, b) = a ROL b",
589 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
590 emit => '. roll %binop',
599 comment => "construct Minus: Minus(a) = -a",
600 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
601 emit => '. negl %unop',
608 comment => "construct 64Bit Minus: Minus(a_l, a_h, 0) = 0 - a_l; 0 - a_h - borrow",
610 reg_req => { in => [ "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
617 outs => [ "low_res", "high_res" ],
623 cmp_attr => "return 1;",
624 comment => "construct lowered Minus: Minus(a) = -a",
630 comment => "construct Increment: Inc(a) = a++",
631 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
632 emit => '. incl %unop',
639 comment => "construct Decrement: Dec(a) = a--",
640 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
641 emit => '. decl %unop',
648 comment => "construct Not: Not(a) = !a",
649 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
650 emit => '. notl %unop',
660 comment => "construct conditional jump: CMP A, B && JMPxx LABEL",
661 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ] },
662 outs => [ "false", "true" ],
664 units => [ "BRANCH" ],
670 comment => "construct conditional jump: TEST A, B && JMPxx LABEL",
671 reg_req => { in => [ "gp", "gp" ] },
672 outs => [ "false", "true" ],
674 units => [ "BRANCH" ],
680 comment => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
681 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "none", "none" ] },
682 outs => [ "false", "true" ],
683 units => [ "BRANCH" ],
689 comment => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
690 reg_req => { in => [ "gp", "gp" ] },
691 units => [ "BRANCH" ],
697 comment => "construct switch",
698 reg_req => { in => [ "gp" ], out => [ "none" ] },
700 units => [ "BRANCH" ],
706 comment => "represents an integer constant",
707 reg_req => { out => [ "gp" ] },
715 comment => "unknown value",
716 reg_req => { out => [ "gp_UKNWN" ] },
725 comment => "unknown value",
726 reg_req => { out => [ "vfp_UKNWN" ] },
735 comment => "unknown value",
736 reg_req => { out => [ "xmm_UKNWN" ] },
745 comment => "unknown GP value",
746 reg_req => { out => [ "gp_NOREG" ] },
755 comment => "unknown VFP value",
756 reg_req => { out => [ "vfp_NOREG" ] },
765 comment => "unknown XMM value",
766 reg_req => { out => [ "xmm_NOREG" ] },
774 comment => "change floating point control word",
775 reg_req => { out => [ "fp_cw" ] },
783 state => "exc_pinned",
784 comment => "load floating point control word FldCW(ptr, mem) = LD ptr -> reg",
785 reg_req => { in => [ "gp", "gp", "none" ], out => [ "fp_cw" ] },
787 emit => ". fldcw %AM",
794 state => "exc_pinned",
795 comment => "store floating point control word: FstCW(ptr, mem) = ST ptr -> reg",
796 reg_req => { in => [ "gp", "gp", "fp_cw", "none" ] },
798 emit => ". fstcw %AM",
804 # we should not rematrialize this node. It produces 2 results and has
805 # very strict constrains
806 comment => "construct CDQ: sign extend EAX -> EDX:EAX",
807 reg_req => { in => [ "gp" ], out => [ "eax in_r1", "edx" ] },
809 outs => [ "EAX", "EDX" ],
817 state => "exc_pinned",
818 comment => "construct Load: Load(ptr, mem) = LD ptr -> reg",
819 reg_req => { in => [ "gp", "gp", "none" ], out => [ "gp", "none" ] },
821 emit => ". mov%SE%ME%.l %AM, %D1",
822 outs => [ "res", "M" ],
828 cmp_attr => "return 1;",
829 comment => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg",
830 outs => [ "res", "M" ],
836 cmp_attr => "return 1;",
837 state => "exc_pinned",
838 comment => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val",
845 state => "exc_pinned",
846 comment => "construct Store: Store(ptr, val, mem) = ST ptr,val",
847 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "none" ] },
848 emit => '. mov%M %binop',
856 state => "exc_pinned",
857 comment => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
858 reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => ["none" ] },
859 emit => '. mov%M %binop',
867 comment => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
868 reg_req => { in => [ "gp", "gp" ], out => [ "in_r1" ] },
869 emit => '. leal %AM, %D1',
876 comment => "push on the stack",
877 reg_req => { in => [ "gp", "gp", "gp", "esp", "none" ], out => [ "esp", "none" ] },
878 emit => '. pushl %unop',
879 outs => [ "stack:I|S", "M" ],
885 comment => "pop a gp register from the stack",
886 reg_req => { in => [ "gp", "gp", "esp", "none" ], out => [ "esp", "gp", "none" ] },
887 emit => '. popl %unop',
888 outs => [ "stack:I|S", "res", "M" ],
894 comment => "create stack frame",
895 reg_req => { in => [ "esp" ], out => [ "ebp", "esp" ] },
897 outs => [ "frame:I", "stack:I|S", "M" ],
903 comment => "destroy stack frame",
904 reg_req => { in => [ "esp", "ebp" ], out => [ "ebp", "esp" ] },
906 outs => [ "frame:I", "stack:I|S" ],
913 comment => "allocate space on stack",
914 reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "none" ] },
915 emit => '. addl %binop',
916 outs => [ "stack:S", "M" ],
922 comment => "free space on stack",
923 reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "none" ] },
924 emit => '. subl %binop',
925 outs => [ "stack:S", "M" ],
931 comment => "get the TLS base address",
932 reg_req => { out => [ "gp" ] },
938 #-----------------------------------------------------------------------------#
939 # _____ _____ ______ __ _ _ _ #
940 # / ____/ ____| ____| / _| | | | | | #
941 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
942 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
943 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
944 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
945 #-----------------------------------------------------------------------------#
947 # commutative operations
951 comment => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
952 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
953 emit => '. add%XXM %binop',
961 comment => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
962 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
963 emit => '. mul%XXM %binop',
971 comment => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
972 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
973 emit => '. max%XXM %binop',
981 comment => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
982 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
983 emit => '. min%XXM %binop',
991 comment => "construct SSE And: And(a, b) = a AND b",
992 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
993 emit => '. andp%XSD %binop',
1001 comment => "construct SSE Or: Or(a, b) = a OR b",
1002 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1003 emit => '. orp%XSD %binop',
1010 comment => "construct SSE Xor: Xor(a, b) = a XOR b",
1011 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1012 emit => '. xorp%XSD %binop',
1018 # not commutative operations
1022 comment => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
1023 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] },
1024 emit => '. andnp%XSD %binop',
1032 comment => "construct SSE Sub: Sub(a, b) = a - b",
1033 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1034 emit => '. sub%XXM %binop',
1042 comment => "construct SSE Div: Div(a, b) = a / b",
1043 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] },
1044 outs => [ "res", "M" ],
1045 emit => '. div%XXM %binop',
1054 comment => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
1055 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] },
1063 op_flags => "L|X|Y",
1064 comment => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
1065 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "none", "none" ] },
1066 outs => [ "false", "true" ],
1074 comment => "represents a SSE constant",
1075 reg_req => { out => [ "xmm" ] },
1076 emit => '. mov%XXM $%C, %D1',
1086 state => "exc_pinned",
1087 comment => "construct SSE Load: Load(ptr, mem) = LD ptr",
1088 reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none" ] },
1089 emit => '. mov%XXM %AM, %D1',
1090 outs => [ "res", "M" ],
1097 state => "exc_pinned",
1098 comment => "construct Store: Store(ptr, val, mem) = ST ptr,val",
1099 reg_req => { in => [ "gp", "gp", "xmm", "none" ] },
1100 emit => '. mov%XXM %binop',
1108 state => "exc_pinned",
1109 comment => "construct Store without index: Store(ptr, val, mem) = ST ptr,val",
1110 reg_req => { in => [ "gp", "xmm", "none" ] },
1111 emit => '. mov%XXM %S2, %AM',
1119 comment => "construct: transfer a value from x87 FPU into a SSE register",
1120 cmp_attr => "return 1;",
1126 comment => "construct: transfer a value from SSE register to x87 FPU",
1127 cmp_attr => "return 1;",
1134 state => "exc_pinned",
1135 comment => "store ST0 onto stack",
1136 reg_req => { in => [ "gp", "gp", "none" ] },
1137 emit => '. fstp%XM %AM',
1146 state => "exc_pinned",
1147 comment => "load ST0 from stack",
1148 reg_req => { in => [ "gp", "none" ], out => [ "vf0", "none" ] },
1149 emit => '. fld%M %AM',
1150 outs => [ "res", "M" ],
1160 comment => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
1161 reg_req => { in => [ "edi", "esi", "ecx", "none" ], out => [ "edi", "esi", "ecx", "none" ] },
1162 outs => [ "DST", "SRC", "CNT", "M" ],
1169 comment => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
1170 reg_req => { in => [ "edi", "esi", "none" ], out => [ "edi", "esi", "none" ] },
1171 outs => [ "DST", "SRC", "M" ],
1178 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3", "none" ] },
1179 comment => "construct Conv Int -> Int",
1185 reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => [ "in_r3", "none" ] },
1186 comment => "construct Conv Int -> Int",
1192 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm", "none" ] },
1193 comment => "construct Conv Int -> Floating Point",
1200 reg_req => { in => [ "gp", "gp", "xmm", "none" ], out => [ "gp", "none" ] },
1201 comment => "construct Conv Floating Point -> Int",
1208 reg_req => { in => [ "gp", "gp", "xmm", "none" ], out => [ "xmm", "none" ] },
1209 comment => "construct Conv Floating Point -> Floating Point",
1217 comment => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
1218 reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "in_r4" ] },
1226 comment => "check if Psi condition tree evaluates to true and move result accordingly",
1227 reg_req => { in => [ "gp", "gp", "gp" ], out => [ "in_r3" ] },
1235 comment => "construct Conditional Move: SSE Compare + int CMov ",
1236 reg_req => { in => [ "xmm", "xmm", "gp", "gp" ], out => [ "in_r4" ] },
1244 comment => "construct Conditional Move: x87 Compare + int CMov",
1245 reg_req => { in => [ "vfp", "vfp", "gp", "gp" ], out => [ "in_r4" ] },
1253 comment => "construct Set: Set(sel) == sel ? 1 : 0",
1254 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "eax ebx ecx edx" ] },
1262 comment => "check if Psi condition tree evaluates to true and set result accordingly",
1263 reg_req => { in => [ "gp" ], out => [ "eax ebx ecx edx" ] },
1271 comment => "construct Set: SSE Compare + int Set",
1272 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "eax ebx ecx edx" ] },
1280 comment => "construct Set: x87 Compare + int Set",
1281 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "eax ebx ecx edx" ] },
1289 comment => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
1290 reg_req => { in => [ "vfp", "vfp", "vfp", "vfp" ], out => [ "vfp" ] },
1296 #----------------------------------------------------------#
1298 # (_) | | | | / _| | | | #
1299 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
1300 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
1301 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
1302 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
1304 # _ __ ___ __| | ___ ___ #
1305 # | '_ \ / _ \ / _` |/ _ \/ __| #
1306 # | | | | (_) | (_| | __/\__ \ #
1307 # |_| |_|\___/ \__,_|\___||___/ #
1308 #----------------------------------------------------------#
1312 comment => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
1313 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1321 comment => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1322 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1330 cmp_attr => "return 1;",
1331 comment => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1337 comment => "virtual fp Sub: Sub(a, b) = a - b",
1338 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1345 cmp_attr => "return 1;",
1346 comment => "lowered virtual fp Sub: Sub(a, b) = a - b",
1351 comment => "virtual fp Div: Div(a, b) = a / b",
1352 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1353 outs => [ "res", "M" ],
1359 cmp_attr => "return 1;",
1360 comment => "lowered virtual fp Div: Div(a, b) = a / b",
1361 outs => [ "res", "M" ],
1366 comment => "virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1367 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1374 cmp_attr => "return 1;",
1375 comment => "lowered virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1381 comment => "virtual fp Abs: Abs(a) = |a|",
1382 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1390 comment => "virtual fp Chs: Chs(a) = -a",
1391 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1399 comment => "virtual fp Sin: Sin(a) = sin(a)",
1400 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1408 comment => "virtual fp Cos: Cos(a) = cos(a)",
1409 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1417 comment => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
1418 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1424 # virtual Load and Store
1428 state => "exc_pinned",
1429 comment => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
1430 reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] },
1431 outs => [ "res", "M" ],
1438 state => "exc_pinned",
1439 comment => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
1440 reg_req => { in => [ "gp", "gp", "vfp", "none" ] },
1449 comment => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1450 reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] },
1451 outs => [ "res", "M" ],
1457 cmp_attr => "return 1;",
1458 comment => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1459 outs => [ "res", "M" ],
1464 comment => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1465 reg_req => { in => [ "gp", "gp", "vfp", "none" ] },
1472 cmp_attr => "return 1;",
1473 comment => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1483 comment => "virtual fp Load 0.0: Ld 0.0 -> reg",
1484 reg_req => { out => [ "vfp" ] },
1492 comment => "virtual fp Load 1.0: Ld 1.0 -> reg",
1493 reg_req => { out => [ "vfp" ] },
1501 comment => "virtual fp Load pi: Ld pi -> reg",
1502 reg_req => { out => [ "vfp" ] },
1510 comment => "virtual fp Load ln 2: Ld ln 2 -> reg",
1511 reg_req => { out => [ "vfp" ] },
1519 comment => "virtual fp Load lg 2: Ld lg 2 -> reg",
1520 reg_req => { out => [ "vfp" ] },
1528 comment => "virtual fp Load ld 10: Ld ld 10 -> reg",
1529 reg_req => { out => [ "vfp" ] },
1537 comment => "virtual fp Load ld e: Ld ld e -> reg",
1538 reg_req => { out => [ "vfp" ] },
1547 # init_attr => " set_ia32_ls_mode(res, mode);",
1548 comment => "represents a virtual floating point constant",
1549 reg_req => { out => [ "vfp" ] },
1559 op_flags => "L|X|Y",
1560 comment => "represents a virtual floating point compare",
1561 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "none", "none", "eax" ] },
1562 outs => [ "false", "true", "temp_reg_eax" ],
1567 #------------------------------------------------------------------------#
1568 # ___ _____ __ _ _ _ #
1569 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1570 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1571 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1572 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1573 #------------------------------------------------------------------------#
1575 # Note: gas is strangely buggy: fdivrp and fdivp as well as fsubrp and fsubp
1576 # are swapped, we work this around in the emitter...
1580 rd_constructor => "NONE",
1581 comment => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1583 emit => '. fadd%XM %x87_binop',
1588 rd_constructor => "NONE",
1589 comment => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1591 emit => '. faddp %x87_binop',
1596 rd_constructor => "NONE",
1597 comment => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1599 emit => '. fmul%XM %x87_binop',
1604 rd_constructor => "NONE",
1605 comment => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1607 emit => '. fmulp %x87_binop',,
1612 rd_constructor => "NONE",
1613 comment => "x87 fp Sub: Sub(a, b) = a - b",
1615 emit => '. fsub%XM %x87_binop',
1620 rd_constructor => "NONE",
1621 comment => "x87 fp Sub: Sub(a, b) = a - b",
1623 # see note about gas bugs
1624 emit => '. fsubrp %x87_binop',
1629 rd_constructor => "NONE",
1631 comment => "x87 fp SubR: SubR(a, b) = b - a",
1633 emit => '. fsubr%XM %x87_binop',
1638 rd_constructor => "NONE",
1640 comment => "x87 fp SubR: SubR(a, b) = b - a",
1642 # see note about gas bugs
1643 emit => '. fsubp %x87_binop',
1648 rd_constructor => "NONE",
1649 comment => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1654 # this node is just here, to keep the simulator running
1655 # we can omit this when a fprem simulation function exists
1658 rd_constructor => "NONE",
1659 comment => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1666 rd_constructor => "NONE",
1667 comment => "x87 fp Div: Div(a, b) = a / b",
1669 emit => '. fdiv%XM %x87_binop',
1674 rd_constructor => "NONE",
1675 comment => "x87 fp Div: Div(a, b) = a / b",
1677 # see note about gas bugs
1678 emit => '. fdivrp %x87_binop',
1683 rd_constructor => "NONE",
1684 comment => "x87 fp DivR: DivR(a, b) = b / a",
1686 emit => '. fdivr%XM %x87_binop',
1691 rd_constructor => "NONE",
1692 comment => "x87 fp DivR: DivR(a, b) = b / a",
1694 # see note about gas bugs
1695 emit => '. fdivp %x87_binop',
1700 rd_constructor => "NONE",
1701 comment => "x87 fp Abs: Abs(a) = |a|",
1708 rd_constructor => "NONE",
1709 comment => "x87 fp Chs: Chs(a) = -a",
1716 rd_constructor => "NONE",
1717 comment => "x87 fp Sin: Sin(a) = sin(a)",
1724 rd_constructor => "NONE",
1725 comment => "x87 fp Cos: Cos(a) = cos(a)",
1732 rd_constructor => "NONE",
1733 comment => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1735 emit => '. fsqrt $',
1738 # x87 Load and Store
1741 rd_constructor => "NONE",
1742 op_flags => "R|L|F",
1743 state => "exc_pinned",
1744 comment => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1746 emit => '. fld%XM %AM',
1750 rd_constructor => "NONE",
1751 op_flags => "R|L|F",
1752 state => "exc_pinned",
1753 comment => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1755 emit => '. fst%XM %AM',
1760 rd_constructor => "NONE",
1761 op_flags => "R|L|F",
1762 state => "exc_pinned",
1763 comment => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1765 emit => '. fstp%XM %AM',
1773 rd_constructor => "NONE",
1774 comment => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1776 emit => '. fild%XM %AM',
1781 rd_constructor => "NONE",
1782 comment => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1784 emit => '. fist%M %AM',
1790 rd_constructor => "NONE",
1791 comment => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1793 emit => '. fistp%M %AM',
1802 comment => "x87 fp Load 0.0: Ld 0.0 -> reg",
1810 comment => "x87 fp Load 1.0: Ld 1.0 -> reg",
1818 comment => "x87 fp Load pi: Ld pi -> reg",
1826 comment => "x87 fp Load ln 2: Ld ln 2 -> reg",
1834 comment => "x87 fp Load lg 2: Ld lg 2 -> reg",
1842 comment => "x87 fp Load ld 10: Ld ld 10 -> reg",
1844 emit => '. fldll2t',
1850 comment => "x87 fp Load ld e: Ld ld e -> reg",
1856 # Note that it is NEVER allowed to do CSE on these nodes
1857 # Moreover, note the virtual register requierements!
1861 comment => "x87 stack exchange",
1863 cmp_attr => "return 1;",
1864 emit => '. fxch %X1',
1869 comment => "x87 stack push",
1871 cmp_attr => "return 1;",
1872 emit => '. fld %X1',
1877 comment => "x87 stack push",
1878 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1879 cmp_attr => "return 1;",
1880 emit => '. fld %X1',
1885 comment => "x87 stack pop",
1887 cmp_attr => "return 1;",
1888 emit => '. fstp %X1',
1894 op_flags => "L|X|Y",
1895 comment => "floating point compare",
1900 op_flags => "L|X|Y",
1901 comment => "floating point compare and pop",
1906 op_flags => "L|X|Y",
1907 comment => "floating point compare and pop twice",
1912 op_flags => "L|X|Y",
1913 comment => "floating point compare reverse",
1918 op_flags => "L|X|Y",
1919 comment => "floating point compare reverse and pop",
1924 op_flags => "L|X|Y",
1925 comment => "floating point compare reverse and pop twice",
1930 # -------------------------------------------------------------------------------- #
1931 # ____ ____ _____ _ _ #
1932 # / ___/ ___|| ____| __ _____ ___| |_ ___ _ __ _ __ ___ __| | ___ ___ #
1933 # \___ \___ \| _| \ \ / / _ \/ __| __/ _ \| '__| | '_ \ / _ \ / _` |/ _ \/ __| #
1934 # ___) |__) | |___ \ V / __/ (__| || (_) | | | | | | (_) | (_| | __/\__ \ #
1935 # |____/____/|_____| \_/ \___|\___|\__\___/|_| |_| |_|\___/ \__,_|\___||___/ #
1937 # -------------------------------------------------------------------------------- #
1940 # Spilling and reloading of SSE registers, hardcoded, not generated #
1944 state => "exc_pinned",
1945 comment => "construct SSE Load: Load(ptr, mem) = LD ptr",
1946 reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none" ] },
1947 emit => '. movdqu %D1, %AM',
1948 outs => [ "res", "M" ],
1954 state => "exc_pinned",
1955 comment => "construct Store: Store(ptr, val, mem) = ST ptr,val",
1956 reg_req => { in => [ "gp", "gp", "xmm", "none" ] },
1957 emit => '. movdqu %binop',
1964 # Include the generated SIMD node specification written by the SIMD optimization
1965 $my_script_name = dirname($myname) . "/../ia32/ia32_simd_spec.pl";
1966 unless ($return = do $my_script_name) {
1967 warn "couldn't parse $my_script_name: $@" if $@;
1968 warn "couldn't do $my_script_name: $!" unless defined $return;
1969 warn "couldn't run $my_script_name" unless $return;