3 # This is the specification for the ia32 assembler Firm-operations
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
8 # this string marks the beginning of a comment in emit
9 $comment_string = "/*";
11 # the number of additional opcodes you want to register
12 #$additional_opcodes = 0;
14 # The node description is done as a perl hash initializer with the
15 # following structure:
20 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
21 # "irn_flags" => "R|N|I|S"
22 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
23 # "state" => "floats|pinned|mem_pinned|exc_pinned",
25 # { "type" => "type 1", "name" => "name 1" },
26 # { "type" => "type 2", "name" => "name 2" },
29 # "comment" => "any comment for constructor",
30 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
31 # "cmp_attr" => "c source code for comparing node attributes",
32 # "emit" => "emit code with templates",
33 # "attr" => "attitional attribute arguments for constructor"
34 # "init_attr" => "emit attribute initialization template"
35 # "rd_constructor" => "c source code which constructs an ir_node"
36 # "latency" => "latency of this operation (can be float)"
39 # ... # (all nodes you need to describe)
41 # ); # close the %nodes initializer
43 # op_flags: flags for the operation, OPTIONAL (default is "N")
44 # the op_flags correspond to the firm irop_flags:
47 # C irop_flag_commutative
48 # X irop_flag_cfopcode
49 # I irop_flag_ip_cfopcode
52 # H irop_flag_highlevel
53 # c irop_flag_constlike
56 # irn_flags: special node flags, OPTIONAL (default is 0)
57 # following irn_flags are supported:
60 # I ignore for register allocation
61 # S modifies stack pointer
63 # state: state of the operation, OPTIONAL (default is "floats")
65 # arity: arity of the operation, MUST NOT BE OMITTED
67 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
68 # are always the first 3 arguments and are always autmatically
70 # If this key is missing the following arguments will be created:
71 # for i = 1 .. arity: ir_node *op_i
74 # outs: if a node defines more than one output, the names of the projections
75 # nodes having outs having automatically the mode mode_T
77 # comment: OPTIONAL comment for the node constructor
79 # rd_constructor: for every operation there will be a
80 # new_rd_<arch>_<op-name> function with the arguments from above
81 # which creates the ir_node corresponding to the defined operation
82 # you can either put the complete source code of this function here
84 # This key is OPTIONAL. If omitted, the following constructor will
86 # if (!op_<arch>_<op-name>) assert(0);
90 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
93 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
95 # latency: the latency of the operation, default is 1
100 # 1 - caller save (register must be saved by the caller of a function)
101 # 2 - callee save (register must be saved by the called function)
102 # 4 - ignore (do not assign this register)
103 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
106 { "name" => "eax", "type" => 1 },
107 { "name" => "edx", "type" => 1 },
108 { "name" => "ebx", "type" => 2 },
109 { "name" => "ecx", "type" => 1 },
110 { "name" => "esi", "type" => 2 },
111 { "name" => "edi", "type" => 2 },
112 # { "name" => "r11", "type" => 1 },
113 # { "name" => "r12", "type" => 1 },
114 # { "name" => "r13", "type" => 1 },
115 # { "name" => "r14", "type" => 1 },
116 # { "name" => "r15", "type" => 1 },
117 # { "name" => "r16", "type" => 1 },
118 # { "name" => "r17", "type" => 1 },
119 # { "name" => "r18", "type" => 1 },
120 # { "name" => "r19", "type" => 1 },
121 # { "name" => "r20", "type" => 1 },
122 # { "name" => "r21", "type" => 1 },
123 # { "name" => "r22", "type" => 1 },
124 # { "name" => "r23", "type" => 1 },
125 # { "name" => "r24", "type" => 1 },
126 # { "name" => "r25", "type" => 1 },
127 # { "name" => "r26", "type" => 1 },
128 # { "name" => "r27", "type" => 1 },
129 # { "name" => "r28", "type" => 1 },
130 # { "name" => "r29", "type" => 1 },
131 # { "name" => "r30", "type" => 1 },
132 # { "name" => "r31", "type" => 1 },
133 # { "name" => "r32", "type" => 1 },
134 { "name" => "ebp", "type" => 2 },
135 { "name" => "esp", "type" => 4 },
136 { "name" => "gp_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
137 { "name" => "gp_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
138 { "mode" => "mode_P" }
141 { "name" => "xmm0", "type" => 1 },
142 { "name" => "xmm1", "type" => 1 },
143 { "name" => "xmm2", "type" => 1 },
144 { "name" => "xmm3", "type" => 1 },
145 { "name" => "xmm4", "type" => 1 },
146 { "name" => "xmm5", "type" => 1 },
147 { "name" => "xmm6", "type" => 1 },
148 { "name" => "xmm7", "type" => 1 },
149 { "name" => "xmm_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
150 { "name" => "xmm_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
151 { "mode" => "mode_D" }
154 { "name" => "vf0", "type" => 1 },
155 { "name" => "vf1", "type" => 1 },
156 { "name" => "vf2", "type" => 1 },
157 { "name" => "vf3", "type" => 1 },
158 { "name" => "vf4", "type" => 1 },
159 { "name" => "vf5", "type" => 1 },
160 { "name" => "vf6", "type" => 1 },
161 { "name" => "vf7", "type" => 1 },
162 { "name" => "vfp_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
163 { "name" => "vfp_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
164 { "mode" => "mode_E" }
167 { "name" => "st0", "type" => 1 },
168 { "name" => "st1", "type" => 1 },
169 { "name" => "st2", "type" => 1 },
170 { "name" => "st3", "type" => 1 },
171 { "name" => "st4", "type" => 1 },
172 { "name" => "st5", "type" => 1 },
173 { "name" => "st6", "type" => 1 },
174 { "name" => "st7", "type" => 1 },
175 { "mode" => "mode_E" }
179 #--------------------------------------------------#
182 # _ __ _____ __ _ _ __ ___ _ __ ___ #
183 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
184 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
185 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
188 #--------------------------------------------------#
195 #-----------------------------------------------------------------#
198 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
199 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
200 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
201 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
204 #-----------------------------------------------------------------#
206 # commutative operations
209 # All nodes supporting Addressmode have 5 INs:
210 # 1 - base r1 == NoReg in case of no AM or no base
211 # 2 - index r2 == NoReg in case of no AM or no index
212 # 3 - op1 r3 == always present
213 # 4 - op2 r4 == NoReg in case of immediate operation
214 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
218 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
219 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
220 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
221 "emit" => '. add %ia32_emit_binop /* Add(%A3, %A4) -> %D1 */',
222 "outs" => [ "res", "M" ],
226 "comment" => "construct Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
227 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
228 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
229 "emit" => '. adc %ia32_emit_binop /* AddC(%A3, %A4) -> %D1 */',
230 "outs" => [ "res", "M" ],
236 "cmp_attr" => " return 1;\n",
237 "comment" => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
243 "cmp_attr" => " return 1;\n",
244 "comment" => "construct lowered Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
249 "comment" => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
250 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
251 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] },
252 "emit" => '. mul %ia32_emit_unop /* Mul(%A1, %A2) -> %D1 */',
253 "outs" => [ "EAX", "EDX", "M" ],
259 "cmp_attr" => " return 1;\n",
260 "comment" => "construct lowered MulS: MulS(a, b) = MulS(b, a) = a * b",
261 "outs" => [ "EAX", "EDX", "M" ],
267 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
268 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
269 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
270 "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */',
271 "outs" => [ "res", "M" ],
277 "cmp_attr" => " return 1;\n",
278 "comment" => "construct lowered Mul: Mul(a, b) = Mul(b, a) = a * b",
282 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
284 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
285 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
286 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] },
287 "emit" => '. imul %ia32_emit_unop /* Mulh(%A1, %A2) -> %D1 */',
288 "outs" => [ "EAX", "EDX", "M" ],
294 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
295 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
296 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
297 "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */',
298 "outs" => [ "res", "M" ],
303 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
304 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
305 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
306 "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */',
307 "outs" => [ "res", "M" ],
312 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
313 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
314 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
315 "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */',
316 "outs" => [ "res", "M" ],
321 "cmp_attr" => " return 1;\n",
322 "comment" => "construct lowered Eor: Eor(a, b) = Eor(b, a) = a EOR b",
328 "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
329 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
331 '2. cmp %S1, %S2 /* prepare Max (%S1 - %S2), (%A1, %A2) */
332 if (mode_is_signed(get_irn_mode(n))) {
333 4. cmovl %D1, %S2 /* %S1 is less %S2 */
336 4. cmovb %D1, %S2 /* %S1 is below %S2 */
344 "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
345 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
347 '2. cmp %S1, %S2 /* prepare Min (%S1 - %S2), (%A1, %A2) */
348 if (mode_is_signed(get_irn_mode(n))) {
349 2. cmovg %D1, %S2 /* %S1 is greater %S2 */
352 2. cmova %D1, %S2, %D1 /* %S1 is above %S2 */
358 # not commutative operations
362 "comment" => "construct Sub: Sub(a, b) = a - b",
363 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
364 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
365 "emit" => '. sub %ia32_emit_binop /* Sub(%A3, %A4) -> %D1 */',
366 "outs" => [ "res", "M" ],
370 "comment" => "construct Sub with Carry: SubC(a, b) = a - b - carry",
371 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
372 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3 !in_r4" ] },
373 "emit" => '. sbb %ia32_emit_binop /* SubC(%A3, %A4) -> %D1 */',
374 "outs" => [ "res", "M" ],
379 "cmp_attr" => " return 1;\n",
380 "comment" => "construct lowered Sub: Sub(a, b) = a - b",
385 "cmp_attr" => " return 1;\n",
386 "comment" => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
392 "state" => "exc_pinned",
393 "reg_req" => { "in" => [ "eax", "gp", "edx", "none" ], "out" => [ "eax", "edx" ] },
394 "attr" => "ia32_op_flavour_t dm_flav",
395 "init_attr" => " attr->data.op_flav = dm_flav;",
396 "cmp_attr" => " return attr_a->data.op_flav != attr_b->data.op_flav;\n",
398 ' if (mode_is_signed(get_ia32_res_mode(n))) {
399 4. idiv %S2 /* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
402 4. div %S2 /* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
405 "outs" => [ "div_res", "mod_res", "M" ],
411 "comment" => "construct Shl: Shl(a, b) = a << b",
412 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
413 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
414 "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */',
415 "outs" => [ "res", "M" ],
419 "cmp_attr" => " return 1;\n",
420 "comment" => "construct lowered Shl: Shl(a, b) = a << b",
426 "comment" => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
427 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
428 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r5" ] },
431 if (get_ia32_immop_type(n) == ia32_ImmNone) {
432 if (get_ia32_op_type(n) == ia32_AddrModeD) {
433 4. shld %ia32_emit_am, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
436 4. shld %S3, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
440 if (get_ia32_op_type(n) == ia32_AddrModeD) {
441 4. shld %ia32_emit_am, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
444 4. shld %S3, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
448 "outs" => [ "res", "M" ],
453 "cmp_attr" => " return 1;\n",
454 "comment" => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
460 "comment" => "construct Shr: Shr(a, b) = a >> b",
461 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
462 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
463 "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */',
464 "outs" => [ "res", "M" ],
468 "cmp_attr" => " return 1;\n",
469 "comment" => "construct lowered Shr: Shr(a, b) = a << b",
475 "comment" => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
476 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
477 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r5" ] },
480 if (get_ia32_immop_type(n) == ia32_ImmNone) {
481 if (get_ia32_op_type(n) == ia32_AddrModeD) {
482 4. shrd %ia32_emit_am, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
485 4. shrd %S3, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
489 if (get_ia32_op_type(n) == ia32_AddrModeD) {
490 4. shrd %ia32_emit_am, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
493 4. shrd %S3, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
497 "outs" => [ "res", "M" ],
502 "cmp_attr" => " return 1;\n",
503 "comment" => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
509 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
510 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
511 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
512 "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */',
513 "outs" => [ "res", "M" ],
517 "cmp_attr" => " return 1;\n",
518 "comment" => "construct lowered Shrs: Shrs(a, b) = a << b",
524 "comment" => "construct RotR: RotR(a, b) = a ROTR b",
525 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
526 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
527 "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */',
528 "outs" => [ "res", "M" ],
533 "comment" => "construct RotL: RotL(a, b) = a ROTL b",
534 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
535 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
536 "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */',
537 "outs" => [ "res", "M" ],
544 "comment" => "construct Minus: Minus(a) = -a",
545 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
546 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
547 "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */',
548 "outs" => [ "res", "M" ],
552 "cmp_attr" => " return 1;\n",
553 "comment" => "construct lowered Minus: Minus(a) = -a",
559 "comment" => "construct Increment: Inc(a) = a++",
560 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
561 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
562 "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */',
563 "outs" => [ "res", "M" ],
568 "comment" => "construct Decrement: Dec(a) = a--",
569 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
570 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
571 "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */',
572 "outs" => [ "res", "M" ],
577 "comment" => "construct Not: Not(a) = !a",
578 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
579 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
580 "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */',
581 "outs" => [ "res", "M" ],
587 "op_flags" => "L|X|Y",
588 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
589 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
590 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
591 "outs" => [ "false", "true" ],
596 "op_flags" => "L|X|Y",
597 "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
598 "reg_req" => { "in" => [ "gp", "gp" ] },
599 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
600 "outs" => [ "false", "true" ],
605 "op_flags" => "L|X|Y",
606 "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
607 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
608 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
609 "outs" => [ "false", "true" ],
613 "op_flags" => "L|X|Y",
614 "comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
615 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
616 "reg_req" => { "in" => [ "gp", "gp" ] },
620 "op_flags" => "L|X|Y",
621 "comment" => "construct switch",
622 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
623 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
630 "comment" => "represents an integer constant",
631 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
632 "reg_req" => { "in" => [ "none" ], "out" => [ "gp" ] },
637 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
638 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
639 "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */',
640 "outs" => [ "EAX", "EDX" ],
647 "state" => "exc_pinned",
648 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
649 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
650 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
653 ' if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) {
654 4. mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
657 4. mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
660 "outs" => [ "res", "M" ],
665 "cmp_attr" => " return 1;\n",
666 "comment" => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg",
667 "outs" => [ "res", "M" ],
673 "cmp_attr" => " return 1;\n",
674 "state" => "exc_pinned",
675 "comment" => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val",
682 "state" => "exc_pinned",
683 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
684 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
685 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
686 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
693 "state" => "exc_pinned",
694 "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
695 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
696 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
697 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
704 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
705 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
706 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
707 "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */',
712 # We don't set class modify_stack here (but we will do this on proj 0)
713 "comment" => "push a gp register on the stack",
714 "reg_req" => { "in" => [ "esp", "gp", "none" ], "out" => [ "esp" ] },
716 if (get_ia32_id_cnst(n)) {
717 if (get_ia32_immop_type(n) == ia32_ImmConst) {
718 4. push %C /* Push const on stack */
720 4. push OFFSET FLAT:%C /* Push symconst on stack */
723 else if (get_ia32_op_type(n) == ia32_Normal) {
724 2. push %S2 /* Push(%A2) */
727 2. push %ia32_emit_am /* Push memory to stack */
730 "outs" => [ "stack", "M" ],
735 # We don't set class modify stack here (but we will do this on proj 1)
736 "comment" => "pop a gp register from the stack",
737 "reg_req" => { "in" => [ "esp", "none" ], "out" => [ "gp", "esp" ] },
739 if (get_ia32_op_type(n) == ia32_Normal) {
740 2. pop %D1 /* Pop from stack into %D1 */
743 2. pop %ia32_emit_am /* Pop from stack into memory */
746 "outs" => [ "res", "stack", "M" ],
751 "comment" => "create stack frame",
752 "reg_req" => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] },
753 "emit" => '. enter /* Enter */',
754 "outs" => [ "frame", "stack", "M" ],
759 "comment" => "destroy stack frame",
760 "reg_req" => { "in" => [ "esp", "ebp" ], "out" => [ "ebp", "esp" ] },
761 "emit" => '. leave /* Leave */',
762 "outs" => [ "frame", "stack", "M" ],
768 "comment" => "allocate space on stack",
769 "reg_req" => { "in" => [ "esp", "gp" ], "out" => [ "esp", "none" ] },
770 "outs" => [ "stack", "M" ],
773 #-----------------------------------------------------------------------------#
774 # _____ _____ ______ __ _ _ _ #
775 # / ____/ ____| ____| / _| | | | | | #
776 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
777 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
778 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
779 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
780 #-----------------------------------------------------------------------------#
782 # commutative operations
786 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
787 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
788 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
789 "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */',
790 "outs" => [ "res", "M" ],
796 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
797 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
798 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
799 "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */',
800 "outs" => [ "res", "M" ],
806 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
807 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
808 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
809 "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */',
810 "outs" => [ "res", "M" ],
816 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
817 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
818 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
819 "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */',
820 "outs" => [ "res", "M" ],
826 "comment" => "construct SSE And: And(a, b) = a AND b",
827 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
828 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
829 "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */',
830 "outs" => [ "res", "M" ],
836 "comment" => "construct SSE Or: Or(a, b) = a OR b",
837 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
838 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
839 "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */',
840 "outs" => [ "res", "M" ],
845 "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
846 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
847 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
848 "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */',
849 "outs" => [ "res", "M" ],
853 # not commutative operations
857 "comment" => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
858 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
859 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
860 "emit" => '. andnp%M %ia32_emit_binop /* SSE AndNot(%A3, %A4) -> %D1 */',
861 "outs" => [ "res", "M" ],
867 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
868 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
869 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
870 "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */',
871 "outs" => [ "res", "M" ],
877 "comment" => "construct SSE Div: Div(a, b) = a / b",
878 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
879 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
880 "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */',
881 "outs" => [ "res", "M" ],
889 "comment" => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
890 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
891 "outs" => [ "res", "M" ],
896 "op_flags" => "L|X|Y",
897 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
898 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
899 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
900 "outs" => [ "false", "true" ],
907 "comment" => "represents a SSE constant",
908 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
909 "reg_req" => { "in" => [ "none" ], "out" => [ "xmm" ] },
910 "emit" => '. movs%M %D1, %C /* Load fConst into register */',
918 "state" => "exc_pinned",
919 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
920 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
921 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm" ] },
922 "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */',
923 "outs" => [ "res", "M" ],
929 "state" => "exc_pinned",
930 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
931 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
932 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
933 "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */',
940 "state" => "exc_pinned",
941 "comment" => "construct Store without index: Store(ptr, val, mem) = ST ptr,val",
942 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
943 "reg_req" => { "in" => [ "gp", "xmm", "none" ] },
944 "emit" => '. movs%M %ia32_emit_am, %S2 /* store XMM0 onto stack */',
951 "comment" => "construct: transfer a value from x87 FPU into a SSE register",
952 "cmp_attr" => " return 1;\n",
958 "comment" => "construct: transfer a value from SSE register to x87 FPU",
959 "cmp_attr" => " return 1;\n",
966 "state" => "exc_pinned",
967 "comment" => "store ST0 onto stack",
968 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
969 "reg_req" => { "in" => [ "gp", "none" ] },
970 "emit" => '. fstp %ia32_emit_am /* store ST0 onto stack */',
978 "state" => "exc_pinned",
979 "comment" => "load ST0 from stack",
980 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
981 "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "st0", "none" ] },
982 "emit" => '. fld %ia32_emit_am /* load ST0 from stack */',
983 "outs" => [ "res", "M" ],
992 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
993 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "edi", "esi", "ecx", "none" ] },
994 "outs" => [ "DST", "SRC", "CNT", "M" ],
1000 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
1001 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1002 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "edi", "esi", "none" ] },
1003 "outs" => [ "DST", "SRC", "M" ],
1009 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
1010 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1011 "comment" => "construct Conv Int -> Int",
1012 "outs" => [ "res", "M" ],
1016 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
1017 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1018 "comment" => "construct Conv Int -> Int",
1019 "outs" => [ "res", "M" ],
1023 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
1024 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1025 "comment" => "construct Conv Int -> Floating Point",
1026 "outs" => [ "res", "M" ],
1031 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
1032 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1033 "comment" => "construct Conv Floating Point -> Int",
1034 "outs" => [ "res", "M" ],
1039 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
1040 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1041 "comment" => "construct Conv Floating Point -> Floating Point",
1042 "outs" => [ "res", "M" ],
1048 "comment" => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
1049 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "in_r4" ] },
1055 "comment" => "check if Psi condition tree evaluates to true and move result accordingly",
1056 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r3" ] },
1062 "comment" => "construct Conditional Move: SSE Compare + int CMov ",
1063 "reg_req" => { "in" => [ "xmm", "xmm", "gp", "gp" ], "out" => [ "in_r4" ] },
1069 "comment" => "construct Conditional Move: x87 Compare + int CMov",
1070 "reg_req" => { "in" => [ "vfp", "vfp", "gp", "gp" ], "out" => [ "in_r4" ] },
1076 "comment" => "construct Set: Set(sel) == sel ? 1 : 0",
1077 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1078 "outs" => [ "res", "M" ],
1084 "comment" => "check if Psi condition tree evaluates to true and set result accordingly",
1085 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax ebx ecx edx" ] },
1091 "comment" => "construct Set: SSE Compare + int Set",
1092 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1093 "outs" => [ "res", "M" ],
1099 "comment" => "construct Set: x87 Compare + int Set",
1100 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1101 "outs" => [ "res", "M" ],
1107 "comment" => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
1108 "reg_req" => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] },
1112 #----------------------------------------------------------#
1114 # (_) | | | | / _| | | | #
1115 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
1116 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
1117 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
1118 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
1120 # _ __ ___ __| | ___ ___ #
1121 # | '_ \ / _ \ / _` |/ _ \/ __| #
1122 # | | | | (_) | (_| | __/\__ \ #
1123 # |_| |_|\___/ \__,_|\___||___/ #
1124 #----------------------------------------------------------#
1128 "comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
1129 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1130 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1131 "outs" => [ "res", "M" ],
1137 "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1138 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1139 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1140 "outs" => [ "res", "M" ],
1146 "cmp_attr" => " return 1;\n",
1147 "comment" => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1153 "comment" => "virtual fp Sub: Sub(a, b) = a - b",
1154 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1155 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1156 "outs" => [ "res", "M" ],
1161 "cmp_attr" => " return 1;\n",
1162 "comment" => "lowered virtual fp Sub: Sub(a, b) = a - b",
1167 "comment" => "virtual fp Div: Div(a, b) = a / b",
1168 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1169 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1170 "outs" => [ "res", "M" ],
1175 "cmp_attr" => " return 1;\n",
1176 "comment" => "lowered virtual fp Div: Div(a, b) = a / b",
1182 "comment" => "virtual fp Abs: Abs(a) = |a|",
1183 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1189 "comment" => "virtual fp Chs: Chs(a) = -a",
1190 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1196 "comment" => "virtual fp Sin: Sin(a) = sin(a)",
1197 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1203 "comment" => "virtual fp Cos: Cos(a) = cos(a)",
1204 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1210 "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
1211 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1215 # virtual Load and Store
1218 "op_flags" => "L|F",
1219 "state" => "exc_pinned",
1220 "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
1221 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1222 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1223 "outs" => [ "res", "M" ],
1228 "op_flags" => "L|F",
1229 "state" => "exc_pinned",
1230 "comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
1231 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1232 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1240 "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1241 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1242 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1243 "outs" => [ "res", "M" ],
1248 "cmp_attr" => " return 1;\n",
1249 "comment" => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1250 "outs" => [ "res", "M" ],
1255 "comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1256 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1257 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1263 "cmp_attr" => " return 1;\n",
1264 "comment" => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1274 "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg",
1275 "reg_req" => { "out" => [ "vfp" ] },
1281 "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg",
1282 "reg_req" => { "out" => [ "vfp" ] },
1288 "comment" => "virtual fp Load pi: Ld pi -> reg",
1289 "reg_req" => { "out" => [ "vfp" ] },
1295 "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg",
1296 "reg_req" => { "out" => [ "vfp" ] },
1302 "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg",
1303 "reg_req" => { "out" => [ "vfp" ] },
1309 "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg",
1310 "reg_req" => { "out" => [ "vfp" ] },
1316 "comment" => "virtual fp Load ld e: Ld ld e -> reg",
1317 "reg_req" => { "out" => [ "vfp" ] },
1324 "init_attr" => " set_ia32_ls_mode(res, mode);",
1325 "comment" => "represents a virtual floating point constant",
1326 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1327 "reg_req" => { "in" => [ "none" ], "out" => [ "vfp" ] },
1334 "op_flags" => "L|X|Y",
1335 "comment" => "represents a virtual floating point compare",
1336 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1337 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] },
1338 "outs" => [ "false", "true", "temp_reg_eax" ],
1342 #------------------------------------------------------------------------#
1343 # ___ _____ __ _ _ _ #
1344 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1345 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1346 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1347 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1348 #------------------------------------------------------------------------#
1352 "rd_constructor" => "NONE",
1353 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1355 "emit" => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A3, %A4) -> %D1 */',
1360 "rd_constructor" => "NONE",
1361 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1363 "emit" => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A3, %A4) -> %D1 */',
1368 "rd_constructor" => "NONE",
1369 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1371 "emit" => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A3, %A4) -> %D1 */',
1376 "rd_constructor" => "NONE",
1377 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1379 "emit" => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A3, %A4) -> %D1 */',,
1384 "rd_constructor" => "NONE",
1385 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1387 "emit" => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A3, %A4) -> %D1 */',
1392 "rd_constructor" => "NONE",
1393 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1395 "emit" => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A3, %A4) -> %D1 */',
1400 "rd_constructor" => "NONE",
1402 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1404 "emit" => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A3, %A4) -> %D1 */',
1409 "rd_constructor" => "NONE",
1411 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1413 "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A3, %A4) -> %D1 */',
1418 "rd_constructor" => "NONE",
1419 "comment" => "x87 fp Div: Div(a, b) = a / b",
1421 "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A3, %A4) -> %D1 */',
1426 "rd_constructor" => "NONE",
1427 "comment" => "x87 fp Div: Div(a, b) = a / b",
1429 "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A3, %A4) -> %D1 */',
1434 "rd_constructor" => "NONE",
1435 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1437 "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A3, %A4) -> %D1 */',
1442 "rd_constructor" => "NONE",
1443 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1445 "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A3, %A4) -> %D1 */',
1450 "rd_constructor" => "NONE",
1451 "comment" => "x87 fp Abs: Abs(a) = |a|",
1453 "emit" => '. fabs /* x87 fabs(%A1) -> %D1 */',
1458 "rd_constructor" => "NONE",
1459 "comment" => "x87 fp Chs: Chs(a) = -a",
1461 "emit" => '. fchs /* x87 fchs(%A1) -> %D1 */',
1466 "rd_constructor" => "NONE",
1467 "comment" => "x87 fp Sin: Sin(a) = sin(a)",
1469 "emit" => '. fsin /* x87 sin(%A1) -> %D1 */',
1474 "rd_constructor" => "NONE",
1475 "comment" => "x87 fp Cos: Cos(a) = cos(a)",
1477 "emit" => '. fcos /* x87 cos(%A1) -> %D1 */',
1482 "rd_constructor" => "NONE",
1483 "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1485 "emit" => '. fsqrt $ /* x87 sqrt(%A1) -> %D1 */',
1488 # x87 Load and Store
1491 "rd_constructor" => "NONE",
1492 "op_flags" => "R|L|F",
1493 "state" => "exc_pinned",
1494 "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1496 "emit" => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */',
1500 "rd_constructor" => "NONE",
1501 "op_flags" => "R|L|F",
1502 "state" => "exc_pinned",
1503 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1505 "emit" => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */',
1509 "rd_constructor" => "NONE",
1510 "op_flags" => "R|L|F",
1511 "state" => "exc_pinned",
1512 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1514 "emit" => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */',
1521 "rd_constructor" => "NONE",
1522 "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1524 "emit" => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */',
1529 "rd_constructor" => "NONE",
1530 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1532 "emit" => '. fist %ia32_emit_am /* integer Store(%A3) -> (%A1) */',
1537 "rd_constructor" => "NONE",
1538 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1540 "emit" => '. fistp %ia32_emit_am /* integer Store(%A3) -> (%A1) and pop */',
1548 "rd_constructor" => "NONE",
1549 "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
1551 "emit" => '. fldz /* x87 0.0 -> %D1 */',
1557 "rd_constructor" => "NONE",
1558 "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
1560 "emit" => '. fld1 /* x87 1.0 -> %D1 */',
1566 "rd_constructor" => "NONE",
1567 "comment" => "x87 fp Load pi: Ld pi -> reg",
1569 "emit" => '. fldpi /* x87 pi -> %D1 */',
1575 "rd_constructor" => "NONE",
1576 "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
1578 "emit" => '. fldln2 /* x87 ln(2) -> %D1 */',
1584 "rd_constructor" => "NONE",
1585 "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
1587 "emit" => '. fldlg2 /* x87 log(2) -> %D1 */',
1593 "rd_constructor" => "NONE",
1594 "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
1596 "emit" => '. fldll2t /* x87 ld(10) -> %D1 */',
1602 "rd_constructor" => "NONE",
1603 "comment" => "x87 fp Load ld e: Ld ld e -> reg",
1605 "emit" => '. fldl2e /* x87 ld(e) -> %D1 */',
1609 "op_flags" => "R|c",
1611 "rd_constructor" => "NONE",
1612 "comment" => "represents a x87 constant",
1613 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1614 "reg_req" => { "out" => [ "st" ] },
1615 "emit" => '. fld %ia32_emit_adr /* Load fConst into register -> %D1 */',
1619 # Note that it is NEVER allowed to do CSE on these nodes
1622 "op_flags" => "R|K",
1623 "comment" => "x87 stack exchange",
1624 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1625 "cmp_attr" => " return 1;\n",
1626 "emit" => '. fxch %X1 /* x87 swap %X1, %X3 */',
1631 "comment" => "x87 stack push",
1632 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1633 "cmp_attr" => " return 1;\n",
1634 "emit" => '. fld %X1 /* x87 push %X1 */',
1638 "op_flags" => "R|K",
1639 "comment" => "x87 stack pop",
1640 "reg_req" => { "out" => [ "st" ] },
1641 "cmp_attr" => " return 1;\n",
1642 "emit" => '. fstp %X1 /* x87 pop %X1 */',
1648 "op_flags" => "L|X|Y",
1649 "comment" => "floating point compare",
1650 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1655 "op_flags" => "L|X|Y",
1656 "comment" => "floating point compare and pop",
1657 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1662 "op_flags" => "L|X|Y",
1663 "comment" => "floating point compare and pop twice",
1664 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1669 "op_flags" => "L|X|Y",
1670 "comment" => "floating point compare reverse",
1671 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1676 "op_flags" => "L|X|Y",
1677 "comment" => "floating point compare reverse and pop",
1678 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1683 "op_flags" => "L|X|Y",
1684 "comment" => "floating point compare reverse and pop twice",
1685 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",