3 # This is the specification for the ia32 assembler Firm-operations
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
9 # The node description is done as a perl hash initializer with the
10 # following structure:
15 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
16 # "irn_flags" => "R|N|I"
17 # "arity" => "0|1|2|3 ... |variable|dynamic|all",
18 # "state" => "floats|pinned",
20 # { "type" => "type 1", "name" => "name 1" },
21 # { "type" => "type 2", "name" => "name 2" },
24 # "comment" => "any comment for constructor",
25 # "emit" => "emit code with templates",
26 # "rd_constructor" => "c source code which constructs an ir_node"
29 # ... # (all nodes you need to describe)
31 # ); # close the %nodes initializer
33 # op_flags: flags for the operation, OPTIONAL (default is "N")
34 # the op_flags correspond to the firm irop_flags:
37 # C irop_flag_commutative
38 # X irop_flag_cfopcode
39 # I irop_flag_ip_cfopcode
42 # H irop_flag_highlevel
43 # c irop_flag_constlike
46 # irn_flags: special node flags, OPTIONAL (default is 0)
47 # following irn_flags are supported:
50 # I ignore for register allocation
52 # state: state of the operation, OPTIONAL (default is "pinned")
54 # arity: arity of the operation, MUST NOT BE OMITTED
56 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
57 # are always the first 3 arguments and are always autmatically
59 # If this key is missing the following arguments will be created:
60 # for i = 1 .. arity: ir_node *op_i
63 # comment: OPTIONAL comment for the node constructor
65 # rd_constructor: for every operation there will be a
66 # new_rd_<arch>_<op-name> function with the arguments from above
67 # which creates the ir_node corresponding to the defined operation
68 # you can either put the complete source code of this function here
70 # This key is OPTIONAL. If omitted, the following constructor will
72 # if (!op_<arch>_<op-name>) assert(0);
76 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
79 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
83 # 1 - caller save (register must be saved by the caller of a function)
84 # 2 - callee save (register must be saved by the called function)
85 # 4 - ignore (do not assign this register)
86 # 8 - this is the stack pointer
87 # 16 - this is the base pointer
88 # NOTE: Make sure to list the registers returning the call-result before all other
89 # caller save registers and in the correct order, otherwise it will break
91 # Last entry of each class is the largest Firm-Mode a register can hold
94 { "name" => "eax", "type" => 1 },
95 { "name" => "edx", "type" => 1 },
96 { "name" => "ebx", "type" => 2 },
97 { "name" => "ecx", "type" => 1 },
98 { "name" => "esi", "type" => 2 },
99 { "name" => "edi", "type" => 2 },
100 { "name" => "ebp", "type" => 16 },
101 { "name" => "esp", "type" => 8 },
102 { "name" => "xxx", "type" => 4 }, # we need a dummy register for NoReg and Unknown nodes
103 { "mode" => "mode_P" }
106 { "name" => "xmm0", "type" => 1 },
107 { "name" => "xmm1", "type" => 1 },
108 { "name" => "xmm2", "type" => 1 },
109 { "name" => "xmm3", "type" => 1 },
110 { "name" => "xmm4", "type" => 1 },
111 { "name" => "xmm5", "type" => 1 },
112 { "name" => "xmm6", "type" => 1 },
113 { "name" => "xmm7", "type" => 1 },
114 { "name" => "xxxx", "type" => 4 }, # we need a dummy register for NoReg and Unknown nodes
115 { "mode" => "mode_D" }
119 #--------------------------------------------------#
122 # _ __ _____ __ _ _ __ ___ _ __ ___ #
123 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
124 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
125 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
128 #--------------------------------------------------#
132 #-----------------------------------------------------------------#
135 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
136 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
137 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
138 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
141 #-----------------------------------------------------------------#
143 # commutative operations
146 # All nodes supporting Addressmode have 5 INs:
147 # 1 - base r1 == NoReg in case of no AM or no base
148 # 2 - index r2 == NoReg in case of no AM or no index
149 # 3 - op1 r3 == always present
150 # 4 - op2 r4 == NoReg in case of immediate operation
151 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
155 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
156 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
157 "emit" => '. add %ia32_emit_binop\t\t\t/* Add(%A1, %A2) -> %D1 */'
162 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
163 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
164 "emit" => '. imul %ia32_emit_binop\t\t\t/* Mul(%A1, %A2) -> %D1 */'
167 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
169 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
170 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r1", "edx in_r2" ] },
171 "emit" => '. imul %ia32_emit_unop\t\t\t/* Mulh(%A1, %A2) -> %D1 */ '
176 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
177 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
178 "emit" => '. and %ia32_emit_binop\t\t\t/* And(%A1, %A2) -> %D1 */'
183 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
184 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
185 "emit" => '. or %ia32_emit_binop\t\t\t/* Or(%A1, %A2) -> %D1 */'
190 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
191 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
192 "emit" => '. xor %ia32_emit_binop\t\t\t/* Xor(%A1, %A2) -> %D1 */'
197 "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
198 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
200 '2. cmp %S1, %S2\t\t\t/* prepare Max (%S1 - %S2), (%A1, %A2) */
201 if (mode_is_signed(get_irn_mode(n))) {
202 4. cmovl %D1, %S2\t\t\t/* %S1 is less %S2 */
205 4. cmovb %D1, %S2\t\t\t/* %S1 is below %S2 */
212 "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
213 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
215 '2. cmp %S1, %S2\t\t\t/* prepare Min (%S1 - %S2), (%A1, %A2) */
216 if (mode_is_signed(get_irn_mode(n))) {
217 2. cmovg %D1, %S2\t\t\t/* %S1 is greater %S2 */
220 2. cmova %D1, %S2, %D1\t\t\t/* %S1 is above %S2 */
225 # not commutative operations
229 "comment" => "construct Sub: Sub(a, b) = a - b",
230 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
231 "emit" => '. sub %ia32_emit_binop\t\t\t/* Sub(%A1, %A2) -> %D1 */'
236 "state" => "exc_pinned",
237 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "eax in_r1", "edx in_r3" ] },
239 ' if (mode_is_signed(get_irn_mode(n))) {
240 4. idiv %S2\t\t\t/* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
243 4. div %S2\t\t\t/* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
250 "comment" => "construct Shl: Shl(a, b) = a << b",
251 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r1" ] },
252 "emit" => '. shl %ia32_emit_binop\t\t\t/* Shl(%A1, %A2) -> %D1 */'
257 "comment" => "construct Shr: Shr(a, b) = a >> b",
258 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r1" ] },
259 "emit" => '. shr %ia32_emit_binop\t\t\t/* Shr(%A1, %A2) -> %D1 */'
264 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
265 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r1" ] },
266 "emit" => '. sar %ia32_emit_binop\t\t\t/* Shrs(%A1, %A2) -> %D1 */'
271 "comment" => "construct RotR: RotR(a, b) = a ROTR b",
272 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r1" ] },
273 "emit" => '. ror %ia32_emit_binop\t\t\t/* RotR(%A1, %A2) -> %D1 */'
278 "comment" => "construct RotL: RotL(a, b) = a ROTL b",
279 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r1" ] },
280 "emit" => '. rol %ia32_emit_binop\t\t\t/* RotL(%A1, %A2) -> %D1 */'
287 "comment" => "construct Minus: Minus(a) = -a",
288 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
289 "emit" => '. neg %ia32_emit_unop\t\t\t/* Neg(%A1) -> %D1, (%A1) */'
294 "comment" => "construct Increment: Inc(a) = a++",
295 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
296 "emit" => '. inc %ia32_emit_unop\t\t\t/* Inc(%S1) -> %D1, (%A1) */'
301 "comment" => "construct Decrement: Dec(a) = a--",
302 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
303 "emit" => '. dec %ia32_emit_unop\t\t\t/* Dec(%S1) -> %D1, (%A1) */'
308 "comment" => "construct Not: Not(a) = !a",
309 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
310 "emit" => '. not %ia32_emit_unop\t\t\t/* Not(%S1) -> %D1, (%A1) */'
317 "reg_req" => { "in" => [ "gp" ], "out" => [ "in_r1" ] },
318 "comment" => "construct Conv: Conv(a) = (conv)a"
322 "op_flags" => "L|X|Y",
323 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
324 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
328 "op_flags" => "L|X|Y",
329 "comment" => "construct switch",
330 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "none" ] },
336 "comment" => "represents an integer constant",
337 "reg_req" => { "out" => [ "gp" ] },
338 "emit" => '. mov %D1, %C\t\t\t/* Mov Const into register */',
341 if (attr_a->tp == attr_b->tp) {
342 if (attr_a->tp == ia32_SymConst) {
343 if (attr_a->sc == NULL || attr_b->sc == NULL)
346 return strcmp(attr_a->sc, attr_b->sc);
349 if (attr_a->tv == NULL || attr_b->tv == NULL)
352 if (tarval_cmp(attr_a->tv, attr_b->tv) == pn_Cmp_Eq)
365 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
366 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
367 "emit" => '. cdq\t\t\t/* sign extend EAX -> EDX:EAX, (%A1) */'
375 "state" => "exc_pinned",
376 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
377 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
378 "emit" => '. mov %D1, %ia32_emit_am\t\t\t/* Load((%A1)) -> %D1 */'
383 "state" => "exc_pinned",
384 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
385 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
386 "emit" => '. mov %ia32_emit_am, %S3\t\t\t/* Store(%A2) -> (%A1) */'
391 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
392 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
393 "emit" => '. lea %D1, %ia32_emit_am\t\t/* %D1 = %S1 + %S2 << %C + %O, (%A1, %A2) */'
399 "comment" => "constructs a Stack Parameter to retrieve a parameter from Stack",
400 "reg_req" => { "in" => [ "none" ], "out" => [ "gp" ] },
403 return (attr_a->pn_code != attr_b->pn_code);
409 "comment" => "constructs a Stack Argument to pass an argument on Stack",
410 "reg_req" => { "in" => [ "none", "gp" ], "out" => [ "none" ] },
413 return (attr_a->pn_code != attr_b->pn_code);
417 #--------------------------------------------------------#
420 # | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
421 # | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
422 # | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
423 # |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
424 #--------------------------------------------------------#
426 # commutative operations
430 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
431 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r1" ] },
432 "emit" => '. adds%M %ia32_emit_binop\t\t\t/* SSE Add(%A1, %A2) -> %D1 */'
437 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
438 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
439 "emit" => '. muls%M %ia32_emit_binop\t\t\t/* SSE Mul(%A1, %A2) -> %D1 */'
444 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
445 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
446 "emit" => '. maxs%M %ia32_emit_binop\t\t\t/* SSE Max(%A1, %A2) -> %D1 */'
451 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
452 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
453 "emit" => '. mins%M %ia32_emit_binop\t\t\t/* SSE Min(%A1, %A2) -> %D1 */'
458 "comment" => "construct SSE And: And(a, b) = a AND b",
459 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
460 "emit" => '. andp%M %ia32_emit_binop\t\t\t/* SSE And(%A3, %A4) -> %D1 */'
465 "comment" => "construct SSE Or: Or(a, b) = a OR b",
466 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
467 "emit" => '. orp%M %ia32_emit_binop\t\t\t/* SSE Or(%A3, %A4) -> %D1 */'
472 "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
473 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
474 "emit" => '. xorp%M %ia32_emit_binop\t\t\t/* SSE Xor(%A3, %A4) -> %D1 */'
477 # not commutative operations
481 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
482 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r1" ] },
483 "emit" => '. subs%M %ia32_emit_binop\t\t\t/* SSE Sub(%A1, %A2) -> %D1 */'
488 "comment" => "construct SSE Div: Div(a, b) = a / b",
489 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r1" ] },
490 "emit" => '. divs%M %ia32_emit_binop\t\t\t/* SSE Div(%A1, %A2) -> %D1 */'
497 "reg_req" => { "in" => [ "fp" ], "out" => [ "gp" ] },
498 "comment" => "construct Conv: Conv(a) = (conv)a"
502 "op_flags" => "L|X|Y",
503 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
504 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "none", "none" ] },
510 "comment" => "represents a SSE constant",
511 "reg_req" => { "out" => [ "fp" ] },
512 "emit" => '. mov%M %D1, %C\t\t\t/* Load fConst into register */',
515 if (attr_a->tp == attr_b->tp) {
516 if (attr_a->tp == ia32_SymConst) {
517 if (attr_a->sc == NULL || attr_b->sc == NULL)
520 return strcmp(attr_a->sc, attr_b->sc);
523 if (attr_a->tv == NULL || attr_b->tv == NULL)
526 if (tarval_cmp(attr_a->tv, attr_b->tv) == pn_Cmp_Eq)
542 "state" => "exc_pinned",
543 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
544 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "fp" ] },
545 "emit" => '. movs%M %D1, %ia32_emit_am\t\t\t/* Load((%A1)) -> %D1 */'
550 "state" => "exc_pinned",
551 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
552 "reg_req" => { "in" => [ "gp", "gp", "fp", "none" ] },
553 "emit" => '. movs%M %ia32_emit_am, %S3\t\t\t/* Store(%S3) -> (%A1) */'
559 "comment" => "constructs a Stack Parameter to retrieve a SSE parameter from Stack",
560 "reg_req" => { "in" => [ "none" ], "out" => [ "fp" ] },
563 return (attr_a->pn_code != attr_b->pn_code);
569 "comment" => "constructs a Stack Argument to pass an argument on Stack",
570 "reg_req" => { "in" => [ "none", "fp" ], "out" => [ "none" ] },
573 return (attr_a->pn_code != attr_b->pn_code);
581 "state" => "mem_pinned",
582 "arity" => "variable",
583 "comment" => "construct Call: Call(...)",
585 { "type" => "int", "name" => "n" },
586 { "type" => "ir_node **", "name" => "in" }
589 " if (!op_ia32_Call) assert(0);
590 return new_ir_node(db, irg, block, op_ia32_Call, mode_T, n, in);
599 "arity" => "variable",
600 "comment" => "construct Return: Return(...)",
602 { "type" => "int", "name" => "n" },
603 { "type" => "ir_node **", "name" => "in" }
606 " if (!op_ia32_Return) assert(0);
607 return new_ir_node(db, irg, block, op_ia32_Return, mode_X, n, in);
617 "comment" => "construct Alloca: allocate memory on Stack",
618 "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] }