3 # This is the specification for the ia32 assembler Firm-operations
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
8 # this string marks the beginning of a comment in emit
9 $comment_string = "/*";
11 # the number of additional opcodes you want to register
12 #$additional_opcodes = 0;
14 # The node description is done as a perl hash initializer with the
15 # following structure:
20 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
21 # "irn_flags" => "R|N|I"
22 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
23 # "state" => "floats|pinned|mem_pinned|exc_pinned",
25 # { "type" => "type 1", "name" => "name 1" },
26 # { "type" => "type 2", "name" => "name 2" },
29 # "comment" => "any comment for constructor",
30 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
31 # "cmp_attr" => "c source code for comparing node attributes",
32 # "emit" => "emit code with templates",
33 # "attr" => "attitional attribute arguments for constructor"
34 # "init_attr" => "emit attribute initialization template"
35 # "rd_constructor" => "c source code which constructs an ir_node"
38 # ... # (all nodes you need to describe)
40 # ); # close the %nodes initializer
42 # op_flags: flags for the operation, OPTIONAL (default is "N")
43 # the op_flags correspond to the firm irop_flags:
46 # C irop_flag_commutative
47 # X irop_flag_cfopcode
48 # I irop_flag_ip_cfopcode
51 # H irop_flag_highlevel
52 # c irop_flag_constlike
55 # irn_flags: special node flags, OPTIONAL (default is 0)
56 # following irn_flags are supported:
59 # I ignore for register allocation
61 # state: state of the operation, OPTIONAL (default is "floats")
63 # arity: arity of the operation, MUST NOT BE OMITTED
65 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
66 # are always the first 3 arguments and are always autmatically
68 # If this key is missing the following arguments will be created:
69 # for i = 1 .. arity: ir_node *op_i
72 # outs: if a node defines more than one output, the names of the projections
73 # nodes having outs having automatically the mode mode_T
75 # comment: OPTIONAL comment for the node constructor
77 # rd_constructor: for every operation there will be a
78 # new_rd_<arch>_<op-name> function with the arguments from above
79 # which creates the ir_node corresponding to the defined operation
80 # you can either put the complete source code of this function here
82 # This key is OPTIONAL. If omitted, the following constructor will
84 # if (!op_<arch>_<op-name>) assert(0);
88 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
91 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
95 # 1 - caller save (register must be saved by the caller of a function)
96 # 2 - callee save (register must be saved by the called function)
97 # 4 - ignore (do not assign this register)
98 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
101 { "name" => "eax", "type" => 1 },
102 { "name" => "edx", "type" => 1 },
103 { "name" => "ebx", "type" => 2 },
104 { "name" => "ecx", "type" => 1 },
105 { "name" => "esi", "type" => 2 },
106 { "name" => "edi", "type" => 2 },
107 # { "name" => "r11", "type" => 1 },
108 # { "name" => "r12", "type" => 1 },
109 # { "name" => "r13", "type" => 1 },
110 # { "name" => "r14", "type" => 1 },
111 # { "name" => "r15", "type" => 1 },
112 # { "name" => "r16", "type" => 1 },
113 # { "name" => "r17", "type" => 1 },
114 # { "name" => "r18", "type" => 1 },
115 # { "name" => "r19", "type" => 1 },
116 # { "name" => "r20", "type" => 1 },
117 # { "name" => "r21", "type" => 1 },
118 # { "name" => "r22", "type" => 1 },
119 # { "name" => "r23", "type" => 1 },
120 # { "name" => "r24", "type" => 1 },
121 # { "name" => "r25", "type" => 1 },
122 # { "name" => "r26", "type" => 1 },
123 # { "name" => "r27", "type" => 1 },
124 # { "name" => "r28", "type" => 1 },
125 # { "name" => "r29", "type" => 1 },
126 # { "name" => "r30", "type" => 1 },
127 # { "name" => "r31", "type" => 1 },
128 # { "name" => "r32", "type" => 1 },
129 { "name" => "ebp", "type" => 2 },
130 { "name" => "esp", "type" => 4 },
131 { "name" => "gp_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
132 { "name" => "gp_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
133 { "mode" => "mode_P" }
136 { "name" => "xmm0", "type" => 1 },
137 { "name" => "xmm1", "type" => 1 },
138 { "name" => "xmm2", "type" => 1 },
139 { "name" => "xmm3", "type" => 1 },
140 { "name" => "xmm4", "type" => 1 },
141 { "name" => "xmm5", "type" => 1 },
142 { "name" => "xmm6", "type" => 1 },
143 { "name" => "xmm7", "type" => 1 },
144 { "name" => "xmm_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
145 { "name" => "xmm_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
146 { "mode" => "mode_D" }
149 { "name" => "vf0", "type" => 1 },
150 { "name" => "vf1", "type" => 1 },
151 { "name" => "vf2", "type" => 1 },
152 { "name" => "vf3", "type" => 1 },
153 { "name" => "vf4", "type" => 1 },
154 { "name" => "vf5", "type" => 1 },
155 { "name" => "vf6", "type" => 1 },
156 { "name" => "vf7", "type" => 1 },
157 { "name" => "vfp_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
158 { "name" => "vfp_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
159 { "mode" => "mode_E" }
162 { "name" => "st0", "type" => 1 },
163 { "name" => "st1", "type" => 1 },
164 { "name" => "st2", "type" => 1 },
165 { "name" => "st3", "type" => 1 },
166 { "name" => "st4", "type" => 1 },
167 { "name" => "st5", "type" => 1 },
168 { "name" => "st6", "type" => 1 },
169 { "name" => "st7", "type" => 1 },
170 { "mode" => "mode_E" }
174 #--------------------------------------------------#
177 # _ __ _____ __ _ _ __ ___ _ __ ___ #
178 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
179 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
180 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
183 #--------------------------------------------------#
190 #-----------------------------------------------------------------#
193 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
194 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
195 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
196 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
199 #-----------------------------------------------------------------#
201 # commutative operations
204 # All nodes supporting Addressmode have 5 INs:
205 # 1 - base r1 == NoReg in case of no AM or no base
206 # 2 - index r2 == NoReg in case of no AM or no index
207 # 3 - op1 r3 == always present
208 # 4 - op2 r4 == NoReg in case of immediate operation
209 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
213 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
214 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
215 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
216 "emit" => '. add %ia32_emit_binop /* Add(%A3, %A4) -> %D1 */',
217 "outs" => [ "res", "M" ],
221 "comment" => "construct Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
222 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
223 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
224 "emit" => '. adc %ia32_emit_binop /* AddC(%A3, %A4) -> %D1 */',
225 "outs" => [ "res", "M" ],
231 "comment" => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
237 "comment" => "construct lowered Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
242 "comment" => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
243 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
244 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r3", "edx in_r4" ] },
245 "emit" => '. mul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */',
246 "outs" => [ "EAX", "EDX", "M" ],
251 "comment" => "construct lowered MulS: MulS(a, b) = MulS(b, a) = a * b",
252 "outs" => [ "EAX", "EDX", "M" ],
258 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
259 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
260 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
261 "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */',
262 "outs" => [ "res", "M" ],
267 "comment" => "construct lowered Mul: Mul(a, b) = Mul(b, a) = a * b",
271 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
273 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
274 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
275 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r3", "edx in_r4" ] },
276 "emit" => '. imul %ia32_emit_binop /* Mulh(%A1, %A2) -> %D1 */',
277 "outs" => [ "EAX", "EDX", "M" ],
282 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
283 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
284 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
285 "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */',
286 "outs" => [ "res", "M" ],
291 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
292 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
293 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
294 "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */',
295 "outs" => [ "res", "M" ],
300 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
301 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
302 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
303 "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */',
304 "outs" => [ "res", "M" ],
309 "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
310 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
312 '2. cmp %S1, %S2 /* prepare Max (%S1 - %S2), (%A1, %A2) */
313 if (mode_is_signed(get_irn_mode(n))) {
314 4. cmovl %D1, %S2 /* %S1 is less %S2 */
317 4. cmovb %D1, %S2 /* %S1 is below %S2 */
324 "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
325 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
327 '2. cmp %S1, %S2 /* prepare Min (%S1 - %S2), (%A1, %A2) */
328 if (mode_is_signed(get_irn_mode(n))) {
329 2. cmovg %D1, %S2 /* %S1 is greater %S2 */
332 2. cmova %D1, %S2, %D1 /* %S1 is above %S2 */
337 # not commutative operations
341 "comment" => "construct Sub: Sub(a, b) = a - b",
342 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
343 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
344 "emit" => '. sub %ia32_emit_binop /* Sub(%A3, %A4) -> %D1 */',
345 "outs" => [ "res", "M" ],
349 "comment" => "construct Sub with Carry: SubC(a, b) = a - b - carry",
350 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
351 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
352 "emit" => '. sbb %ia32_emit_binop /* SubC(%A3, %A4) -> %D1 */',
353 "outs" => [ "res", "M" ],
358 "comment" => "construct lowered Sub: Sub(a, b) = a - b",
363 "comment" => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
369 "state" => "exc_pinned",
370 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "eax in_r1", "edx in_r3" ] },
371 "attr" => "ia32_op_flavour_t dm_flav",
372 "init_attr" => " attr->data.op_flav = dm_flav;",
373 "cmp_attr" => " return attr_a->data.op_flav != attr_b->data.op_flav;\n",
375 ' if (mode_is_signed(get_irn_mode(n))) {
376 4. idiv %S2 /* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
379 4. div %S2 /* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
382 "outs" => [ "div_res", "mod_res", "M" ],
387 "comment" => "construct Shl: Shl(a, b) = a << b",
388 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
389 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
390 "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */',
391 "outs" => [ "res", "M" ],
395 "comment" => "construct lowered Shl: Shl(a, b) = a << b",
401 "comment" => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
402 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
403 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r5" ] },
406 if (get_ia32_immop_type(n) == ia32_ImmNone) {
407 if (get_ia32_op_type(n) == ia32_AddrModeD) {
408 4. shld %ia32_emit_am, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
411 4. shld %S3, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
415 if (get_ia32_op_type(n) == ia32_AddrModeD) {
416 4. shld %ia32_emit_am, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
419 4. shld %S3, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
423 "outs" => [ "res", "M" ],
427 "comment" => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
433 "comment" => "construct Shr: Shr(a, b) = a >> b",
434 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
435 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
436 "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */',
437 "outs" => [ "res", "M" ],
441 "comment" => "construct lowered Shr: Shr(a, b) = a << b",
447 "comment" => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
448 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
449 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r5" ] },
452 if (get_ia32_immop_type(n) == ia32_ImmNone) {
453 if (get_ia32_op_type(n) == ia32_AddrModeD) {
454 4. shrd %ia32_emit_am, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
457 4. shrd %S3, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
461 if (get_ia32_op_type(n) == ia32_AddrModeD) {
462 4. shrd %ia32_emit_am, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
465 4. shrd %S3, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
469 "outs" => [ "res", "M" ],
473 "comment" => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
479 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
480 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
481 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
482 "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */',
483 "outs" => [ "res", "M" ],
487 "comment" => "construct lowered Shrs: Shrs(a, b) = a << b",
493 "comment" => "construct RotR: RotR(a, b) = a ROTR b",
494 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
495 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
496 "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */',
497 "outs" => [ "res", "M" ],
502 "comment" => "construct RotL: RotL(a, b) = a ROTL b",
503 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
504 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
505 "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */',
506 "outs" => [ "res", "M" ],
513 "comment" => "construct Minus: Minus(a) = -a",
514 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
515 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
516 "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */',
517 "outs" => [ "res", "M" ],
522 "comment" => "construct Increment: Inc(a) = a++",
523 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
524 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
525 "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */',
526 "outs" => [ "res", "M" ],
531 "comment" => "construct Decrement: Dec(a) = a--",
532 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
533 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
534 "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */',
535 "outs" => [ "res", "M" ],
540 "comment" => "construct Not: Not(a) = !a",
541 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
542 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
543 "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */',
544 "outs" => [ "res", "M" ],
550 "op_flags" => "L|X|Y",
551 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
552 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
553 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
554 "outs" => [ "false", "true" ],
558 "op_flags" => "L|X|Y",
559 "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
560 "reg_req" => { "in" => [ "gp", "gp" ] },
561 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
562 "outs" => [ "false", "true" ],
566 "op_flags" => "L|X|Y",
567 "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
568 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
569 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
570 "outs" => [ "false", "true" ],
574 "op_flags" => "L|X|Y",
575 "comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
576 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
577 "reg_req" => { "in" => [ "gp", "gp" ] },
581 "op_flags" => "L|X|Y",
582 "comment" => "construct switch",
583 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
584 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
590 "comment" => "represents an integer constant",
591 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
592 "reg_req" => { "in" => [ "none" ], "out" => [ "gp" ] },
597 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
598 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
599 "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */',
600 "outs" => [ "EAX", "EDX" ],
608 "state" => "exc_pinned",
609 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
610 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
611 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
613 ' if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) {
614 4. mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
617 4. mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
620 "outs" => [ "res", "M" ],
625 "state" => "exc_pinned",
626 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
627 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
628 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
629 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
635 "state" => "exc_pinned",
636 "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
637 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
638 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
639 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
645 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
646 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
647 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
648 "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */'
652 "comment" => "push a gp register on the stack",
653 "reg_req" => { "in" => [ "esp", "gp", "none" ], "out" => [ "esp" ] },
655 if (get_ia32_id_cnst(n)) {
656 if (get_ia32_immop_type(n) == ia32_ImmConst) {
657 . push %C /* Push(%A2) */
659 . push OFFSET FLAT:%C /* Push(%A2) */
663 . push %S2 /* Push(%A2) */
666 "outs" => [ "stack", "M" ],
670 "comment" => "pop a gp register from the stack",
671 "reg_req" => { "in" => [ "esp", "none" ], "out" => [ "gp", "esp" ] },
672 "emit" => '. pop %D1 /* Pop -> %D1 */',
673 "outs" => [ "res", "stack", "M" ],
677 "comment" => "create stack frame",
678 "reg_req" => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] },
679 "emit" => '. enter /* Enter */',
680 "outs" => [ "frame", "stack", "M" ],
684 "comment" => "destroy stack frame",
685 "reg_req" => { "in" => [ "esp", "ebp" ], "out" => [ "ebp", "esp" ] },
686 "emit" => '. leave /* Leave */',
687 "outs" => [ "frame", "stack", "M" ],
690 #-----------------------------------------------------------------------------#
691 # _____ _____ ______ __ _ _ _ #
692 # / ____/ ____| ____| / _| | | | | | #
693 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
694 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
695 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
696 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
697 #-----------------------------------------------------------------------------#
699 # commutative operations
703 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
704 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
705 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
706 "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */',
707 "outs" => [ "res", "M" ],
712 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
713 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
714 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
715 "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */',
716 "outs" => [ "res", "M" ],
721 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
722 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
723 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
724 "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */',
725 "outs" => [ "res", "M" ],
730 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
731 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
732 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
733 "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */',
734 "outs" => [ "res", "M" ],
739 "comment" => "construct SSE And: And(a, b) = a AND b",
740 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
741 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
742 "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */',
743 "outs" => [ "res", "M" ],
748 "comment" => "construct SSE Or: Or(a, b) = a OR b",
749 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
750 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
751 "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */',
752 "outs" => [ "res", "M" ],
757 "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
758 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
759 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
760 "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */',
761 "outs" => [ "res", "M" ],
764 # not commutative operations
768 "comment" => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
769 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
770 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
771 "emit" => '. andnp%M %ia32_emit_binop /* SSE AndNot(%A3, %A4) -> %D1 */',
772 "outs" => [ "res", "M" ],
777 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
778 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
779 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
780 "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */',
781 "outs" => [ "res", "M" ],
786 "comment" => "construct SSE Div: Div(a, b) = a / b",
787 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
788 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
789 "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */',
790 "outs" => [ "res", "M" ],
797 "comment" => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
798 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
799 "outs" => [ "res", "M" ],
803 "op_flags" => "L|X|Y",
804 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
805 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
806 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
807 "outs" => [ "false", "true" ],
813 "comment" => "represents a SSE constant",
814 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
815 "reg_req" => { "in" => [ "none" ], "out" => [ "xmm" ] },
816 "emit" => '. movs%M %D1, %C /* Load fConst into register */',
824 "state" => "exc_pinned",
825 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
826 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
827 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm" ] },
828 "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */',
829 "outs" => [ "res", "M" ],
834 "state" => "exc_pinned",
835 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
836 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
837 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
838 "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */',
847 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
848 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "none" ] },
854 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
855 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
856 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "none" ] },
862 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
863 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
864 "comment" => "construct Conv Int -> Int",
865 "outs" => [ "res", "M" ],
869 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
870 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
871 "comment" => "construct Conv Int -> Int",
872 "outs" => [ "res", "M" ],
876 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
877 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
878 "comment" => "construct Conv Int -> Floating Point",
879 "outs" => [ "res", "M" ],
883 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
884 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
885 "comment" => "construct Conv Floating Point -> Int",
886 "outs" => [ "res", "M" ],
890 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
891 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
892 "comment" => "construct Conv Floating Point -> Floating Point",
893 "outs" => [ "res", "M" ],
898 "comment" => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
899 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "in_r4" ] }
904 "comment" => "check if Psi condition tree evaluates to true and move result accordingly",
905 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r3" ] }
910 "comment" => "construct Conditional Move: SSE Compare + int CMov ",
911 "reg_req" => { "in" => [ "xmm", "xmm", "gp", "gp" ], "out" => [ "in_r4" ] }
916 "comment" => "construct Conditional Move: x87 Compare + int CMov",
917 "reg_req" => { "in" => [ "vfp", "vfp", "gp", "gp" ], "out" => [ "in_r4" ] }
922 "comment" => "construct Set: Set(sel) == sel ? 1 : 0",
923 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
924 "outs" => [ "res", "M" ],
929 "comment" => "check if Psi condition tree evaluates to true and set result accordingly",
930 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax ebx ecx edx" ] },
935 "comment" => "construct Set: SSE Compare + int Set",
936 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
937 "outs" => [ "res", "M" ],
942 "comment" => "construct Set: x87 Compare + int Set",
943 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
944 "outs" => [ "res", "M" ],
949 "comment" => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
950 "reg_req" => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] }
953 #----------------------------------------------------------#
955 # (_) | | | | / _| | | | #
956 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
957 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
958 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
959 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
961 # _ __ ___ __| | ___ ___ #
962 # | '_ \ / _ \ / _` |/ _ \/ __| #
963 # | | | | (_) | (_| | __/\__ \ #
964 # |_| |_|\___/ \__,_|\___||___/ #
965 #----------------------------------------------------------#
969 "comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
970 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
971 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
972 "outs" => [ "res", "M" ],
977 "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a + b",
978 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
979 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
980 "outs" => [ "res", "M" ],
985 "comment" => "virtual fp Sub: Sub(a, b) = a - b",
986 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
987 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
988 "outs" => [ "res", "M" ],
992 "comment" => "virtual fp Div: Div(a, b) = a / b",
993 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
994 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
995 "outs" => [ "res", "M" ],
1000 "comment" => "virtual fp Abs: Abs(a) = |a|",
1001 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1006 "comment" => "virtual fp Chs: Chs(a) = -a",
1007 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1012 "comment" => "virtual fp Sin: Sin(a) = sin(a)",
1013 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1018 "comment" => "virtual fp Cos: Cos(a) = cos(a)",
1019 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1024 "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
1025 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1028 # virtual Load and Store
1031 "op_flags" => "L|F",
1033 "state" => "exc_pinned",
1034 "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
1035 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1036 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1037 "outs" => [ "res", "M" ],
1041 "op_flags" => "L|F",
1042 "state" => "exc_pinned",
1043 "comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
1044 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1045 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1053 "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1054 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1055 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1056 "outs" => [ "res", "M" ],
1060 "comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1061 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1062 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1070 "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg",
1071 "reg_req" => { "out" => [ "vfp" ] },
1076 "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg",
1077 "reg_req" => { "out" => [ "vfp" ] },
1082 "comment" => "virtual fp Load pi: Ld pi -> reg",
1083 "reg_req" => { "out" => [ "vfp" ] },
1088 "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg",
1089 "reg_req" => { "out" => [ "vfp" ] },
1094 "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg",
1095 "reg_req" => { "out" => [ "vfp" ] },
1100 "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg",
1101 "reg_req" => { "out" => [ "vfp" ] },
1106 "comment" => "virtual fp Load ld e: Ld ld e -> reg",
1107 "reg_req" => { "out" => [ "vfp" ] },
1113 "init_attr" => " set_ia32_ls_mode(res, mode);",
1114 "comment" => "represents a virtual floating point constant",
1115 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1116 "reg_req" => { "in" => [ "none" ], "out" => [ "vfp" ] },
1122 "op_flags" => "L|X|Y",
1123 "comment" => "represents a virtual floating point compare",
1124 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1125 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] },
1126 "outs" => [ "false", "true", "temp_reg_eax" ],
1129 #------------------------------------------------------------------------#
1130 # ___ _____ __ _ _ _ #
1131 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1132 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1133 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1134 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1135 #------------------------------------------------------------------------#
1139 "rd_constructor" => "NONE",
1140 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1142 "emit" => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */',
1147 "rd_constructor" => "NONE",
1148 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1150 "emit" => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */',
1155 "rd_constructor" => "NONE",
1156 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1158 "emit" => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */',
1163 "rd_constructor" => "NONE",
1164 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1166 "emit" => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */',,
1171 "rd_constructor" => "NONE",
1172 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1174 "emit" => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */',
1179 "rd_constructor" => "NONE",
1180 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1182 "emit" => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */',
1187 "rd_constructor" => "NONE",
1189 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1191 "emit" => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */',
1196 "rd_constructor" => "NONE",
1198 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1200 "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */',
1205 "rd_constructor" => "NONE",
1206 "comment" => "x87 fp Div: Div(a, b) = a / b",
1208 "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */',
1213 "rd_constructor" => "NONE",
1214 "comment" => "x87 fp Div: Div(a, b) = a / b",
1216 "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */',
1221 "rd_constructor" => "NONE",
1222 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1224 "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */',
1229 "rd_constructor" => "NONE",
1230 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1232 "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */',
1237 "rd_constructor" => "NONE",
1238 "comment" => "x87 fp Abs: Abs(a) = |a|",
1240 "emit" => '. fabs /* x87 fabs(%S1) -> %D1 */',
1245 "rd_constructor" => "NONE",
1246 "comment" => "x87 fp Chs: Chs(a) = -a",
1248 "emit" => '. fchs /* x87 fchs(%S1) -> %D1 */',
1253 "rd_constructor" => "NONE",
1254 "comment" => "x87 fp Sin: Sin(a) = sin(a)",
1256 "emit" => '. fsin /* x87 sin(%S1) -> %D1 */',
1261 "rd_constructor" => "NONE",
1262 "comment" => "x87 fp Cos: Cos(a) = cos(a)",
1264 "emit" => '. fcos /* x87 cos(%S1) -> %D1 */',
1269 "rd_constructor" => "NONE",
1270 "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1272 "emit" => '. fsqrt $ /* x87 sqrt(%S1) -> %D1 */',
1275 # x87 Load and Store
1278 "rd_constructor" => "NONE",
1279 "op_flags" => "R|L|F",
1280 "state" => "exc_pinned",
1281 "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1283 "emit" => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */',
1287 "rd_constructor" => "NONE",
1288 "op_flags" => "R|L|F",
1289 "state" => "exc_pinned",
1290 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1292 "emit" => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */',
1296 "rd_constructor" => "NONE",
1297 "op_flags" => "R|L|F",
1298 "state" => "exc_pinned",
1299 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1301 "emit" => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */',
1309 "rd_constructor" => "NONE",
1310 "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1312 "emit" => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */',
1317 "rd_constructor" => "NONE",
1318 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1320 "emit" => '. fist %ia32_emit_am /* integer Store(%A3) -> (%A1) */',
1325 "rd_constructor" => "NONE",
1326 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1328 "emit" => '. fistp %ia32_emit_am /* integer Store(%A3) -> (%A1) and pop */',
1335 "rd_constructor" => "NONE",
1336 "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
1338 "emit" => '. fldz /* x87 0.0 -> %D1 */',
1343 "rd_constructor" => "NONE",
1344 "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
1346 "emit" => '. fld1 /* x87 1.0 -> %D1 */',
1351 "rd_constructor" => "NONE",
1352 "comment" => "x87 fp Load pi: Ld pi -> reg",
1354 "emit" => '. fldpi /* x87 pi -> %D1 */',
1359 "rd_constructor" => "NONE",
1360 "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
1362 "emit" => '. fldln2 /* x87 ln(2) -> %D1 */',
1367 "rd_constructor" => "NONE",
1368 "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
1370 "emit" => '. fldlg2 /* x87 log(2) -> %D1 */',
1375 "rd_constructor" => "NONE",
1376 "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
1378 "emit" => '. fldll2t /* x87 ld(10) -> %D1 */',
1383 "rd_constructor" => "NONE",
1384 "comment" => "x87 fp Load ld e: Ld ld e -> reg",
1386 "emit" => '. fldl2e /* x87 ld(e) -> %D1 */',
1390 "op_flags" => "R|c",
1392 "rd_constructor" => "NONE",
1393 "comment" => "represents a x87 constant",
1394 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1395 "reg_req" => { "out" => [ "st" ] },
1396 "emit" => '. fld %ia32_emit_adr /* Load fConst into register -> %D1 */',
1400 # Note that it is NEVER allowed to do CSE on these nodes
1403 "op_flags" => "R|K",
1404 "comment" => "x87 stack exchange",
1405 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1406 "cmp_attr" => " return 1;\n",
1407 "emit" => '. fxch %X1 /* x87 swap %X1, %X3 */',
1412 "comment" => "x87 stack push",
1413 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1414 "cmp_attr" => " return 1;\n",
1415 "emit" => '. fld %X1 /* x87 push %X1 */',
1419 "op_flags" => "R|K",
1420 "comment" => "x87 stack pop",
1421 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1422 "cmp_attr" => " return 1;\n",
1423 "emit" => '. fstp %X1 /* x87 pop %X1 */',
1429 "op_flags" => "L|X|Y",
1430 "comment" => "floating point compare",
1431 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1436 "op_flags" => "L|X|Y",
1437 "comment" => "floating point compare and pop",
1438 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1443 "op_flags" => "L|X|Y",
1444 "comment" => "floating point compare and pop twice",
1445 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1450 "op_flags" => "L|X|Y",
1451 "comment" => "floating point compare reverse",
1452 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1457 "op_flags" => "L|X|Y",
1458 "comment" => "floating point compare reverse and pop",
1459 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1464 "op_flags" => "L|X|Y",
1465 "comment" => "floating point compare reverse and pop twice",
1466 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",