3 # This is the specification for the ia32 assembler Firm-operations
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
8 # this string marks the beginning of a comment in emit
9 $comment_string = "/*";
11 # the number of additional opcodes you want to register
12 #$additional_opcodes = 0;
14 # The node description is done as a perl hash initializer with the
15 # following structure:
20 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
21 # "irn_flags" => "R|N|I"
22 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
23 # "state" => "floats|pinned|mem_pinned|exc_pinned",
25 # { "type" => "type 1", "name" => "name 1" },
26 # { "type" => "type 2", "name" => "name 2" },
29 # "comment" => "any comment for constructor",
30 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
31 # "cmp_attr" => "c source code for comparing node attributes",
32 # "emit" => "emit code with templates",
33 # "attr" => "attitional attribute arguments for constructor"
34 # "init_attr" => "emit attribute initialization template"
35 # "rd_constructor" => "c source code which constructs an ir_node"
38 # ... # (all nodes you need to describe)
40 # ); # close the %nodes initializer
42 # op_flags: flags for the operation, OPTIONAL (default is "N")
43 # the op_flags correspond to the firm irop_flags:
46 # C irop_flag_commutative
47 # X irop_flag_cfopcode
48 # I irop_flag_ip_cfopcode
51 # H irop_flag_highlevel
52 # c irop_flag_constlike
55 # irn_flags: special node flags, OPTIONAL (default is 0)
56 # following irn_flags are supported:
59 # I ignore for register allocation
61 # state: state of the operation, OPTIONAL (default is "floats")
63 # arity: arity of the operation, MUST NOT BE OMITTED
65 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
66 # are always the first 3 arguments and are always autmatically
68 # If this key is missing the following arguments will be created:
69 # for i = 1 .. arity: ir_node *op_i
72 # outs: if a node defines more than one output, the names of the projections
73 # nodes having outs having automatically the mode mode_T
75 # comment: OPTIONAL comment for the node constructor
77 # rd_constructor: for every operation there will be a
78 # new_rd_<arch>_<op-name> function with the arguments from above
79 # which creates the ir_node corresponding to the defined operation
80 # you can either put the complete source code of this function here
82 # This key is OPTIONAL. If omitted, the following constructor will
84 # if (!op_<arch>_<op-name>) assert(0);
88 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
91 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
95 # 1 - caller save (register must be saved by the caller of a function)
96 # 2 - callee save (register must be saved by the called function)
97 # 4 - ignore (do not assign this register)
98 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
101 { "name" => "eax", "type" => 1 },
102 { "name" => "edx", "type" => 1 },
103 { "name" => "ebx", "type" => 2 },
104 { "name" => "ecx", "type" => 1 },
105 { "name" => "esi", "type" => 2 },
106 { "name" => "edi", "type" => 2 },
107 { "name" => "ebp", "type" => 2 },
108 { "name" => "esp", "type" => 4 },
109 { "name" => "gp_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
110 { "name" => "gp_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
111 { "mode" => "mode_P" }
114 { "name" => "xmm0", "type" => 1 },
115 { "name" => "xmm1", "type" => 1 },
116 { "name" => "xmm2", "type" => 1 },
117 { "name" => "xmm3", "type" => 1 },
118 { "name" => "xmm4", "type" => 1 },
119 { "name" => "xmm5", "type" => 1 },
120 { "name" => "xmm6", "type" => 1 },
121 { "name" => "xmm7", "type" => 1 },
122 { "name" => "xmm_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
123 { "name" => "xmm_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
124 { "mode" => "mode_D" }
127 { "name" => "vf0", "type" => 1 },
128 { "name" => "vf1", "type" => 1 },
129 { "name" => "vf2", "type" => 1 },
130 { "name" => "vf3", "type" => 1 },
131 { "name" => "vf4", "type" => 1 },
132 { "name" => "vf5", "type" => 1 },
133 { "name" => "vf6", "type" => 1 },
134 { "name" => "vf7", "type" => 1 },
135 { "name" => "vfp_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
136 { "name" => "vfp_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
137 { "mode" => "mode_E" }
140 { "name" => "st0", "type" => 1 },
141 { "name" => "st1", "type" => 1 },
142 { "name" => "st2", "type" => 1 },
143 { "name" => "st3", "type" => 1 },
144 { "name" => "st4", "type" => 1 },
145 { "name" => "st5", "type" => 1 },
146 { "name" => "st6", "type" => 1 },
147 { "name" => "st7", "type" => 1 },
148 { "mode" => "mode_E" }
152 #--------------------------------------------------#
155 # _ __ _____ __ _ _ __ ___ _ __ ___ #
156 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
157 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
158 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
161 #--------------------------------------------------#
168 #-----------------------------------------------------------------#
171 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
172 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
173 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
174 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
177 #-----------------------------------------------------------------#
179 # commutative operations
182 # All nodes supporting Addressmode have 5 INs:
183 # 1 - base r1 == NoReg in case of no AM or no base
184 # 2 - index r2 == NoReg in case of no AM or no index
185 # 3 - op1 r3 == always present
186 # 4 - op2 r4 == NoReg in case of immediate operation
187 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
191 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
192 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
193 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
194 "emit" => '. add %ia32_emit_binop /* Add(%A1, %A2) -> %D1 */',
195 "outs" => [ "res", "M" ],
200 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
201 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
202 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
203 "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */',
204 "outs" => [ "res", "M" ],
207 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
209 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
210 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
211 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r3", "edx in_r4" ] },
212 "emit" => '. imul %ia32_emit_binop /* Mulh(%A1, %A2) -> %D1 */',
213 "outs" => [ "EAX", "EDX", "M" ],
218 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
219 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
220 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
221 "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */',
222 "outs" => [ "res", "M" ],
227 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
228 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
229 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
230 "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */',
231 "outs" => [ "res", "M" ],
236 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
237 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
238 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
239 "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */',
240 "outs" => [ "res", "M" ],
245 "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
246 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
248 '2. cmp %S1, %S2 /* prepare Max (%S1 - %S2), (%A1, %A2) */
249 if (mode_is_signed(get_irn_mode(n))) {
250 4. cmovl %D1, %S2 /* %S1 is less %S2 */
253 4. cmovb %D1, %S2 /* %S1 is below %S2 */
260 "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
261 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
263 '2. cmp %S1, %S2 /* prepare Min (%S1 - %S2), (%A1, %A2) */
264 if (mode_is_signed(get_irn_mode(n))) {
265 2. cmovg %D1, %S2 /* %S1 is greater %S2 */
268 2. cmova %D1, %S2, %D1 /* %S1 is above %S2 */
275 "comment" => "construct Mux: Mux(sel, a, b) == sel ? a : b",
276 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r2" ] },
278 '. cmp %S1, 0 /* compare Sel for CMov (%A2, %A3) */
279 . cmovne %D1, %S3 /* sel == true -> return %S3 */
283 # not commutative operations
287 "comment" => "construct Sub: Sub(a, b) = a - b",
288 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
289 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
290 "emit" => '. sub %ia32_emit_binop /* Sub(%A1, %A2) -> %D1 */',
291 "outs" => [ "res", "M" ],
296 "state" => "exc_pinned",
297 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "eax in_r1", "edx in_r3" ] },
298 "attr" => "ia32_op_flavour_t dm_flav",
299 "init_attr" => " attr->data.op_flav = dm_flav;",
300 "cmp_attr" => " return attr_a->data.op_flav != attr_b->data.op_flav;\n",
302 ' if (mode_is_signed(get_irn_mode(n))) {
303 4. idiv %S2 /* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
306 4. div %S2 /* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
309 "outs" => [ "div_res", "mod_res", "M" ],
314 "comment" => "construct Shl: Shl(a, b) = a << b",
315 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
316 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
317 "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */',
318 "outs" => [ "res", "M" ],
323 "comment" => "construct Shr: Shr(a, b) = a >> b",
324 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
325 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
326 "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */',
327 "outs" => [ "res", "M" ],
332 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
333 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
334 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
335 "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */',
336 "outs" => [ "res", "M" ],
341 "comment" => "construct RotR: RotR(a, b) = a ROTR b",
342 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
343 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
344 "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */',
345 "outs" => [ "res", "M" ],
350 "comment" => "construct RotL: RotL(a, b) = a ROTL b",
351 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
352 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
353 "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */',
354 "outs" => [ "res", "M" ],
361 "comment" => "construct Minus: Minus(a) = -a",
362 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
363 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
364 "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */',
365 "outs" => [ "res", "M" ],
370 "comment" => "construct Increment: Inc(a) = a++",
371 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
372 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
373 "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */',
374 "outs" => [ "res", "M" ],
379 "comment" => "construct Decrement: Dec(a) = a--",
380 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
381 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
382 "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */',
383 "outs" => [ "res", "M" ],
388 "comment" => "construct Not: Not(a) = !a",
389 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
390 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
391 "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */',
392 "outs" => [ "res", "M" ],
398 "op_flags" => "L|X|Y",
399 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
400 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
401 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
402 "outs" => [ "false", "true" ],
406 "op_flags" => "L|X|Y",
407 "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
408 "reg_req" => { "in" => [ "gp", "gp" ] },
409 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
410 "outs" => [ "false", "true" ],
414 "op_flags" => "L|X|Y",
415 "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
416 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
417 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
418 "outs" => [ "false", "true" ],
422 "op_flags" => "L|X|Y",
423 "comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
424 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
425 "reg_req" => { "in" => [ "gp", "gp" ] },
429 "op_flags" => "L|X|Y",
430 "comment" => "construct switch",
431 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
432 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
438 "comment" => "represents an integer constant",
439 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
440 "reg_req" => { "in" => [ "none" ], "out" => [ "gp" ] },
445 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
446 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
447 "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */',
448 "outs" => [ "EAX", "EDX" ],
456 "state" => "exc_pinned",
457 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
458 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
459 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
461 ' if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) {
462 4. mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
465 4. mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
468 "outs" => [ "res", "M" ],
473 "state" => "exc_pinned",
474 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
475 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
476 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
477 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
483 "state" => "exc_pinned",
484 "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
485 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
486 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
487 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
493 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
494 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
495 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
496 "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */'
500 "comment" => "push a gp register on the stack",
501 "reg_req" => { "in" => [ "esp", "gp", "none" ], "out" => [ "esp" ] },
503 if (get_ia32_id_cnst(n)) {
504 if (get_ia32_immop_type(n) == ia32_ImmConst) {
505 . push %C /* Push(%A2) */
507 . push OFFSET FLAT:%C /* Push(%A2) */
511 . push %S2 /* Push(%A2) */
514 "outs" => [ "stack", "M" ],
518 "comment" => "pop a gp register from the stack",
519 "reg_req" => { "in" => [ "esp", "none" ], "out" => [ "gp", "esp" ] },
520 "emit" => '. pop %D1 /* Pop -> %D1 */',
521 "outs" => [ "res", "stack", "M" ],
525 "comment" => "create stack frame",
526 "reg_req" => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] },
527 "emit" => '. enter /* Enter */',
528 "outs" => [ "frame", "stack", "M" ],
532 "comment" => "destroy stack frame",
533 "reg_req" => { "in" => [ "esp", "ebp" ], "out" => [ "ebp", "esp" ] },
534 "emit" => '. leave /* Leave */',
535 "outs" => [ "frame", "stack", "M" ],
538 #-----------------------------------------------------------------------------#
539 # _____ _____ ______ __ _ _ _ #
540 # / ____/ ____| ____| / _| | | | | | #
541 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
542 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
543 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
544 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
545 #-----------------------------------------------------------------------------#
547 # commutative operations
551 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
552 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
553 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
554 "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */',
555 "outs" => [ "res", "M" ],
560 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
561 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
562 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
563 "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */',
564 "outs" => [ "res", "M" ],
569 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
570 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
571 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
572 "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */',
573 "outs" => [ "res", "M" ],
578 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
579 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
580 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
581 "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */',
582 "outs" => [ "res", "M" ],
587 "comment" => "construct SSE And: And(a, b) = a AND b",
588 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
589 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
590 "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */',
591 "outs" => [ "res", "M" ],
596 "comment" => "construct SSE Or: Or(a, b) = a OR b",
597 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
598 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
599 "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */',
600 "outs" => [ "res", "M" ],
605 "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
606 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
607 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
608 "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */',
609 "outs" => [ "res", "M" ],
612 # not commutative operations
616 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
617 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
618 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
619 "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */',
620 "outs" => [ "res", "M" ],
625 "comment" => "construct SSE Div: Div(a, b) = a / b",
626 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
627 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
628 "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */',
629 "outs" => [ "res", "M" ],
635 "op_flags" => "L|X|Y",
636 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
637 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
638 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
639 "outs" => [ "false", "true" ],
645 "comment" => "represents a SSE constant",
646 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
647 "reg_req" => { "in" => [ "none" ], "out" => [ "xmm" ] },
648 "emit" => '. mov%M %D1, %C /* Load fConst into register */',
656 "state" => "exc_pinned",
657 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
658 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
659 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm" ] },
660 "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */',
661 "outs" => [ "res", "M" ],
666 "state" => "exc_pinned",
667 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
668 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
669 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
670 "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */',
679 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
680 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "none" ] },
686 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
687 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
688 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "none" ] },
694 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
695 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
696 "comment" => "construct Conv Int -> Int",
697 "outs" => [ "res", "M" ],
701 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
702 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
703 "comment" => "construct Conv Int -> Int",
704 "outs" => [ "res", "M" ],
708 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
709 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
710 "comment" => "construct Conv Int -> Floating Point",
711 "outs" => [ "res", "M" ],
715 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
716 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
717 "comment" => "construct Conv Floating Point -> Int",
718 "outs" => [ "res", "M" ],
722 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
723 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
724 "comment" => "construct Conv Floating Point -> Floating Point",
725 "outs" => [ "res", "M" ],
728 #----------------------------------------------------------#
730 # (_) | | | | / _| | | | #
731 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
732 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
733 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
734 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
736 # _ __ ___ __| | ___ ___ #
737 # | '_ \ / _ \ / _` |/ _ \/ __| #
738 # | | | | (_) | (_| | __/\__ \ #
739 # |_| |_|\___/ \__,_|\___||___/ #
740 #----------------------------------------------------------#
744 "comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
745 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
746 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
747 "outs" => [ "res", "M" ],
752 "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a + b",
753 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
754 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
755 "outs" => [ "res", "M" ],
760 "comment" => "virtual fp Sub: Sub(a, b) = a - b",
761 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
762 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
763 "outs" => [ "res", "M" ],
767 "comment" => "virtual fp Div: Div(a, b) = a / b",
768 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
769 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
770 "outs" => [ "res", "M" ],
775 "comment" => "virtual fp Abs: Abs(a) = |a|",
776 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
781 "comment" => "virtual fp Chs: Chs(a) = -a",
782 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
787 "comment" => "virtual fp Sin: Sin(a) = sin(a)",
788 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
793 "comment" => "virtual fp Cos: Cos(a) = cos(a)",
794 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
799 "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
800 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
803 # virtual Load and Store
808 "state" => "exc_pinned",
809 "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
810 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
811 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
812 "outs" => [ "res", "M" ],
817 "state" => "exc_pinned",
818 "comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
819 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
820 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
828 "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
829 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
830 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
831 "outs" => [ "res", "M" ],
835 "comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
836 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
837 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
845 "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg",
846 "reg_req" => { "out" => [ "vfp" ] },
851 "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg",
852 "reg_req" => { "out" => [ "vfp" ] },
857 "comment" => "virtual fp Load pi: Ld pi -> reg",
858 "reg_req" => { "out" => [ "vfp" ] },
863 "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg",
864 "reg_req" => { "out" => [ "vfp" ] },
869 "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg",
870 "reg_req" => { "out" => [ "vfp" ] },
875 "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg",
876 "reg_req" => { "out" => [ "vfp" ] },
881 "comment" => "virtual fp Load ld e: Ld ld e -> reg",
882 "reg_req" => { "out" => [ "vfp" ] },
888 "comment" => "represents a virtual floating point constant",
889 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
890 "reg_req" => { "in" => [ "none" ], "out" => [ "vfp" ] },
896 "op_flags" => "L|X|Y",
897 "comment" => "represents a virtual floating point compare",
898 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
899 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] },
900 "outs" => [ "false", "true", "temp_reg_eax" ],
903 #------------------------------------------------------------------------#
904 # ___ _____ __ _ _ _ #
905 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
906 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
907 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
908 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
909 #------------------------------------------------------------------------#
913 "rd_constructor" => "NONE",
914 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
916 "emit" => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */',
921 "rd_constructor" => "NONE",
922 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
924 "emit" => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */',
929 "rd_constructor" => "NONE",
930 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
932 "emit" => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */',
937 "rd_constructor" => "NONE",
938 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
940 "emit" => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */',,
945 "rd_constructor" => "NONE",
946 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
948 "emit" => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */',
953 "rd_constructor" => "NONE",
954 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
956 "emit" => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */',
961 "rd_constructor" => "NONE",
963 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
965 "emit" => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */',
970 "rd_constructor" => "NONE",
972 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
974 "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */',
979 "rd_constructor" => "NONE",
980 "comment" => "x87 fp Div: Div(a, b) = a / b",
982 "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */',
987 "rd_constructor" => "NONE",
988 "comment" => "x87 fp Div: Div(a, b) = a / b",
990 "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */',
995 "rd_constructor" => "NONE",
996 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
998 "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */',
1003 "rd_constructor" => "NONE",
1004 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1006 "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */',
1011 "rd_constructor" => "NONE",
1012 "comment" => "x87 fp Abs: Abs(a) = |a|",
1014 "emit" => '. fabs /* x87 fabs(%S1) -> %D1 */',
1019 "rd_constructor" => "NONE",
1020 "comment" => "x87 fp Chs: Chs(a) = -a",
1022 "emit" => '. fchs /* x87 fchs(%S1) -> %D1 */',
1027 "rd_constructor" => "NONE",
1028 "comment" => "x87 fp Sin: Sin(a) = sin(a)",
1030 "emit" => '. fsin /* x87 sin(%S1) -> %D1 */',
1035 "rd_constructor" => "NONE",
1036 "comment" => "x87 fp Cos: Cos(a) = cos(a)",
1038 "emit" => '. fcos /* x87 cos(%S1) -> %D1 */',
1043 "rd_constructor" => "NONE",
1044 "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1046 "emit" => '. fsqrt $ /* x87 sqrt(%S1) -> %D1 */',
1049 # x87 Load and Store
1052 "rd_constructor" => "NONE",
1053 "op_flags" => "R|L|F",
1054 "state" => "exc_pinned",
1055 "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1057 "emit" => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */',
1061 "rd_constructor" => "NONE",
1062 "op_flags" => "R|L|F",
1063 "state" => "exc_pinned",
1064 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1066 "emit" => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */',
1070 "rd_constructor" => "NONE",
1071 "op_flags" => "R|L|F",
1072 "state" => "exc_pinned",
1073 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1075 "emit" => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */',
1083 "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1085 "emit" => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */',
1090 "rd_constructor" => "NONE",
1091 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1093 "emit" => '. fist %ia32_emit_am /* integer Store(%A3) -> (%A1) */',
1098 "rd_constructor" => "NONE",
1099 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1101 "emit" => '. fistp %ia32_emit_am /* integer Store(%A3) -> (%A1) and pop */',
1108 "rd_constructor" => "NONE",
1109 "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
1111 "emit" => '. fldz /* x87 0.0 -> %D1 */',
1116 "rd_constructor" => "NONE",
1117 "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
1119 "emit" => '. fld1 /* x87 1.0 -> %D1 */',
1124 "rd_constructor" => "NONE",
1125 "comment" => "x87 fp Load pi: Ld pi -> reg",
1127 "emit" => '. fldpi /* x87 pi -> %D1 */',
1132 "rd_constructor" => "NONE",
1133 "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
1135 "emit" => '. fldln2 /* x87 ln(2) -> %D1 */',
1140 "rd_constructor" => "NONE",
1141 "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
1143 "emit" => '. fldlg2 /* x87 log(2) -> %D1 */',
1148 "rd_constructor" => "NONE",
1149 "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
1151 "emit" => '. fldll2t /* x87 ld(10) -> %D1 */',
1156 "rd_constructor" => "NONE",
1157 "comment" => "x87 fp Load ld e: Ld ld e -> reg",
1159 "emit" => '. fldl2e /* x87 ld(e) -> %D1 */',
1166 "comment" => "represents a x87 constant",
1167 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1168 "reg_req" => { "out" => [ "st" ] },
1169 "emit" => '. fld%M %C /* Load fConst into register -> %D1 */',
1173 # Note that it is NEVER allowed to do CSE on these nodes
1176 "op_flags" => "R|K",
1177 "comment" => "x87 stack exchange",
1178 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1179 "cmp_attr" => " return 1;\n",
1180 "emit" => '. fxch %X1 /* x87 swap %X1, %X3 */',
1185 "comment" => "x87 stack push",
1186 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1187 "cmp_attr" => " return 1;\n",
1188 "emit" => '. fld %X1 /* x87 push %X1 */',
1192 "op_flags" => "R|K",
1193 "comment" => "x87 stack pop",
1194 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1195 "cmp_attr" => " return 1;\n",
1196 "emit" => '. fstp %X1 /* x87 pop %X1 */',
1202 "op_flags" => "L|X|Y",
1203 "comment" => "floating point compare",
1204 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1209 "op_flags" => "L|X|Y",
1210 "comment" => "floating point compare and pop",
1211 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1216 "op_flags" => "L|X|Y",
1217 "comment" => "floating point compare and pop twice",
1218 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1223 "op_flags" => "L|X|Y",
1224 "comment" => "floating point compare reverse",
1225 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1230 "op_flags" => "L|X|Y",
1231 "comment" => "floating point compare reverse and pop",
1232 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1237 "op_flags" => "L|X|Y",
1238 "comment" => "floating point compare reverse and pop twice",
1239 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",