3 # This is the specification for the ia32 assembler Firm-operations
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
8 # this string marks the beginning of a comment in emit
9 $comment_string = "/*";
11 # the number of additional opcodes you want to register
12 #$additional_opcodes = 0;
14 # The node description is done as a perl hash initializer with the
15 # following structure:
20 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
21 # "irn_flags" => "R|N|I|S"
22 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
23 # "state" => "floats|pinned|mem_pinned|exc_pinned",
25 # { "type" => "type 1", "name" => "name 1" },
26 # { "type" => "type 2", "name" => "name 2" },
29 # "comment" => "any comment for constructor",
30 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
31 # "cmp_attr" => "c source code for comparing node attributes",
32 # "emit" => "emit code with templates",
33 # "attr" => "attitional attribute arguments for constructor"
34 # "init_attr" => "emit attribute initialization template"
35 # "rd_constructor" => "c source code which constructs an ir_node"
36 # "latency" => "latency of this operation (can be float)"
39 # ... # (all nodes you need to describe)
41 # ); # close the %nodes initializer
43 # op_flags: flags for the operation, OPTIONAL (default is "N")
44 # the op_flags correspond to the firm irop_flags:
47 # C irop_flag_commutative
48 # X irop_flag_cfopcode
49 # I irop_flag_ip_cfopcode
52 # H irop_flag_highlevel
53 # c irop_flag_constlike
56 # irn_flags: special node flags, OPTIONAL (default is 0)
57 # following irn_flags are supported:
60 # I ignore for register allocation
61 # S modifies stack pointer
63 # state: state of the operation, OPTIONAL (default is "floats")
65 # arity: arity of the operation, MUST NOT BE OMITTED
67 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
68 # are always the first 3 arguments and are always autmatically
70 # If this key is missing the following arguments will be created:
71 # for i = 1 .. arity: ir_node *op_i
74 # outs: if a node defines more than one output, the names of the projections
75 # nodes having outs having automatically the mode mode_T
77 # comment: OPTIONAL comment for the node constructor
79 # rd_constructor: for every operation there will be a
80 # new_rd_<arch>_<op-name> function with the arguments from above
81 # which creates the ir_node corresponding to the defined operation
82 # you can either put the complete source code of this function here
84 # This key is OPTIONAL. If omitted, the following constructor will
86 # if (!op_<arch>_<op-name>) assert(0);
90 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
93 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
95 # latency: the latency of the operation, default is 1
100 # 1 - caller save (register must be saved by the caller of a function)
101 # 2 - callee save (register must be saved by the called function)
102 # 4 - ignore (do not assign this register)
103 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
106 { "name" => "eax", "type" => 1 },
107 { "name" => "edx", "type" => 1 },
108 { "name" => "ebx", "type" => 2 },
109 { "name" => "ecx", "type" => 1 },
110 { "name" => "esi", "type" => 2 },
111 { "name" => "edi", "type" => 2 },
112 # { "name" => "r11", "type" => 1 },
113 # { "name" => "r12", "type" => 1 },
114 # { "name" => "r13", "type" => 1 },
115 # { "name" => "r14", "type" => 1 },
116 # { "name" => "r15", "type" => 1 },
117 # { "name" => "r16", "type" => 1 },
118 # { "name" => "r17", "type" => 1 },
119 # { "name" => "r18", "type" => 1 },
120 # { "name" => "r19", "type" => 1 },
121 # { "name" => "r20", "type" => 1 },
122 # { "name" => "r21", "type" => 1 },
123 # { "name" => "r22", "type" => 1 },
124 # { "name" => "r23", "type" => 1 },
125 # { "name" => "r24", "type" => 1 },
126 # { "name" => "r25", "type" => 1 },
127 # { "name" => "r26", "type" => 1 },
128 # { "name" => "r27", "type" => 1 },
129 # { "name" => "r28", "type" => 1 },
130 # { "name" => "r29", "type" => 1 },
131 # { "name" => "r30", "type" => 1 },
132 # { "name" => "r31", "type" => 1 },
133 # { "name" => "r32", "type" => 1 },
134 { "name" => "ebp", "type" => 2 },
135 { "name" => "esp", "type" => 4 },
136 { "name" => "gp_NOREG", "type" => 2 | 4 }, # we need a dummy register for NoReg nodes
137 { "name" => "gp_UKNWN", "type" => 2 | 4 | 8 }, # we need a dummy register for Unknown nodes
138 { "mode" => "mode_P" }
141 { "name" => "xmm0", "type" => 1 },
142 { "name" => "xmm1", "type" => 1 },
143 { "name" => "xmm2", "type" => 1 },
144 { "name" => "xmm3", "type" => 1 },
145 { "name" => "xmm4", "type" => 1 },
146 { "name" => "xmm5", "type" => 1 },
147 { "name" => "xmm6", "type" => 1 },
148 { "name" => "xmm7", "type" => 1 },
149 { "name" => "xmm_NOREG", "type" => 2 | 4 }, # we need a dummy register for NoReg nodes
150 { "name" => "xmm_UKNWN", "type" => 2 | 4 | 8 }, # we need a dummy register for Unknown nodes
151 { "mode" => "mode_D" }
154 { "name" => "vf0", "type" => 1 },
155 { "name" => "vf1", "type" => 1 },
156 { "name" => "vf2", "type" => 1 },
157 { "name" => "vf3", "type" => 1 },
158 { "name" => "vf4", "type" => 1 },
159 { "name" => "vf5", "type" => 1 },
160 { "name" => "vf6", "type" => 1 },
161 { "name" => "vf7", "type" => 1 },
162 { "name" => "vfp_NOREG", "type" => 2 | 4 }, # we need a dummy register for NoReg nodes
163 { "name" => "vfp_UKNWN", "type" => 2 | 4 | 8 }, # we need a dummy register for Unknown nodes
164 { "mode" => "mode_E" }
167 { "name" => "st0", "type" => 1 },
168 { "name" => "st1", "type" => 1 },
169 { "name" => "st2", "type" => 1 },
170 { "name" => "st3", "type" => 1 },
171 { "name" => "st4", "type" => 1 },
172 { "name" => "st5", "type" => 1 },
173 { "name" => "st6", "type" => 1 },
174 { "name" => "st7", "type" => 1 },
175 { "mode" => "mode_E" }
179 #--------------------------------------------------#
182 # _ __ _____ __ _ _ __ ___ _ __ ___ #
183 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
184 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
185 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
188 #--------------------------------------------------#
195 #-----------------------------------------------------------------#
198 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
199 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
200 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
201 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
204 #-----------------------------------------------------------------#
206 # commutative operations
209 # All nodes supporting Addressmode have 5 INs:
210 # 1 - base r1 == NoReg in case of no AM or no base
211 # 2 - index r2 == NoReg in case of no AM or no index
212 # 3 - op1 r3 == always present
213 # 4 - op2 r4 == NoReg in case of immediate operation
214 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
218 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
219 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
220 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
221 "emit" => '. add %ia32_emit_binop /* Add(%A3, %A4) -> %D1 */',
222 "outs" => [ "res", "M" ],
226 "comment" => "construct Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
227 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
228 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
229 "emit" => '. adc %ia32_emit_binop /* AddC(%A3, %A4) -> %D1 */',
230 "outs" => [ "res", "M" ],
236 "cmp_attr" => " return 1;\n",
237 "comment" => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
243 "cmp_attr" => " return 1;\n",
244 "comment" => "construct lowered Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
249 # we should not rematrialize this node. It produces 2 results and has
250 # very strict constrains
251 "comment" => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
252 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
253 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] },
254 "emit" => '. mul %ia32_emit_unop /* Mul(%A1, %A2) -> %D1 */',
255 "outs" => [ "EAX", "EDX", "M" ],
260 # we should not rematrialize this node. It produces 2 results and has
261 # very strict constrains
263 "cmp_attr" => " return 1;\n",
264 "comment" => "construct lowered MulS: MulS(a, b) = MulS(b, a) = a * b",
265 "outs" => [ "EAX", "EDX", "M" ],
271 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
272 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
273 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
274 "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */',
275 "outs" => [ "res", "M" ],
281 "cmp_attr" => " return 1;\n",
282 "comment" => "construct lowered Mul: Mul(a, b) = Mul(b, a) = a * b",
286 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
288 # we should not rematrialize this node. It produces 2 results and has
289 # very strict constrains
290 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
291 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
292 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] },
293 "emit" => '. imul %ia32_emit_unop /* Mulh(%A1, %A2) -> %D1 */',
294 "outs" => [ "EAX", "EDX", "M" ],
300 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
301 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
302 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
303 "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */',
304 "outs" => [ "res", "M" ],
309 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
310 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
311 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
312 "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */',
313 "outs" => [ "res", "M" ],
318 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
319 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
320 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
321 "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */',
322 "outs" => [ "res", "M" ],
327 "cmp_attr" => " return 1;\n",
328 "comment" => "construct lowered Eor: Eor(a, b) = Eor(b, a) = a EOR b",
334 "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
335 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
337 '2. cmp %S1, %S2 /* prepare Max (%S1 - %S2), (%A1, %A2) */
338 if (mode_is_signed(get_irn_mode(n))) {
339 4. cmovl %D1, %S2 /* %S1 is less %S2 */
342 4. cmovb %D1, %S2 /* %S1 is below %S2 */
350 "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
351 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
353 '2. cmp %S1, %S2 /* prepare Min (%S1 - %S2), (%A1, %A2) */
354 if (mode_is_signed(get_irn_mode(n))) {
355 2. cmovg %D1, %S2 /* %S1 is greater %S2 */
358 2. cmova %D1, %S2, %D1 /* %S1 is above %S2 */
364 # not commutative operations
368 "comment" => "construct Sub: Sub(a, b) = a - b",
369 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
370 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
371 "emit" => '. sub %ia32_emit_binop /* Sub(%A3, %A4) -> %D1 */',
372 "outs" => [ "res", "M" ],
376 "comment" => "construct Sub with Carry: SubC(a, b) = a - b - carry",
377 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
378 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3 !in_r4" ] },
379 "emit" => '. sbb %ia32_emit_binop /* SubC(%A3, %A4) -> %D1 */',
380 "outs" => [ "res", "M" ],
385 "cmp_attr" => " return 1;\n",
386 "comment" => "construct lowered Sub: Sub(a, b) = a - b",
391 "cmp_attr" => " return 1;\n",
392 "comment" => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
398 "state" => "exc_pinned",
399 "reg_req" => { "in" => [ "eax", "gp", "edx", "none" ], "out" => [ "eax", "edx" ] },
400 "attr" => "ia32_op_flavour_t dm_flav",
401 "init_attr" => " attr->data.op_flav = dm_flav;",
402 "cmp_attr" => " return attr_a->data.op_flav != attr_b->data.op_flav;\n",
404 ' if (mode_is_signed(get_ia32_res_mode(n))) {
405 4. idiv %S2 /* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
408 4. div %S2 /* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
411 "outs" => [ "div_res", "mod_res", "M" ],
417 "comment" => "construct Shl: Shl(a, b) = a << b",
418 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
419 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx gp_NOREG", "none" ], "out" => [ "in_r3 !in_r4" ] },
420 "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */',
421 "outs" => [ "res", "M" ],
425 "cmp_attr" => " return 1;\n",
426 "comment" => "construct lowered Shl: Shl(a, b) = a << b",
432 "comment" => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
433 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
434 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!ecx in_r3 !in_r4" ] },
437 if (get_ia32_immop_type(n) == ia32_ImmNone) {
438 if (get_ia32_op_type(n) == ia32_AddrModeD) {
439 4. shld %ia32_emit_am, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
442 4. shld %S3, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
446 if (get_ia32_op_type(n) == ia32_AddrModeD) {
447 4. shld %ia32_emit_am, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
450 4. shld %S3, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
454 "outs" => [ "res", "M" ],
459 "cmp_attr" => " return 1;\n",
460 "comment" => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
466 "comment" => "construct Shr: Shr(a, b) = a >> b",
467 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
468 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx gp_NOREG", "none" ], "out" => [ "in_r3 !in_r4" ] },
469 "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */',
470 "outs" => [ "res", "M" ],
474 "cmp_attr" => " return 1;\n",
475 "comment" => "construct lowered Shr: Shr(a, b) = a << b",
481 "comment" => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
482 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
483 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!ecx in_r3 !in_r4" ] },
486 if (get_ia32_immop_type(n) == ia32_ImmNone) {
487 if (get_ia32_op_type(n) == ia32_AddrModeD) {
488 4. shrd %ia32_emit_am, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
491 4. shrd %S3, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
495 if (get_ia32_op_type(n) == ia32_AddrModeD) {
496 4. shrd %ia32_emit_am, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
499 4. shrd %S3, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
503 "outs" => [ "res", "M" ],
508 "cmp_attr" => " return 1;\n",
509 "comment" => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
515 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
516 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
517 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx gp_NOREG", "none" ], "out" => [ "in_r3 !in_r4" ] },
518 "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */',
519 "outs" => [ "res", "M" ],
523 "cmp_attr" => " return 1;\n",
524 "comment" => "construct lowered Shrs: Shrs(a, b) = a << b",
530 "comment" => "construct RotR: RotR(a, b) = a ROTR b",
531 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
532 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
533 "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */',
534 "outs" => [ "res", "M" ],
539 "comment" => "construct RotL: RotL(a, b) = a ROTL b",
540 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
541 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
542 "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */',
543 "outs" => [ "res", "M" ],
550 "comment" => "construct Minus: Minus(a) = -a",
551 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
552 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
553 "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */',
554 "outs" => [ "res", "M" ],
558 "cmp_attr" => " return 1;\n",
559 "comment" => "construct lowered Minus: Minus(a) = -a",
565 "comment" => "construct Increment: Inc(a) = a++",
566 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
567 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
568 "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */',
569 "outs" => [ "res", "M" ],
574 "comment" => "construct Decrement: Dec(a) = a--",
575 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
576 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
577 "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */',
578 "outs" => [ "res", "M" ],
583 "comment" => "construct Not: Not(a) = !a",
584 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
585 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
586 "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */',
587 "outs" => [ "res", "M" ],
593 "op_flags" => "L|X|Y",
594 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
595 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
596 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
597 "outs" => [ "false", "true" ],
602 "op_flags" => "L|X|Y",
603 "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
604 "reg_req" => { "in" => [ "gp", "gp" ] },
605 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
606 "outs" => [ "false", "true" ],
611 "op_flags" => "L|X|Y",
612 "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
613 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
614 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
615 "outs" => [ "false", "true" ],
619 "op_flags" => "L|X|Y",
620 "comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
621 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
622 "reg_req" => { "in" => [ "gp", "gp" ] },
626 "op_flags" => "L|X|Y",
627 "comment" => "construct switch",
628 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
629 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
636 "comment" => "represents an integer constant",
637 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
638 "reg_req" => { "in" => [ "none" ], "out" => [ "gp" ] },
642 # we should not rematrialize this node. It produces 2 results and has
643 # very strict constrains
644 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
645 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
646 "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */',
647 "outs" => [ "EAX", "EDX" ],
654 "state" => "exc_pinned",
655 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
656 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
657 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
660 ' if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) {
661 4. mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
664 4. mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
667 "outs" => [ "res", "M" ],
672 "cmp_attr" => " return 1;\n",
673 "comment" => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg",
674 "outs" => [ "res", "M" ],
680 "cmp_attr" => " return 1;\n",
681 "state" => "exc_pinned",
682 "comment" => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val",
689 "state" => "exc_pinned",
690 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
691 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
692 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
693 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
700 "state" => "exc_pinned",
701 "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
702 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
703 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx gp_NOREG", "none" ] },
704 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
711 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
712 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
713 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
714 "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */',
719 # We don't set class modify_stack here (but we will do this on proj 0)
720 "comment" => "push on the stack",
721 "reg_req" => { "in" => [ "gp", "gp", "gp", "esp", "none" ], "out" => [ "esp" ] },
722 "emit" => '. push %ia32_emit_unop /* PUSH(%A1) */',
723 "outs" => [ "stack", "M" ],
728 # We don't set class modify stack here (but we will do this on proj 1)
729 "comment" => "pop a gp register from the stack",
730 "reg_req" => { "in" => [ "gp", "gp", "esp", "none" ], "out" => [ "gp", "esp" ] },
731 "emit" => '. pop %ia32_emit_unop /* POP(%A1) */',
732 "outs" => [ "res", "stack", "M" ],
737 "comment" => "create stack frame",
738 "reg_req" => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] },
739 "emit" => '. enter /* Enter */',
740 "outs" => [ "frame", "stack", "M" ],
745 "comment" => "destroy stack frame",
746 "reg_req" => { "in" => [ "esp", "ebp" ], "out" => [ "ebp", "esp" ] },
747 "emit" => '. leave /* Leave */',
748 "outs" => [ "frame", "stack", "M" ],
754 "comment" => "allocate space on stack",
755 "reg_req" => { "in" => [ "esp", "gp" ], "out" => [ "esp", "none" ] },
756 "outs" => [ "stack", "M" ],
761 "comment" => "free space on stack",
762 "reg_req" => { "in" => [ "esp", "gp" ], "out" => [ "esp", "none" ] },
763 "outs" => [ "stack", "M" ],
768 "comment" => "get the TLS base address",
769 "reg_req" => { "out" => [ "gp" ] },
774 #-----------------------------------------------------------------------------#
775 # _____ _____ ______ __ _ _ _ #
776 # / ____/ ____| ____| / _| | | | | | #
777 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
778 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
779 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
780 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
781 #-----------------------------------------------------------------------------#
783 # commutative operations
787 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
788 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
789 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
790 "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */',
791 "outs" => [ "res", "M" ],
797 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
798 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
799 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
800 "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */',
801 "outs" => [ "res", "M" ],
807 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
808 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
809 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
810 "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */',
811 "outs" => [ "res", "M" ],
817 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
818 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
819 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
820 "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */',
821 "outs" => [ "res", "M" ],
827 "comment" => "construct SSE And: And(a, b) = a AND b",
828 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
829 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
830 "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */',
831 "outs" => [ "res", "M" ],
837 "comment" => "construct SSE Or: Or(a, b) = a OR b",
838 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
839 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
840 "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */',
841 "outs" => [ "res", "M" ],
846 "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
847 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
848 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
849 "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */',
850 "outs" => [ "res", "M" ],
854 # not commutative operations
858 "comment" => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
859 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
860 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
861 "emit" => '. andnp%M %ia32_emit_binop /* SSE AndNot(%A3, %A4) -> %D1 */',
862 "outs" => [ "res", "M" ],
868 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
869 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
870 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
871 "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */',
872 "outs" => [ "res", "M" ],
878 "comment" => "construct SSE Div: Div(a, b) = a / b",
879 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
880 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
881 "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */',
882 "outs" => [ "res", "M" ],
890 "comment" => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
891 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
892 "outs" => [ "res", "M" ],
897 "op_flags" => "L|X|Y",
898 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
899 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
900 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
901 "outs" => [ "false", "true" ],
908 "comment" => "represents a SSE constant",
909 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
910 "reg_req" => { "in" => [ "none" ], "out" => [ "xmm" ] },
911 "emit" => '. movs%M %D1, %C /* Load fConst into register */',
919 "state" => "exc_pinned",
920 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
921 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
922 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm" ] },
923 "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */',
924 "outs" => [ "res", "M" ],
930 "state" => "exc_pinned",
931 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
932 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
933 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
934 "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */',
941 "state" => "exc_pinned",
942 "comment" => "construct Store without index: Store(ptr, val, mem) = ST ptr,val",
943 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
944 "reg_req" => { "in" => [ "gp", "xmm", "none" ] },
945 "emit" => '. movs%M %ia32_emit_am, %S2 /* store XMM0 onto stack */',
952 "comment" => "construct: transfer a value from x87 FPU into a SSE register",
953 "cmp_attr" => " return 1;\n",
959 "comment" => "construct: transfer a value from SSE register to x87 FPU",
960 "cmp_attr" => " return 1;\n",
967 "state" => "exc_pinned",
968 "comment" => "store ST0 onto stack",
969 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
970 "reg_req" => { "in" => [ "gp", "none" ] },
971 "emit" => '. fstp %ia32_emit_am /* store ST0 onto stack */',
979 "state" => "exc_pinned",
980 "comment" => "load ST0 from stack",
981 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
982 "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "vf0", "none" ] },
983 "emit" => '. fld %ia32_emit_am /* load ST0 from stack */',
984 "outs" => [ "res", "M" ],
993 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
994 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "edi", "esi", "ecx", "none" ] },
995 "outs" => [ "DST", "SRC", "CNT", "M" ],
1000 "state" => "pinned",
1001 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
1002 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1003 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "edi", "esi", "none" ] },
1004 "outs" => [ "DST", "SRC", "M" ],
1010 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
1011 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1012 "comment" => "construct Conv Int -> Int",
1013 "outs" => [ "res", "M" ],
1017 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
1018 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1019 "comment" => "construct Conv Int -> Int",
1020 "outs" => [ "res", "M" ],
1024 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
1025 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1026 "comment" => "construct Conv Int -> Floating Point",
1027 "outs" => [ "res", "M" ],
1032 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
1033 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1034 "comment" => "construct Conv Floating Point -> Int",
1035 "outs" => [ "res", "M" ],
1040 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
1041 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1042 "comment" => "construct Conv Floating Point -> Floating Point",
1043 "outs" => [ "res", "M" ],
1049 "comment" => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
1050 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "in_r4" ] },
1056 "comment" => "check if Psi condition tree evaluates to true and move result accordingly",
1057 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r3" ] },
1063 "comment" => "construct Conditional Move: SSE Compare + int CMov ",
1064 "reg_req" => { "in" => [ "xmm", "xmm", "gp", "gp" ], "out" => [ "in_r4" ] },
1070 "comment" => "construct Conditional Move: x87 Compare + int CMov",
1071 "reg_req" => { "in" => [ "vfp", "vfp", "gp", "gp" ], "out" => [ "in_r4" ] },
1077 "comment" => "construct Set: Set(sel) == sel ? 1 : 0",
1078 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1079 "outs" => [ "res", "M" ],
1085 "comment" => "check if Psi condition tree evaluates to true and set result accordingly",
1086 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax ebx ecx edx" ] },
1092 "comment" => "construct Set: SSE Compare + int Set",
1093 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1094 "outs" => [ "res", "M" ],
1100 "comment" => "construct Set: x87 Compare + int Set",
1101 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1102 "outs" => [ "res", "M" ],
1108 "comment" => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
1109 "reg_req" => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] },
1113 #----------------------------------------------------------#
1115 # (_) | | | | / _| | | | #
1116 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
1117 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
1118 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
1119 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
1121 # _ __ ___ __| | ___ ___ #
1122 # | '_ \ / _ \ / _` |/ _ \/ __| #
1123 # | | | | (_) | (_| | __/\__ \ #
1124 # |_| |_|\___/ \__,_|\___||___/ #
1125 #----------------------------------------------------------#
1129 "comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
1130 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1131 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1132 "outs" => [ "res", "M" ],
1138 "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1139 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1140 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1141 "outs" => [ "res", "M" ],
1147 "cmp_attr" => " return 1;\n",
1148 "comment" => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1154 "comment" => "virtual fp Sub: Sub(a, b) = a - b",
1155 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1156 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1157 "outs" => [ "res", "M" ],
1162 "cmp_attr" => " return 1;\n",
1163 "comment" => "lowered virtual fp Sub: Sub(a, b) = a - b",
1168 "comment" => "virtual fp Div: Div(a, b) = a / b",
1169 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1170 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1171 "outs" => [ "res", "M" ],
1176 "cmp_attr" => " return 1;\n",
1177 "comment" => "lowered virtual fp Div: Div(a, b) = a / b",
1183 "comment" => "virtual fp Abs: Abs(a) = |a|",
1184 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1190 "comment" => "virtual fp Chs: Chs(a) = -a",
1191 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1197 "comment" => "virtual fp Sin: Sin(a) = sin(a)",
1198 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1204 "comment" => "virtual fp Cos: Cos(a) = cos(a)",
1205 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1211 "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
1212 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1216 # virtual Load and Store
1219 "op_flags" => "L|F",
1220 "state" => "exc_pinned",
1221 "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
1222 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1223 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1224 "outs" => [ "res", "M" ],
1229 "op_flags" => "L|F",
1230 "state" => "exc_pinned",
1231 "comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
1232 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1233 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1241 "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1242 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1243 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1244 "outs" => [ "res", "M" ],
1249 "cmp_attr" => " return 1;\n",
1250 "comment" => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1251 "outs" => [ "res", "M" ],
1256 "comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1257 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1258 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1264 "cmp_attr" => " return 1;\n",
1265 "comment" => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1275 "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg",
1276 "reg_req" => { "out" => [ "vfp" ] },
1282 "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg",
1283 "reg_req" => { "out" => [ "vfp" ] },
1289 "comment" => "virtual fp Load pi: Ld pi -> reg",
1290 "reg_req" => { "out" => [ "vfp" ] },
1296 "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg",
1297 "reg_req" => { "out" => [ "vfp" ] },
1303 "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg",
1304 "reg_req" => { "out" => [ "vfp" ] },
1310 "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg",
1311 "reg_req" => { "out" => [ "vfp" ] },
1317 "comment" => "virtual fp Load ld e: Ld ld e -> reg",
1318 "reg_req" => { "out" => [ "vfp" ] },
1325 "init_attr" => " set_ia32_ls_mode(res, mode);",
1326 "comment" => "represents a virtual floating point constant",
1327 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1328 "reg_req" => { "in" => [ "none" ], "out" => [ "vfp" ] },
1335 "op_flags" => "L|X|Y",
1336 "comment" => "represents a virtual floating point compare",
1337 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1338 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] },
1339 "outs" => [ "false", "true", "temp_reg_eax" ],
1343 #------------------------------------------------------------------------#
1344 # ___ _____ __ _ _ _ #
1345 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1346 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1347 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1348 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1349 #------------------------------------------------------------------------#
1353 "rd_constructor" => "NONE",
1354 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1356 "emit" => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A3, %A4) -> %D1 */',
1361 "rd_constructor" => "NONE",
1362 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1364 "emit" => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A3, %A4) -> %D1 */',
1369 "rd_constructor" => "NONE",
1370 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1372 "emit" => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A3, %A4) -> %D1 */',
1377 "rd_constructor" => "NONE",
1378 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1380 "emit" => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A3, %A4) -> %D1 */',,
1385 "rd_constructor" => "NONE",
1386 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1388 "emit" => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A3, %A4) -> %D1 */',
1393 "rd_constructor" => "NONE",
1394 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1396 "emit" => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A3, %A4) -> %D1 */',
1401 "rd_constructor" => "NONE",
1403 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1405 "emit" => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A3, %A4) -> %D1 */',
1410 "rd_constructor" => "NONE",
1412 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1414 "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A3, %A4) -> %D1 */',
1419 "rd_constructor" => "NONE",
1420 "comment" => "x87 fp Div: Div(a, b) = a / b",
1422 "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A3, %A4) -> %D1 */',
1427 "rd_constructor" => "NONE",
1428 "comment" => "x87 fp Div: Div(a, b) = a / b",
1430 "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A3, %A4) -> %D1 */',
1435 "rd_constructor" => "NONE",
1436 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1438 "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A3, %A4) -> %D1 */',
1443 "rd_constructor" => "NONE",
1444 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1446 "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A3, %A4) -> %D1 */',
1451 "rd_constructor" => "NONE",
1452 "comment" => "x87 fp Abs: Abs(a) = |a|",
1454 "emit" => '. fabs /* x87 fabs(%A1) -> %D1 */',
1459 "rd_constructor" => "NONE",
1460 "comment" => "x87 fp Chs: Chs(a) = -a",
1462 "emit" => '. fchs /* x87 fchs(%A1) -> %D1 */',
1467 "rd_constructor" => "NONE",
1468 "comment" => "x87 fp Sin: Sin(a) = sin(a)",
1470 "emit" => '. fsin /* x87 sin(%A1) -> %D1 */',
1475 "rd_constructor" => "NONE",
1476 "comment" => "x87 fp Cos: Cos(a) = cos(a)",
1478 "emit" => '. fcos /* x87 cos(%A1) -> %D1 */',
1483 "rd_constructor" => "NONE",
1484 "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1486 "emit" => '. fsqrt $ /* x87 sqrt(%A1) -> %D1 */',
1489 # x87 Load and Store
1492 "rd_constructor" => "NONE",
1493 "op_flags" => "R|L|F",
1494 "state" => "exc_pinned",
1495 "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1497 "emit" => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */',
1501 "rd_constructor" => "NONE",
1502 "op_flags" => "R|L|F",
1503 "state" => "exc_pinned",
1504 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1506 "emit" => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */',
1510 "rd_constructor" => "NONE",
1511 "op_flags" => "R|L|F",
1512 "state" => "exc_pinned",
1513 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1515 "emit" => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */',
1522 "rd_constructor" => "NONE",
1523 "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1525 "emit" => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */',
1530 "rd_constructor" => "NONE",
1531 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1533 "emit" => '. fist %ia32_emit_am /* integer Store(%A3) -> (%A1) */',
1538 "rd_constructor" => "NONE",
1539 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1541 "emit" => '. fistp %ia32_emit_am /* integer Store(%A3) -> (%A1) and pop */',
1547 "op_flags" => "R|c",
1549 "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
1551 "emit" => '. fldz /* x87 0.0 -> %D1 */',
1555 "op_flags" => "R|c",
1557 "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
1559 "emit" => '. fld1 /* x87 1.0 -> %D1 */',
1563 "op_flags" => "R|c",
1565 "comment" => "x87 fp Load pi: Ld pi -> reg",
1567 "emit" => '. fldpi /* x87 pi -> %D1 */',
1571 "op_flags" => "R|c",
1573 "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
1575 "emit" => '. fldln2 /* x87 ln(2) -> %D1 */',
1579 "op_flags" => "R|c",
1581 "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
1583 "emit" => '. fldlg2 /* x87 log(2) -> %D1 */',
1587 "op_flags" => "R|c",
1589 "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
1591 "emit" => '. fldll2t /* x87 ld(10) -> %D1 */',
1595 "op_flags" => "R|c",
1597 "comment" => "x87 fp Load ld e: Ld ld e -> reg",
1599 "emit" => '. fldl2e /* x87 ld(e) -> %D1 */',
1603 "op_flags" => "R|c",
1605 "rd_constructor" => "NONE",
1606 "comment" => "represents a x87 constant",
1607 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1608 "reg_req" => { "out" => [ "st" ] },
1609 "emit" => '. fld %ia32_emit_adr /* Load fConst into register -> %D1 */',
1613 # Note that it is NEVER allowed to do CSE on these nodes
1616 "op_flags" => "R|K",
1617 "comment" => "x87 stack exchange",
1618 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1619 "cmp_attr" => " return 1;\n",
1620 "emit" => '. fxch %X1 /* x87 swap %X1, %X3 */',
1625 "comment" => "x87 stack push",
1626 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1627 "cmp_attr" => " return 1;\n",
1628 "emit" => '. fld %X1 /* x87 push %X1 */',
1632 "op_flags" => "R|K",
1633 "comment" => "x87 stack pop",
1634 "reg_req" => { "out" => [ "st" ] },
1635 "cmp_attr" => " return 1;\n",
1636 "emit" => '. fstp %X1 /* x87 pop %X1 */',
1642 "op_flags" => "L|X|Y",
1643 "comment" => "floating point compare",
1644 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1649 "op_flags" => "L|X|Y",
1650 "comment" => "floating point compare and pop",
1651 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1656 "op_flags" => "L|X|Y",
1657 "comment" => "floating point compare and pop twice",
1658 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1663 "op_flags" => "L|X|Y",
1664 "comment" => "floating point compare reverse",
1665 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1670 "op_flags" => "L|X|Y",
1671 "comment" => "floating point compare reverse and pop",
1672 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1677 "op_flags" => "L|X|Y",
1678 "comment" => "floating point compare reverse and pop twice",
1679 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",