3 # This is the specification for the ia32 assembler Firm-operations
7 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
10 # The node description is done as a perl hash initializer with the
11 # following structure:
16 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
17 # "irn_flags" => "R|N|I|S"
18 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
19 # "state" => "floats|pinned|mem_pinned|exc_pinned",
21 # { "type" => "type 1", "name" => "name 1" },
22 # { "type" => "type 2", "name" => "name 2" },
25 # "comment" => "any comment for constructor",
26 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
27 # "cmp_attr" => "c source code for comparing node attributes",
28 # "emit" => "emit code with templates",
29 # "attr" => "attitional attribute arguments for constructor"
30 # "init_attr" => "emit attribute initialization template"
31 # "rd_constructor" => "c source code which constructs an ir_node"
32 # "latency" => "latency of this operation (can be float)"
35 # ... # (all nodes you need to describe)
37 # ); # close the %nodes initializer
39 # op_flags: flags for the operation, OPTIONAL (default is "N")
40 # the op_flags correspond to the firm irop_flags:
43 # C irop_flag_commutative
44 # X irop_flag_cfopcode
45 # I irop_flag_ip_cfopcode
48 # H irop_flag_highlevel
49 # c irop_flag_constlike
52 # irn_flags: special node flags, OPTIONAL (default is 0)
53 # following irn_flags are supported:
56 # I ignore for register allocation
57 # S modifies stack pointer
59 # state: state of the operation, OPTIONAL (default is "floats")
61 # arity: arity of the operation, MUST NOT BE OMITTED
63 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
64 # are always the first 3 arguments and are always autmatically
66 # If this key is missing the following arguments will be created:
67 # for i = 1 .. arity: ir_node *op_i
70 # outs: if a node defines more than one output, the names of the projections
71 # nodes having outs having automatically the mode mode_T
72 # One can also annotate some flags for each out, additional to irn_flags.
73 # They are separated from name with a colon ':', and concatenated by pipe '|'
74 # Only I and S are available at the moment (same meaning as in irn_flags).
75 # example: [ "frame:I", "stack:I|S", "M" ]
77 # comment: OPTIONAL comment for the node constructor
79 # rd_constructor: for every operation there will be a
80 # new_rd_<arch>_<op-name> function with the arguments from above
81 # which creates the ir_node corresponding to the defined operation
82 # you can either put the complete source code of this function here
84 # This key is OPTIONAL. If omitted, the following constructor will
86 # if (!op_<arch>_<op-name>) assert(0);
90 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
93 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
95 # latency: the latency of the operation, default is 1
100 # 1 - caller save (register must be saved by the caller of a function)
101 # 2 - callee save (register must be saved by the called function)
102 # 4 - ignore (do not assign this register)
103 # 8 - emitter can choose an arbitrary register of this class
104 # 16 - the register is a virtual one
105 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
108 { "name" => "eax", "type" => 1 },
109 { "name" => "edx", "type" => 1 },
110 { "name" => "ebx", "type" => 2 },
111 { "name" => "ecx", "type" => 1 },
112 { "name" => "esi", "type" => 2 },
113 { "name" => "edi", "type" => 2 },
114 { "name" => "ebp", "type" => 2 },
115 { "name" => "esp", "type" => 4 },
116 { "name" => "gp_NOREG", "type" => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
117 { "name" => "gp_UKNWN", "type" => 4 | 8 | 16}, # we need a dummy register for Unknown nodes
118 { "mode" => "mode_Iu" }
121 { "name" => "xmm0", "type" => 1 },
122 { "name" => "xmm1", "type" => 1 },
123 { "name" => "xmm2", "type" => 1 },
124 { "name" => "xmm3", "type" => 1 },
125 { "name" => "xmm4", "type" => 1 },
126 { "name" => "xmm5", "type" => 1 },
127 { "name" => "xmm6", "type" => 1 },
128 { "name" => "xmm7", "type" => 1 },
129 { "name" => "xmm_NOREG", "type" => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
130 { "name" => "xmm_UKNWN", "type" => 4 | 8 | 16}, # we need a dummy register for Unknown nodes
131 { "mode" => "mode_E" }
134 { "name" => "vf0", "type" => 1 | 16 },
135 { "name" => "vf1", "type" => 1 | 16 },
136 { "name" => "vf2", "type" => 1 | 16 },
137 { "name" => "vf3", "type" => 1 | 16 },
138 { "name" => "vf4", "type" => 1 | 16 },
139 { "name" => "vf5", "type" => 1 | 16 },
140 { "name" => "vf6", "type" => 1 | 16 },
141 { "name" => "vf7", "type" => 1 | 16 },
142 { "name" => "vfp_NOREG", "type" => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
143 { "name" => "vfp_UKNWN", "type" => 4 | 8 | 16}, # we need a dummy register for Unknown nodes
144 { "mode" => "mode_E" }
147 { "name" => "st0", "type" => 1 },
148 { "name" => "st1", "type" => 1 },
149 { "name" => "st2", "type" => 1 },
150 { "name" => "st3", "type" => 1 },
151 { "name" => "st4", "type" => 1 },
152 { "name" => "st5", "type" => 1 },
153 { "name" => "st6", "type" => 1 },
154 { "name" => "st7", "type" => 1 },
155 { "mode" => "mode_E" }
157 "fp_cw" => [ # the floating point control word
158 { "name" => "fpcw", "type" => 0 },
159 { "mode" => "mode_Hu" },
164 "GP" => [ 1, "GP_EAX", "GP_EBX", "GP_ECX", "GP_EDX", "GP_ESI", "GP_EDI", "GP_EBP" ],
165 "SSE" => [ 1, "SSE_XMM0", "SSE_XMM1", "SSE_XMM2", "SSE_XMM3", "SSE_XMM4", "SSE_XMM5", "SSE_XMM6", "SSE_XMM7" ],
166 "VFP" => [ 1, "VFP_VF0", "VFP_VF1", "VFP_VF2", "VFP_VF3", "VFP_VF4", "VFP_VF5", "VFP_VF6", "VFP_VF7" ],
167 "BRANCH" => [ 1, "BRANCH1", "BRANCH2" ],
172 "bundels_per_cycle" => 1
176 "S1" => "${arch}_emit_source_register(env, node, 0);",
177 "S2" => "${arch}_emit_source_register(env, node, 1);",
178 "S3" => "${arch}_emit_source_register(env, node, 2);",
179 "S4" => "${arch}_emit_source_register(env, node, 3);",
180 "S5" => "${arch}_emit_source_register(env, node, 4);",
181 "S6" => "${arch}_emit_source_register(env, node, 5);",
182 "D1" => "${arch}_emit_dest_register(env, node, 0);",
183 "D2" => "${arch}_emit_dest_register(env, node, 1);",
184 "D3" => "${arch}_emit_dest_register(env, node, 2);",
185 "D4" => "${arch}_emit_dest_register(env, node, 3);",
186 "D5" => "${arch}_emit_dest_register(env, node, 4);",
187 "D6" => "${arch}_emit_dest_register(env, node, 5);",
188 "A1" => "${arch}_emit_in_node_name(env, node, 0);",
189 "A2" => "${arch}_emit_in_node_name(env, node, 1);",
190 "A3" => "${arch}_emit_in_node_name(env, node, 2);",
191 "A4" => "${arch}_emit_in_node_name(env, node, 3);",
192 "A5" => "${arch}_emit_in_node_name(env, node, 4);",
193 "A6" => "${arch}_emit_in_node_name(env, node, 5);",
194 "X1" => "${arch}_emit_x87_name(env, node, 0);",
195 "X2" => "${arch}_emit_x87_name(env, node, 1);",
196 "X3" => "${arch}_emit_x87_name(env, node, 2);",
197 "C" => "${arch}_emit_immediate(env, node);",
198 "SE" => "${arch}_emit_extend_suffix(env, get_ia32_ls_mode(node));",
199 "ME" => "if(get_mode_size_bits(get_ia32_ls_mode(node)) != 32)\n
200 ${arch}_emit_mode_suffix(env, get_ia32_ls_mode(node));",
201 "M" => "${arch}_emit_mode_suffix(env, get_ia32_ls_mode(node));",
202 "XM" => "${arch}_emit_x87_mode_suffix(env, node);",
203 "AM" => "${arch}_emit_am(env, node);",
204 "unop" => "${arch}_emit_unop(env, node);",
205 "binop" => "${arch}_emit_binop(env, node);",
206 "x87_binop" => "${arch}_emit_x87_binop(env, node);",
209 #--------------------------------------------------#
212 # _ __ _____ __ _ _ __ ___ _ __ ___ #
213 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
214 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
215 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
218 #--------------------------------------------------#
220 $default_cmp_attr = "return ia32_compare_attr(attr_a, attr_b);";
227 #-----------------------------------------------------------------#
230 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
231 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
232 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
233 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
236 #-----------------------------------------------------------------#
238 # commutative operations
241 # All nodes supporting Addressmode have 5 INs:
242 # 1 - base r1 == NoReg in case of no AM or no base
243 # 2 - index r2 == NoReg in case of no AM or no index
244 # 3 - op1 r3 == always present
245 # 4 - op2 r4 == NoReg in case of immediate operation
246 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
250 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
251 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
252 "emit" => '. addl %binop',
258 "comment" => "construct Add with Carry: Adc(a, b) = Add(b, a) = a + b + carry",
259 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
260 "emit" => '. adcl %binop',
267 "comment" => "construct 64Bit Add: Add(a_l, a_h, b_l, b_h) = a_l + b_l; a_h + b_h + carry",
269 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
276 "outs" => [ "low_res", "high_res" ],
283 "cmp_attr" => "return 1;",
284 "comment" => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
290 "cmp_attr" => "return 1;",
291 "comment" => "construct lowered Add with Carry: Adc(a, b) = Adc(b, a) = a + b + carry",
296 # we should not rematrialize this node. It produces 2 results and has
297 # very strict constrains
298 "comment" => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
299 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx", "none" ] },
300 "emit" => '. mull %unop',
301 "outs" => [ "EAX", "EDX", "M" ],
307 # we should not rematrialize this node. It produces 2 results and has
308 # very strict constrains
310 "cmp_attr" => "return 1;",
311 "comment" => "construct lowered MulS: Mul(a, b) = Mul(b, a) = a * b",
312 "outs" => [ "EAX", "EDX", "M" ],
318 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
319 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
320 "emit" => '. imull %binop',
328 "cmp_attr" => "return 1;",
329 "comment" => "construct lowered IMul: IMul(a, b) = IMul(b, a) = a * b",
333 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
334 # Matze: It's not clear to me why we have a separate Mulh node and not just use
337 # we should not rematrialize this node. It produces 2 results and has
338 # very strict constrains
339 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
340 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] },
341 "emit" => '. imull %unop',
342 "outs" => [ "EAX", "EDX", "M" ],
349 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
350 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
351 "emit" => '. andl %binop',
358 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
359 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
360 "emit" => '. orl %binop',
367 "comment" => "construct Xor: Xor(a, b) = Xor(b, a) = a EOR b",
368 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
369 "emit" => '. xorl %binop',
376 "cmp_attr" => "return 1;",
377 "comment" => "construct lowered Xor: Xor(a, b) = Xor(b, a) = a XOR b",
381 # not commutative operations
385 "comment" => "construct Sub: Sub(a, b) = a - b",
386 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
387 "emit" => '. subl %binop',
393 "comment" => "construct Sub with Carry: SubC(a, b) = a - b - carry",
394 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3 !in_r4" ] },
395 "emit" => '. sbbl %binop',
402 "comment" => "construct 64Bit Sub: Sub(a_l, a_h, b_l, b_h) = a_l - b_l; a_h - b_h - borrow",
404 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
411 "outs" => [ "low_res", "high_res" ],
417 "cmp_attr" => "return 1;",
418 "comment" => "construct lowered Sub: Sub(a, b) = a - b",
423 "cmp_attr" => "return 1;",
424 "comment" => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
430 "state" => "exc_pinned",
431 "reg_req" => { "in" => [ "eax", "gp", "edx", "none" ], "out" => [ "eax", "edx", "none" ] },
432 "attr" => "ia32_op_flavour_t dm_flav",
433 "init_attr" => "attr->data.op_flav = dm_flav;",
434 "emit" => ". idivl %unop",
435 "outs" => [ "div_res", "mod_res", "M" ],
442 "state" => "exc_pinned",
443 "reg_req" => { "in" => [ "eax", "gp", "edx", "none" ], "out" => [ "eax", "edx", "none" ] },
444 "attr" => "ia32_op_flavour_t dm_flav",
445 "init_attr" => "attr->data.op_flav = dm_flav;",
446 "emit" => ". divl %unop",
447 "outs" => [ "div_res", "mod_res", "M" ],
454 "comment" => "construct Shl: Shl(a, b) = a << b",
455 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
456 "emit" => '. shll %binop',
462 "cmp_attr" => "return 1;",
463 "comment" => "construct lowered Shl: Shl(a, b) = a << b",
469 "comment" => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
470 # Out requirements is: different from all in
471 # This is because, out must be different from LowPart and ShiftCount.
472 # We could say "!ecx !in_r4" but it can occur, that all values live through
473 # this Shift and the only value dying is the ShiftCount. Then there would be a
474 # register missing, as result must not be ecx and all other registers are
475 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
476 # (and probably never will). So we create artificial interferences of the result
477 # with all inputs, so the spiller can always assure a free register.
478 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!in" ] },
481 if (get_ia32_immop_type(node) == ia32_ImmNone) {
482 if (get_ia32_op_type(node) == ia32_AddrModeD) {
483 . shldl %%cl, %S4, %AM
485 . shldl %%cl, %S4, %S3
488 if (get_ia32_op_type(node) == ia32_AddrModeD) {
489 . shldl $%C, %S4, %AM
491 . shldl $%C, %S4, %S3
501 "cmp_attr" => "return 1;",
502 "comment" => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
508 "comment" => "construct Shr: Shr(a, b) = a >> b",
509 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
510 "emit" => '. shrl %binop',
516 "cmp_attr" => "return 1;",
517 "comment" => "construct lowered Shr: Shr(a, b) = a << b",
523 "comment" => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
524 # Out requirements is: different from all in
525 # This is because, out must be different from LowPart and ShiftCount.
526 # We could say "!ecx !in_r4" but it can occur, that all values live through
527 # this Shift and the only value dying is the ShiftCount. Then there would be a
528 # register missing, as result must not be ecx and all other registers are
529 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
530 # (and probably never will). So we create artificial interferences of the result
531 # with all inputs, so the spiller can always assure a free register.
532 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!in" ] },
534 if (get_ia32_immop_type(node) == ia32_ImmNone) {
535 if (get_ia32_op_type(node) == ia32_AddrModeD) {
536 . shrdl %%cl, %S4, %AM
538 . shrdl %%cl, %S4, %S3
541 if (get_ia32_op_type(node) == ia32_AddrModeD) {
542 . shrdl $%C, %S4, %AM
544 . shrdl $%C, %S4, %S3
554 "cmp_attr" => "return 1;",
555 "comment" => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
561 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
562 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
563 "emit" => '. sarl %binop',
569 "cmp_attr" => "return 1;",
570 "comment" => "construct lowered Sar: Sar(a, b) = a << b",
576 "comment" => "construct Ror: Ror(a, b) = a ROR b",
577 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
578 "emit" => '. rorl %binop',
585 "comment" => "construct Rol: Rol(a, b) = a ROL b",
586 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
587 "emit" => '. roll %binop',
596 "comment" => "construct Minus: Minus(a) = -a",
597 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
598 "emit" => '. negl %unop',
605 "comment" => "construct 64Bit Minus: Minus(a_l, a_h, 0) = 0 - a_l; 0 - a_h - borrow",
607 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
614 "outs" => [ "low_res", "high_res" ],
620 "cmp_attr" => "return 1;",
621 "comment" => "construct lowered Minus: Minus(a) = -a",
627 "comment" => "construct Increment: Inc(a) = a++",
628 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
629 "emit" => '. incl %unop',
636 "comment" => "construct Decrement: Dec(a) = a--",
637 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
638 "emit" => '. decl %unop',
645 "comment" => "construct Not: Not(a) = !a",
646 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
647 "emit" => '. notl %unop',
655 "op_flags" => "L|X|Y",
656 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
657 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
658 "outs" => [ "false", "true" ],
660 "units" => [ "BRANCH" ],
664 "op_flags" => "L|X|Y",
665 "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
666 "reg_req" => { "in" => [ "gp", "gp" ] },
667 "outs" => [ "false", "true" ],
669 "units" => [ "BRANCH" ],
673 "op_flags" => "L|X|Y",
674 "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
675 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
676 "outs" => [ "false", "true" ],
677 "units" => [ "BRANCH" ],
681 "op_flags" => "L|X|Y",
682 "comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
683 "reg_req" => { "in" => [ "gp", "gp" ] },
684 "units" => [ "BRANCH" ],
688 "op_flags" => "L|X|Y",
689 "comment" => "construct switch",
690 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
692 "units" => [ "BRANCH" ],
698 "comment" => "represents an integer constant",
699 "reg_req" => { "out" => [ "gp" ] },
707 "comment" => "unknown value",
708 "reg_req" => { "out" => [ "gp_UKNWN" ] },
717 "comment" => "unknown value",
718 "reg_req" => { "out" => [ "vfp_UKNWN" ] },
727 "comment" => "unknown value",
728 "reg_req" => { "out" => [ "xmm_UKNWN" ] },
737 "comment" => "unknown GP value",
738 "reg_req" => { "out" => [ "gp_NOREG" ] },
747 "comment" => "unknown VFP value",
748 "reg_req" => { "out" => [ "vfp_NOREG" ] },
757 "comment" => "unknown XMM value",
758 "reg_req" => { "out" => [ "xmm_NOREG" ] },
766 "comment" => "change floating point control word",
767 "reg_req" => { "out" => [ "fp_cw" ] },
775 "state" => "exc_pinned",
776 "comment" => "load floating point control word FldCW(ptr, mem) = LD ptr -> reg",
777 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "fp_cw" ] },
779 "emit" => ". fldcw %AM",
786 "state" => "exc_pinned",
787 "comment" => "store floating point control word: FstCW(ptr, mem) = ST ptr -> reg",
788 "reg_req" => { "in" => [ "gp", "gp", "fp_cw", "none" ] },
790 "emit" => ". fstcw %AM",
796 # we should not rematrialize this node. It produces 2 results and has
797 # very strict constrains
798 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
799 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
801 "outs" => [ "EAX", "EDX" ],
809 "state" => "exc_pinned",
810 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
811 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp", "none" ] },
813 "emit" => ". mov%SE%ME%.l %AM, %D1",
814 "outs" => [ "res", "M" ],
820 "cmp_attr" => "return 1;",
821 "comment" => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg",
822 "outs" => [ "res", "M" ],
828 "cmp_attr" => "return 1;",
829 "state" => "exc_pinned",
830 "comment" => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val",
837 "state" => "exc_pinned",
838 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
839 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
840 "emit" => '. mov%M %binop',
848 "state" => "exc_pinned",
849 "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
850 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
851 "emit" => '. mov%M %binop',
859 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
860 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
861 "emit" => '. leal %AM, %D1',
868 "comment" => "push on the stack",
869 "reg_req" => { "in" => [ "gp", "gp", "gp", "esp", "none" ], "out" => [ "esp", "none" ] },
870 "emit" => '. pushl %unop',
871 "outs" => [ "stack:I|S", "M" ],
877 "comment" => "pop a gp register from the stack",
878 "reg_req" => { "in" => [ "gp", "gp", "esp", "none" ], "out" => [ "esp", "gp", "none" ] },
879 "emit" => '. popl %unop',
880 "outs" => [ "stack:I|S", "res", "M" ],
886 "comment" => "create stack frame",
887 "reg_req" => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] },
889 "outs" => [ "frame:I", "stack:I|S", "M" ],
895 "comment" => "destroy stack frame",
896 "reg_req" => { "in" => [ "esp", "ebp" ], "out" => [ "ebp", "esp" ] },
898 "outs" => [ "frame:I", "stack:I|S" ],
905 "comment" => "allocate space on stack",
906 "reg_req" => { "in" => [ "gp", "gp", "esp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
907 "emit" => '. addl %binop',
908 "outs" => [ "stack:S", "M" ],
914 "comment" => "free space on stack",
915 "reg_req" => { "in" => [ "gp", "gp", "esp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
916 "emit" => '. subl %binop',
917 "outs" => [ "stack:S", "M" ],
923 "comment" => "get the TLS base address",
924 "reg_req" => { "out" => [ "gp" ] },
930 #-----------------------------------------------------------------------------#
931 # _____ _____ ______ __ _ _ _ #
932 # / ____/ ____| ____| / _| | | | | | #
933 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
934 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
935 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
936 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
937 #-----------------------------------------------------------------------------#
939 # commutative operations
943 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
944 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
945 "emit" => '. adds%M %binop',
947 "units" => [ "SSE" ],
953 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
954 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
955 "emit" => '. muls%M %binop',
957 "units" => [ "SSE" ],
963 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
964 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
965 "emit" => '. maxs%M %binop',
967 "units" => [ "SSE" ],
973 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
974 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
975 "emit" => '. mins%M %binop',
977 "units" => [ "SSE" ],
983 "comment" => "construct SSE And: And(a, b) = a AND b",
984 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
985 "emit" => '. andp%M %binop',
987 "units" => [ "SSE" ],
993 "comment" => "construct SSE Or: Or(a, b) = a OR b",
994 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
995 "emit" => '. orp%M %binop',
996 "units" => [ "SSE" ],
1002 "comment" => "construct SSE Xor: Xor(a, b) = a XOR b",
1003 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
1004 "emit" => '. xorp%M %binop',
1006 "units" => [ "SSE" ],
1010 # not commutative operations
1014 "comment" => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
1015 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
1016 "emit" => '. andnp%M %binop',
1018 "units" => [ "SSE" ],
1024 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
1025 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
1026 "emit" => '. subs%M %binop',
1028 "units" => [ "SSE" ],
1034 "comment" => "construct SSE Div: Div(a, b) = a / b",
1035 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
1036 "outs" => [ "res", "M" ],
1037 "emit" => '. divs%M %binop',
1039 "units" => [ "SSE" ],
1046 "comment" => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
1047 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
1049 "units" => [ "SSE" ],
1054 "op_flags" => "L|X|Y",
1055 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
1056 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
1057 "outs" => [ "false", "true" ],
1059 "units" => [ "SSE" ],
1065 "comment" => "represents a SSE constant",
1066 "reg_req" => { "out" => [ "xmm" ] },
1067 "emit" => '. movs%M %D1, $%C',
1069 "units" => [ "SSE" ],
1076 "op_flags" => "L|F",
1077 "state" => "exc_pinned",
1078 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
1079 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
1080 "emit" => '. movs%M %D1, %AM',
1081 "outs" => [ "res", "M" ],
1083 "units" => [ "SSE" ],
1087 "op_flags" => "L|F",
1088 "state" => "exc_pinned",
1089 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
1090 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
1091 "emit" => '. movs%M %binop',
1093 "units" => [ "SSE" ],
1098 "op_flags" => "L|F",
1099 "state" => "exc_pinned",
1100 "comment" => "construct Store without index: Store(ptr, val, mem) = ST ptr,val",
1101 "reg_req" => { "in" => [ "gp", "xmm", "none" ] },
1102 "emit" => '. movs%M %AM, %S2',
1104 "units" => [ "SSE" ],
1109 "op_flags" => "L|F",
1110 "comment" => "construct: transfer a value from x87 FPU into a SSE register",
1111 "cmp_attr" => "return 1;",
1116 "op_flags" => "L|F",
1117 "comment" => "construct: transfer a value from SSE register to x87 FPU",
1118 "cmp_attr" => "return 1;",
1123 "op_flags" => "L|F",
1125 "state" => "exc_pinned",
1126 "comment" => "store ST0 onto stack",
1127 "reg_req" => { "in" => [ "gp", "gp", "none" ] },
1128 "emit" => '. fstp%M %AM',
1130 "units" => [ "SSE" ],
1135 "op_flags" => "L|F",
1137 "state" => "exc_pinned",
1138 "comment" => "load ST0 from stack",
1139 "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "vf0", "none" ] },
1140 "emit" => '. fld%M %AM',
1141 "outs" => [ "res", "M" ],
1143 "units" => [ "SSE" ],
1149 "op_flags" => "F|H",
1150 "state" => "pinned",
1151 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
1152 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "edi", "esi", "ecx", "none" ] },
1153 "outs" => [ "DST", "SRC", "CNT", "M" ],
1154 "units" => [ "GP" ],
1158 "op_flags" => "F|H",
1159 "state" => "pinned",
1160 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
1161 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "edi", "esi", "none" ] },
1162 "outs" => [ "DST", "SRC", "M" ],
1163 "units" => [ "GP" ],
1169 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
1170 "comment" => "construct Conv Int -> Int",
1171 "units" => [ "GP" ],
1172 "mode" => "mode_Iu",
1176 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
1177 "comment" => "construct Conv Int -> Int",
1178 "units" => [ "GP" ],
1179 "mode" => "mode_Iu",
1183 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
1184 "comment" => "construct Conv Int -> Floating Point",
1186 "units" => [ "SSE" ],
1191 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
1192 "comment" => "construct Conv Floating Point -> Int",
1194 "units" => [ "SSE" ],
1195 "mode" => "mode_Iu",
1199 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
1200 "comment" => "construct Conv Floating Point -> Floating Point",
1202 "units" => [ "SSE" ],
1208 "comment" => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
1209 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "in_r4" ] },
1211 "units" => [ "GP" ],
1212 "mode" => "mode_Iu",
1217 "comment" => "check if Psi condition tree evaluates to true and move result accordingly",
1218 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r3" ] },
1220 "units" => [ "GP" ],
1221 "mode" => "mode_Iu",
1226 "comment" => "construct Conditional Move: SSE Compare + int CMov ",
1227 "reg_req" => { "in" => [ "xmm", "xmm", "gp", "gp" ], "out" => [ "in_r4" ] },
1229 "units" => [ "SSE" ],
1230 "mode" => "mode_Iu",
1235 "comment" => "construct Conditional Move: x87 Compare + int CMov",
1236 "reg_req" => { "in" => [ "vfp", "vfp", "gp", "gp" ], "out" => [ "in_r4" ] },
1238 "units" => [ "VFP" ],
1239 "mode" => "mode_Iu",
1244 "comment" => "construct Set: Set(sel) == sel ? 1 : 0",
1245 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax ebx ecx edx" ] },
1247 "units" => [ "GP" ],
1248 "mode" => "mode_Iu",
1253 "comment" => "check if Psi condition tree evaluates to true and set result accordingly",
1254 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax ebx ecx edx" ] },
1256 "units" => [ "GP" ],
1257 "mode" => "mode_Iu",
1262 "comment" => "construct Set: SSE Compare + int Set",
1263 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "eax ebx ecx edx" ] },
1265 "units" => [ "SSE" ],
1266 "mode" => "mode_Iu",
1271 "comment" => "construct Set: x87 Compare + int Set",
1272 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "eax ebx ecx edx" ] },
1274 "units" => [ "VFP" ],
1275 "mode" => "mode_Iu",
1280 "comment" => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
1281 "reg_req" => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] },
1283 "units" => [ "VFP" ],
1287 #----------------------------------------------------------#
1289 # (_) | | | | / _| | | | #
1290 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
1291 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
1292 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
1293 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
1295 # _ __ ___ __| | ___ ___ #
1296 # | '_ \ / _ \ / _` |/ _ \/ __| #
1297 # | | | | (_) | (_| | __/\__ \ #
1298 # |_| |_|\___/ \__,_|\___||___/ #
1299 #----------------------------------------------------------#
1303 "comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
1304 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1306 "units" => [ "VFP" ],
1312 "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1313 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1315 "units" => [ "VFP" ],
1321 "cmp_attr" => "return 1;",
1322 "comment" => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1328 "comment" => "virtual fp Sub: Sub(a, b) = a - b",
1329 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1331 "units" => [ "VFP" ],
1336 "cmp_attr" => "return 1;",
1337 "comment" => "lowered virtual fp Sub: Sub(a, b) = a - b",
1342 "comment" => "virtual fp Div: Div(a, b) = a / b",
1343 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1344 "outs" => [ "res", "M" ],
1346 "units" => [ "VFP" ],
1350 "cmp_attr" => "return 1;",
1351 "comment" => "lowered virtual fp Div: Div(a, b) = a / b",
1352 "outs" => [ "res", "M" ],
1357 "comment" => "virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1358 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1360 "units" => [ "VFP" ],
1365 "cmp_attr" => "return 1;",
1366 "comment" => "lowered virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1372 "comment" => "virtual fp Abs: Abs(a) = |a|",
1373 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1375 "units" => [ "VFP" ],
1381 "comment" => "virtual fp Chs: Chs(a) = -a",
1382 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1384 "units" => [ "VFP" ],
1390 "comment" => "virtual fp Sin: Sin(a) = sin(a)",
1391 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1393 "units" => [ "VFP" ],
1399 "comment" => "virtual fp Cos: Cos(a) = cos(a)",
1400 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1402 "units" => [ "VFP" ],
1408 "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
1409 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1411 "units" => [ "VFP" ],
1415 # virtual Load and Store
1418 "op_flags" => "L|F",
1419 "state" => "exc_pinned",
1420 "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
1421 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1422 "outs" => [ "res", "M" ],
1424 "units" => [ "VFP" ],
1428 "op_flags" => "L|F",
1429 "state" => "exc_pinned",
1430 "comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
1431 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1433 "units" => [ "VFP" ],
1440 "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1441 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1442 "outs" => [ "res", "M" ],
1444 "units" => [ "VFP" ],
1448 "cmp_attr" => "return 1;",
1449 "comment" => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1450 "outs" => [ "res", "M" ],
1455 "comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1456 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1458 "units" => [ "VFP" ],
1463 "cmp_attr" => "return 1;",
1464 "comment" => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1474 "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg",
1475 "reg_req" => { "out" => [ "vfp" ] },
1477 "units" => [ "VFP" ],
1483 "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg",
1484 "reg_req" => { "out" => [ "vfp" ] },
1486 "units" => [ "VFP" ],
1492 "comment" => "virtual fp Load pi: Ld pi -> reg",
1493 "reg_req" => { "out" => [ "vfp" ] },
1495 "units" => [ "VFP" ],
1501 "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg",
1502 "reg_req" => { "out" => [ "vfp" ] },
1504 "units" => [ "VFP" ],
1510 "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg",
1511 "reg_req" => { "out" => [ "vfp" ] },
1513 "units" => [ "VFP" ],
1519 "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg",
1520 "reg_req" => { "out" => [ "vfp" ] },
1522 "units" => [ "VFP" ],
1528 "comment" => "virtual fp Load ld e: Ld ld e -> reg",
1529 "reg_req" => { "out" => [ "vfp" ] },
1531 "units" => [ "VFP" ],
1538 # "init_attr" => " set_ia32_ls_mode(res, mode);",
1539 "comment" => "represents a virtual floating point constant",
1540 "reg_req" => { "out" => [ "vfp" ] },
1542 "units" => [ "VFP" ],
1549 "op_flags" => "L|X|Y",
1550 "comment" => "represents a virtual floating point compare",
1551 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] },
1552 "outs" => [ "false", "true", "temp_reg_eax" ],
1554 "units" => [ "VFP" ],
1557 #------------------------------------------------------------------------#
1558 # ___ _____ __ _ _ _ #
1559 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1560 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1561 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1562 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1563 #------------------------------------------------------------------------#
1567 "rd_constructor" => "NONE",
1568 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1570 "emit" => '. fadd%XM %x87_binop',
1575 "rd_constructor" => "NONE",
1576 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1578 "emit" => '. faddp %x87_binop',
1583 "rd_constructor" => "NONE",
1584 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1586 "emit" => '. fmul%XM %x87_binop',
1591 "rd_constructor" => "NONE",
1592 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1594 "emit" => '. fmulp %x87_binop',,
1599 "rd_constructor" => "NONE",
1600 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1602 "emit" => '. fsub%XM %x87_binop',
1607 "rd_constructor" => "NONE",
1608 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1610 "emit" => '. fsubp %x87_binop',
1615 "rd_constructor" => "NONE",
1617 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1619 "emit" => '. fsubr%XM %x87_binop',
1624 "rd_constructor" => "NONE",
1626 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1628 "emit" => '. fsubrp %x87_binop',
1633 "rd_constructor" => "NONE",
1634 "comment" => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1636 "emit" => '. fprem1',
1639 # this node is just here, to keep the simulator running
1640 # we can omit this when a fprem simulation function exists
1643 "rd_constructor" => "NONE",
1644 "comment" => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1646 "emit" => '. fprem1',
1651 "rd_constructor" => "NONE",
1652 "comment" => "x87 fp Div: Div(a, b) = a / b",
1654 "emit" => '. fdiv%XM %x87_binop',
1659 "rd_constructor" => "NONE",
1660 "comment" => "x87 fp Div: Div(a, b) = a / b",
1662 "emit" => '. fdivp %x87_binop',
1667 "rd_constructor" => "NONE",
1668 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1670 "emit" => '. fdivr%XM %x87_binop',
1675 "rd_constructor" => "NONE",
1676 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1678 "emit" => '. fdivrp %x87_binop',
1683 "rd_constructor" => "NONE",
1684 "comment" => "x87 fp Abs: Abs(a) = |a|",
1691 "rd_constructor" => "NONE",
1692 "comment" => "x87 fp Chs: Chs(a) = -a",
1699 "rd_constructor" => "NONE",
1700 "comment" => "x87 fp Sin: Sin(a) = sin(a)",
1707 "rd_constructor" => "NONE",
1708 "comment" => "x87 fp Cos: Cos(a) = cos(a)",
1715 "rd_constructor" => "NONE",
1716 "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1718 "emit" => '. fsqrt $',
1721 # x87 Load and Store
1724 "rd_constructor" => "NONE",
1725 "op_flags" => "R|L|F",
1726 "state" => "exc_pinned",
1727 "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1729 "emit" => '. fld%M %AM',
1733 "rd_constructor" => "NONE",
1734 "op_flags" => "R|L|F",
1735 "state" => "exc_pinned",
1736 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1738 "emit" => '. fst%M %AM',
1743 "rd_constructor" => "NONE",
1744 "op_flags" => "R|L|F",
1745 "state" => "exc_pinned",
1746 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1748 "emit" => '. fstp%M %AM',
1756 "rd_constructor" => "NONE",
1757 "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1759 "emit" => '. fild%M %AM',
1764 "rd_constructor" => "NONE",
1765 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1767 "emit" => '. fist%M %AM',
1773 "rd_constructor" => "NONE",
1774 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1776 "emit" => '. fistp%M %AM',
1783 "op_flags" => "R|c",
1785 "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
1786 "reg_req" => { "out" => [ "vfp" ] },
1791 "op_flags" => "R|c",
1793 "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
1794 "reg_req" => { "out" => [ "vfp" ] },
1799 "op_flags" => "R|c",
1801 "comment" => "x87 fp Load pi: Ld pi -> reg",
1802 "reg_req" => { "out" => [ "vfp" ] },
1803 "emit" => '. fldpi',
1807 "op_flags" => "R|c",
1809 "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
1810 "reg_req" => { "out" => [ "vfp" ] },
1811 "emit" => '. fldln2',
1815 "op_flags" => "R|c",
1817 "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
1818 "reg_req" => { "out" => [ "vfp" ] },
1819 "emit" => '. fldlg2',
1823 "op_flags" => "R|c",
1825 "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
1826 "reg_req" => { "out" => [ "vfp" ] },
1827 "emit" => '. fldll2t',
1831 "op_flags" => "R|c",
1833 "comment" => "x87 fp Load ld e: Ld ld e -> reg",
1834 "reg_req" => { "out" => [ "vfp" ] },
1835 "emit" => '. fldl2e',
1839 "op_flags" => "R|c",
1841 "rd_constructor" => "NONE",
1842 "comment" => "represents a x87 constant",
1843 "reg_req" => { "out" => [ "vfp" ] },
1844 "emit" => '. fld $%C',
1848 # Note that it is NEVER allowed to do CSE on these nodes
1849 # Moreover, note the virtual register requierements!
1852 "op_flags" => "R|K",
1853 "comment" => "x87 stack exchange",
1855 "cmp_attr" => "return 1;",
1856 "emit" => '. fxch %X1',
1860 "op_flags" => "R|K",
1861 "comment" => "x87 stack push",
1863 "cmp_attr" => "return 1;",
1864 "emit" => '. fld %X1',
1869 "comment" => "x87 stack push",
1870 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1871 "cmp_attr" => "return 1;",
1872 "emit" => '. fld %X1',
1876 "op_flags" => "R|K",
1877 "comment" => "x87 stack pop",
1879 "cmp_attr" => "return 1;",
1880 "emit" => '. fstp %X1',
1886 "op_flags" => "L|X|Y",
1887 "comment" => "floating point compare",
1892 "op_flags" => "L|X|Y",
1893 "comment" => "floating point compare and pop",
1898 "op_flags" => "L|X|Y",
1899 "comment" => "floating point compare and pop twice",
1904 "op_flags" => "L|X|Y",
1905 "comment" => "floating point compare reverse",
1910 "op_flags" => "L|X|Y",
1911 "comment" => "floating point compare reverse and pop",
1916 "op_flags" => "L|X|Y",
1917 "comment" => "floating point compare reverse and pop twice",