3 # This is the specification for the ia32 assembler Firm-operations
10 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
13 # The node description is done as a perl hash initializer with the
14 # following structure:
19 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
20 # "irn_flags" => "R|N|I|S"
21 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
22 # "state" => "floats|pinned|mem_pinned|exc_pinned",
24 # { "type" => "type 1", "name" => "name 1" },
25 # { "type" => "type 2", "name" => "name 2" },
28 # "comment" => "any comment for constructor",
29 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
30 # "cmp_attr" => "c source code for comparing node attributes",
31 # "emit" => "emit code with templates",
32 # "attr" => "attitional attribute arguments for constructor"
33 # "init_attr" => "emit attribute initialization template"
34 # "rd_constructor" => "c source code which constructs an ir_node"
35 # "latency" => "latency of this operation (can be float)"
38 # ... # (all nodes you need to describe)
40 # ); # close the %nodes initializer
42 # op_flags: flags for the operation, OPTIONAL (default is "N")
43 # the op_flags correspond to the firm irop_flags:
46 # C irop_flag_commutative
47 # X irop_flag_cfopcode
48 # I irop_flag_ip_cfopcode
51 # H irop_flag_highlevel
52 # c irop_flag_constlike
55 # irn_flags: special node flags, OPTIONAL (default is 0)
56 # following irn_flags are supported:
59 # I ignore for register allocation
60 # S modifies stack pointer
62 # state: state of the operation, OPTIONAL (default is "floats")
64 # arity: arity of the operation, MUST NOT BE OMITTED
66 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
67 # are always the first 3 arguments and are always autmatically
69 # If this key is missing the following arguments will be created:
70 # for i = 1 .. arity: ir_node *op_i
73 # outs: if a node defines more than one output, the names of the projections
74 # nodes having outs having automatically the mode mode_T
75 # One can also annotate some flags for each out, additional to irn_flags.
76 # They are separated from name with a colon ':', and concatenated by pipe '|'
77 # Only I and S are available at the moment (same meaning as in irn_flags).
78 # example: [ "frame:I", "stack:I|S", "M" ]
80 # comment: OPTIONAL comment for the node constructor
82 # rd_constructor: for every operation there will be a
83 # new_rd_<arch>_<op-name> function with the arguments from above
84 # which creates the ir_node corresponding to the defined operation
85 # you can either put the complete source code of this function here
87 # This key is OPTIONAL. If omitted, the following constructor will
89 # if (!op_<arch>_<op-name>) assert(0);
93 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
96 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
98 # latency: the latency of the operation, default is 1
102 # 0 - no special type
103 # 1 - caller save (register must be saved by the caller of a function)
104 # 2 - callee save (register must be saved by the called function)
105 # 4 - ignore (do not assign this register)
106 # 8 - emitter can choose an arbitrary register of this class
107 # 16 - the register is a virtual one
108 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
111 { "name" => "eax", "type" => 1 },
112 { "name" => "edx", "type" => 1 },
113 { "name" => "ebx", "type" => 2 },
114 { "name" => "ecx", "type" => 1 },
115 { "name" => "esi", "type" => 2 },
116 { "name" => "edi", "type" => 2 },
117 { "name" => "ebp", "type" => 2 },
118 { "name" => "esp", "type" => 4 },
119 { "name" => "gp_NOREG", "type" => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
120 { "name" => "gp_UKNWN", "type" => 4 | 8 | 16 }, # we need a dummy register for Unknown nodes
121 { "mode" => "mode_Iu" }
124 { "name" => "xmm0", "type" => 1 },
125 { "name" => "xmm1", "type" => 1 },
126 { "name" => "xmm2", "type" => 1 },
127 { "name" => "xmm3", "type" => 1 },
128 { "name" => "xmm4", "type" => 1 },
129 { "name" => "xmm5", "type" => 1 },
130 { "name" => "xmm6", "type" => 1 },
131 { "name" => "xmm7", "type" => 1 },
132 { "name" => "xmm_NOREG", "type" => 4 | 16 }, # we need a dummy register for NoReg nodes
133 { "name" => "xmm_UKNWN", "type" => 4 | 8 | 16}, # we need a dummy register for Unknown nodes
134 { "mode" => "mode_E" }
137 { "name" => "vf0", "type" => 1 | 16 },
138 { "name" => "vf1", "type" => 1 | 16 },
139 { "name" => "vf2", "type" => 1 | 16 },
140 { "name" => "vf3", "type" => 1 | 16 },
141 { "name" => "vf4", "type" => 1 | 16 },
142 { "name" => "vf5", "type" => 1 | 16 },
143 { "name" => "vf6", "type" => 1 | 16 },
144 { "name" => "vf7", "type" => 1 | 16 },
145 { "name" => "vfp_NOREG", "type" => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
146 { "name" => "vfp_UKNWN", "type" => 4 | 8 | 16 }, # we need a dummy register for Unknown nodes
147 { "mode" => "mode_E" }
150 { "name" => "st0", "type" => 1 },
151 { "name" => "st1", "type" => 1 },
152 { "name" => "st2", "type" => 1 },
153 { "name" => "st3", "type" => 1 },
154 { "name" => "st4", "type" => 1 },
155 { "name" => "st5", "type" => 1 },
156 { "name" => "st6", "type" => 1 },
157 { "name" => "st7", "type" => 1 },
158 { "mode" => "mode_E" }
160 "fp_cw" => [ # the floating point control word
161 { "name" => "fpcw", "type" => 0 },
162 { "mode" => "mode_Hu" },
168 "GP" => [ 1, "GP_EAX", "GP_EBX", "GP_ECX", "GP_EDX", "GP_ESI", "GP_EDI", "GP_EBP" ],
169 "SSE" => [ 1, "SSE_XMM0", "SSE_XMM1", "SSE_XMM2", "SSE_XMM3", "SSE_XMM4", "SSE_XMM5", "SSE_XMM6", "SSE_XMM7" ],
170 "VFP" => [ 1, "VFP_VF0", "VFP_VF1", "VFP_VF2", "VFP_VF3", "VFP_VF4", "VFP_VF5", "VFP_VF6", "VFP_VF7" ],
171 "BRANCH" => [ 1, "BRANCH1", "BRANCH2" ],
176 "bundels_per_cycle" => 1
180 "S1" => "${arch}_emit_source_register(env, node, 0);",
181 "S2" => "${arch}_emit_source_register(env, node, 1);",
182 "S3" => "${arch}_emit_source_register(env, node, 2);",
183 "S4" => "${arch}_emit_source_register(env, node, 3);",
184 "S5" => "${arch}_emit_source_register(env, node, 4);",
185 "S6" => "${arch}_emit_source_register(env, node, 5);",
186 "D1" => "${arch}_emit_dest_register(env, node, 0);",
187 "D2" => "${arch}_emit_dest_register(env, node, 1);",
188 "D3" => "${arch}_emit_dest_register(env, node, 2);",
189 "D4" => "${arch}_emit_dest_register(env, node, 3);",
190 "D5" => "${arch}_emit_dest_register(env, node, 4);",
191 "D6" => "${arch}_emit_dest_register(env, node, 5);",
192 "A1" => "${arch}_emit_in_node_name(env, node, 0);",
193 "A2" => "${arch}_emit_in_node_name(env, node, 1);",
194 "A3" => "${arch}_emit_in_node_name(env, node, 2);",
195 "A4" => "${arch}_emit_in_node_name(env, node, 3);",
196 "A5" => "${arch}_emit_in_node_name(env, node, 4);",
197 "A6" => "${arch}_emit_in_node_name(env, node, 5);",
198 "X1" => "${arch}_emit_x87_name(env, node, 0);",
199 "X2" => "${arch}_emit_x87_name(env, node, 1);",
200 "X3" => "${arch}_emit_x87_name(env, node, 2);",
201 "C" => "${arch}_emit_immediate(env, node);",
202 "SE" => "${arch}_emit_extend_suffix(env, get_ia32_ls_mode(node));",
203 "ME" => "if(get_mode_size_bits(get_ia32_ls_mode(node)) != 32)\n
204 ia32_emit_mode_suffix(env, get_ia32_ls_mode(node));",
205 "M" => "${arch}_emit_mode_suffix(env, get_ia32_ls_mode(node));",
206 "XM" => "${arch}_emit_x87_mode_suffix(env, node);",
207 "XXM" => "${arch}_emit_xmm_mode_suffix(env, node);",
208 "XSD" => "${arch}_emit_xmm_mode_suffix_s(env, node);",
209 "AM" => "${arch}_emit_am(env, node);",
210 "unop" => "${arch}_emit_unop(env, node);",
211 "binop" => "${arch}_emit_binop(env, node);",
212 "x87_binop" => "${arch}_emit_x87_binop(env, node);",
215 #--------------------------------------------------#
218 # _ __ _____ __ _ _ __ ___ _ __ ___ #
219 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
220 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
221 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
224 #--------------------------------------------------#
226 $default_cmp_attr = "return ia32_compare_attr(attr_a, attr_b);";
233 #-----------------------------------------------------------------#
236 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
237 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
238 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
239 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
242 #-----------------------------------------------------------------#
244 # commutative operations
247 # All nodes supporting Addressmode have 5 INs:
248 # 1 - base r1 == NoReg in case of no AM or no base
249 # 2 - index r2 == NoReg in case of no AM or no index
250 # 3 - op1 r3 == always present
251 # 4 - op2 r4 == NoReg in case of immediate operation
252 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
256 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
257 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
258 "emit" => '. addl %binop',
264 "comment" => "construct Add with Carry: Adc(a, b) = Add(b, a) = a + b + carry",
265 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
266 "emit" => '. adcl %binop',
273 "comment" => "construct 64Bit Add: Add(a_l, a_h, b_l, b_h) = a_l + b_l; a_h + b_h + carry",
275 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
282 "outs" => [ "low_res", "high_res" ],
289 "cmp_attr" => "return 1;",
290 "comment" => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
296 "cmp_attr" => "return 1;",
297 "comment" => "construct lowered Add with Carry: Adc(a, b) = Adc(b, a) = a + b + carry",
302 # we should not rematrialize this node. It produces 2 results and has
303 # very strict constrains
304 "comment" => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
305 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx", "none" ] },
306 "emit" => '. mull %unop',
307 "outs" => [ "EAX", "EDX", "M" ],
313 # we should not rematrialize this node. It produces 2 results and has
314 # very strict constrains
316 "cmp_attr" => "return 1;",
317 "comment" => "construct lowered MulS: Mul(a, b) = Mul(b, a) = a * b",
318 "outs" => [ "EAX", "EDX", "M" ],
324 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
325 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
326 "emit" => '. imull %binop',
334 "comment" => "construct Mul (1 operand format): Mul(a, b) = Mul(b, a) = a * b",
335 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx", "none" ] },
336 "emit" => '. imull %unop',
337 "outs" => [ "EAX", "EDX", "M" ],
344 "cmp_attr" => "return 1;",
345 "comment" => "construct lowered IMul: IMul(a, b) = IMul(b, a) = a * b",
351 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
352 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
353 "emit" => '. andl %binop',
360 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
361 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
362 "emit" => '. orl %binop',
369 "comment" => "construct Xor: Xor(a, b) = Xor(b, a) = a EOR b",
370 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
371 "emit" => '. xorl %binop',
378 "cmp_attr" => "return 1;",
379 "comment" => "construct lowered Xor: Xor(a, b) = Xor(b, a) = a XOR b",
383 # not commutative operations
387 "comment" => "construct Sub: Sub(a, b) = a - b",
388 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
389 "emit" => '. subl %binop',
395 "comment" => "construct Sub with Carry: SubC(a, b) = a - b - carry",
396 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3 !in_r4" ] },
397 "emit" => '. sbbl %binop',
404 "comment" => "construct 64Bit Sub: Sub(a_l, a_h, b_l, b_h) = a_l - b_l; a_h - b_h - borrow",
406 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
413 "outs" => [ "low_res", "high_res" ],
419 "cmp_attr" => "return 1;",
420 "comment" => "construct lowered Sub: Sub(a, b) = a - b",
425 "cmp_attr" => "return 1;",
426 "comment" => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
432 "state" => "exc_pinned",
433 "reg_req" => { "in" => [ "gp", "gp", "eax", "edx", "gp", "none" ], "out" => [ "eax", "edx", "none" ] },
434 "attr" => "ia32_op_flavour_t dm_flav",
435 "init_attr" => "attr->data.op_flav = dm_flav;",
436 "emit" => ". idivl %unop",
437 "outs" => [ "div_res", "mod_res", "M" ],
444 "state" => "exc_pinned",
445 "reg_req" => { "in" => [ "gp", "gp", "eax", "edx", "gp", "none" ], "out" => [ "eax", "edx", "none" ] },
446 "attr" => "ia32_op_flavour_t dm_flav",
447 "init_attr" => "attr->data.op_flav = dm_flav;",
448 "emit" => ". divl %unop",
449 "outs" => [ "div_res", "mod_res", "M" ],
456 "comment" => "construct Shl: Shl(a, b) = a << b",
457 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
458 "emit" => '. shll %binop',
464 "cmp_attr" => "return 1;",
465 "comment" => "construct lowered Shl: Shl(a, b) = a << b",
471 "comment" => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
472 # Out requirements is: different from all in
473 # This is because, out must be different from LowPart and ShiftCount.
474 # We could say "!ecx !in_r4" but it can occur, that all values live through
475 # this Shift and the only value dying is the ShiftCount. Then there would be a
476 # register missing, as result must not be ecx and all other registers are
477 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
478 # (and probably never will). So we create artificial interferences of the result
479 # with all inputs, so the spiller can always assure a free register.
480 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!in" ] },
483 if (get_ia32_immop_type(node) == ia32_ImmNone) {
484 if (get_ia32_op_type(node) == ia32_AddrModeD) {
485 . shldl %%cl, %S4, %AM
487 . shldl %%cl, %S4, %S3
490 if (get_ia32_op_type(node) == ia32_AddrModeD) {
491 . shldl $%C, %S4, %AM
493 . shldl $%C, %S4, %S3
503 "cmp_attr" => "return 1;",
504 "comment" => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
510 "comment" => "construct Shr: Shr(a, b) = a >> b",
511 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
512 "emit" => '. shrl %binop',
518 "cmp_attr" => "return 1;",
519 "comment" => "construct lowered Shr: Shr(a, b) = a << b",
525 "comment" => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
526 # Out requirements is: different from all in
527 # This is because, out must be different from LowPart and ShiftCount.
528 # We could say "!ecx !in_r4" but it can occur, that all values live through
529 # this Shift and the only value dying is the ShiftCount. Then there would be a
530 # register missing, as result must not be ecx and all other registers are
531 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
532 # (and probably never will). So we create artificial interferences of the result
533 # with all inputs, so the spiller can always assure a free register.
534 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!in" ] },
536 if (get_ia32_immop_type(node) == ia32_ImmNone) {
537 if (get_ia32_op_type(node) == ia32_AddrModeD) {
538 . shrdl %%cl, %S4, %AM
540 . shrdl %%cl, %S4, %S3
543 if (get_ia32_op_type(node) == ia32_AddrModeD) {
544 . shrdl $%C, %S4, %AM
546 . shrdl $%C, %S4, %S3
556 "cmp_attr" => "return 1;",
557 "comment" => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
563 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
564 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
565 "emit" => '. sarl %binop',
571 "cmp_attr" => "return 1;",
572 "comment" => "construct lowered Sar: Sar(a, b) = a << b",
578 "comment" => "construct Ror: Ror(a, b) = a ROR b",
579 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
580 "emit" => '. rorl %binop',
587 "comment" => "construct Rol: Rol(a, b) = a ROL b",
588 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
589 "emit" => '. roll %binop',
598 "comment" => "construct Minus: Minus(a) = -a",
599 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
600 "emit" => '. negl %unop',
607 "comment" => "construct 64Bit Minus: Minus(a_l, a_h, 0) = 0 - a_l; 0 - a_h - borrow",
609 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
616 "outs" => [ "low_res", "high_res" ],
622 "cmp_attr" => "return 1;",
623 "comment" => "construct lowered Minus: Minus(a) = -a",
629 "comment" => "construct Increment: Inc(a) = a++",
630 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
631 "emit" => '. incl %unop',
638 "comment" => "construct Decrement: Dec(a) = a--",
639 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
640 "emit" => '. decl %unop',
647 "comment" => "construct Not: Not(a) = !a",
648 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
649 "emit" => '. notl %unop',
657 "op_flags" => "L|X|Y",
658 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
659 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
660 "outs" => [ "false", "true" ],
662 "units" => [ "BRANCH" ],
666 "op_flags" => "L|X|Y",
667 "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
668 "reg_req" => { "in" => [ "gp", "gp" ] },
669 "outs" => [ "false", "true" ],
671 "units" => [ "BRANCH" ],
675 "op_flags" => "L|X|Y",
676 "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
677 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
678 "outs" => [ "false", "true" ],
679 "units" => [ "BRANCH" ],
683 "op_flags" => "L|X|Y",
684 "comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
685 "reg_req" => { "in" => [ "gp", "gp" ] },
686 "units" => [ "BRANCH" ],
690 "op_flags" => "L|X|Y",
691 "comment" => "construct switch",
692 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
694 "units" => [ "BRANCH" ],
700 "comment" => "represents an integer constant",
701 "reg_req" => { "out" => [ "gp" ] },
709 "comment" => "unknown value",
710 "reg_req" => { "out" => [ "gp_UKNWN" ] },
719 "comment" => "unknown value",
720 "reg_req" => { "out" => [ "vfp_UKNWN" ] },
729 "comment" => "unknown value",
730 "reg_req" => { "out" => [ "xmm_UKNWN" ] },
739 "comment" => "unknown GP value",
740 "reg_req" => { "out" => [ "gp_NOREG" ] },
749 "comment" => "unknown VFP value",
750 "reg_req" => { "out" => [ "vfp_NOREG" ] },
759 "comment" => "unknown XMM value",
760 "reg_req" => { "out" => [ "xmm_NOREG" ] },
768 "comment" => "change floating point control word",
769 "reg_req" => { "out" => [ "fp_cw" ] },
777 "state" => "exc_pinned",
778 "comment" => "load floating point control word FldCW(ptr, mem) = LD ptr -> reg",
779 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "fp_cw" ] },
781 "emit" => ". fldcw %AM",
788 "state" => "exc_pinned",
789 "comment" => "store floating point control word: FstCW(ptr, mem) = ST ptr -> reg",
790 "reg_req" => { "in" => [ "gp", "gp", "fp_cw", "none" ] },
792 "emit" => ". fstcw %AM",
798 # we should not rematrialize this node. It produces 2 results and has
799 # very strict constrains
800 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
801 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
803 "outs" => [ "EAX", "EDX" ],
811 "state" => "exc_pinned",
812 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
813 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp", "none" ] },
815 "emit" => ". mov%SE%ME%.l %AM, %D1",
816 "outs" => [ "res", "M" ],
822 "cmp_attr" => "return 1;",
823 "comment" => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg",
824 "outs" => [ "res", "M" ],
830 "cmp_attr" => "return 1;",
831 "state" => "exc_pinned",
832 "comment" => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val",
839 "state" => "exc_pinned",
840 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
841 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "none" ] },
842 "emit" => '. mov%M %binop',
850 "state" => "exc_pinned",
851 "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
852 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => ["none" ] },
853 "emit" => '. mov%M %binop',
861 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
862 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
863 "emit" => '. leal %AM, %D1',
870 "comment" => "push on the stack",
871 "reg_req" => { "in" => [ "gp", "gp", "gp", "esp", "none" ], "out" => [ "esp", "none" ] },
872 "emit" => '. pushl %unop',
873 "outs" => [ "stack:I|S", "M" ],
879 "comment" => "pop a gp register from the stack",
880 "reg_req" => { "in" => [ "gp", "gp", "esp", "none" ], "out" => [ "esp", "gp", "none" ] },
881 "emit" => '. popl %unop',
882 "outs" => [ "stack:I|S", "res", "M" ],
888 "comment" => "create stack frame",
889 "reg_req" => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] },
891 "outs" => [ "frame:I", "stack:I|S", "M" ],
897 "comment" => "destroy stack frame",
898 "reg_req" => { "in" => [ "esp", "ebp" ], "out" => [ "ebp", "esp" ] },
900 "outs" => [ "frame:I", "stack:I|S" ],
907 "comment" => "allocate space on stack",
908 "reg_req" => { "in" => [ "gp", "gp", "esp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
909 "emit" => '. addl %binop',
910 "outs" => [ "stack:S", "M" ],
916 "comment" => "free space on stack",
917 "reg_req" => { "in" => [ "gp", "gp", "esp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
918 "emit" => '. subl %binop',
919 "outs" => [ "stack:S", "M" ],
925 "comment" => "get the TLS base address",
926 "reg_req" => { "out" => [ "gp" ] },
932 #-----------------------------------------------------------------------------#
933 # _____ _____ ______ __ _ _ _ #
934 # / ____/ ____| ____| / _| | | | | | #
935 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
936 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
937 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
938 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
939 #-----------------------------------------------------------------------------#
941 # commutative operations
945 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
946 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
947 "emit" => '. add%XXM %binop',
949 "units" => [ "SSE" ],
955 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
956 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
957 "emit" => '. mul%XXM %binop',
959 "units" => [ "SSE" ],
965 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
966 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
967 "emit" => '. max%XXM %binop',
969 "units" => [ "SSE" ],
975 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
976 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
977 "emit" => '. min%XXM %binop',
979 "units" => [ "SSE" ],
985 "comment" => "construct SSE And: And(a, b) = a AND b",
986 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
987 "emit" => '. andp%XSD %binop',
989 "units" => [ "SSE" ],
995 "comment" => "construct SSE Or: Or(a, b) = a OR b",
996 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
997 "emit" => '. orp%XSD %binop',
998 "units" => [ "SSE" ],
1004 "comment" => "construct SSE Xor: Xor(a, b) = a XOR b",
1005 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
1006 "emit" => '. xorp%XSD %binop',
1008 "units" => [ "SSE" ],
1012 # not commutative operations
1016 "comment" => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
1017 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
1018 "emit" => '. andnp%XSD %binop',
1020 "units" => [ "SSE" ],
1026 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
1027 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
1028 "emit" => '. sub%XXM %binop',
1030 "units" => [ "SSE" ],
1036 "comment" => "construct SSE Div: Div(a, b) = a / b",
1037 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
1038 "outs" => [ "res", "M" ],
1039 "emit" => '. div%XXM %binop',
1041 "units" => [ "SSE" ],
1048 "comment" => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
1049 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
1051 "units" => [ "SSE" ],
1056 "op_flags" => "L|X|Y",
1057 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
1058 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
1059 "outs" => [ "false", "true" ],
1061 "units" => [ "SSE" ],
1067 "comment" => "represents a SSE constant",
1068 "reg_req" => { "out" => [ "xmm" ] },
1069 "emit" => '. mov%XXM $%C, %D1',
1071 "units" => [ "SSE" ],
1078 "op_flags" => "L|F",
1079 "state" => "exc_pinned",
1080 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
1081 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
1082 "emit" => '. mov%XXM %AM, %D1',
1083 "outs" => [ "res", "M" ],
1085 "units" => [ "SSE" ],
1089 "op_flags" => "L|F",
1090 "state" => "exc_pinned",
1091 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
1092 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
1093 "emit" => '. mov%XXM %binop',
1095 "units" => [ "SSE" ],
1100 "op_flags" => "L|F",
1101 "state" => "exc_pinned",
1102 "comment" => "construct Store without index: Store(ptr, val, mem) = ST ptr,val",
1103 "reg_req" => { "in" => [ "gp", "xmm", "none" ] },
1104 "emit" => '. mov%XXM %S2, %AM',
1106 "units" => [ "SSE" ],
1111 "op_flags" => "L|F",
1112 "comment" => "construct: transfer a value from x87 FPU into a SSE register",
1113 "cmp_attr" => "return 1;",
1118 "op_flags" => "L|F",
1119 "comment" => "construct: transfer a value from SSE register to x87 FPU",
1120 "cmp_attr" => "return 1;",
1125 "op_flags" => "L|F",
1127 "state" => "exc_pinned",
1128 "comment" => "store ST0 onto stack",
1129 "reg_req" => { "in" => [ "gp", "gp", "none" ] },
1130 "emit" => '. fstp%XM %AM',
1132 "units" => [ "SSE" ],
1137 "op_flags" => "L|F",
1139 "state" => "exc_pinned",
1140 "comment" => "load ST0 from stack",
1141 "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "vf0", "none" ] },
1142 "emit" => '. fld%M %AM',
1143 "outs" => [ "res", "M" ],
1145 "units" => [ "SSE" ],
1151 "op_flags" => "F|H",
1152 "state" => "pinned",
1153 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
1154 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "edi", "esi", "ecx", "none" ] },
1155 "outs" => [ "DST", "SRC", "CNT", "M" ],
1156 "units" => [ "GP" ],
1160 "op_flags" => "F|H",
1161 "state" => "pinned",
1162 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
1163 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "edi", "esi", "none" ] },
1164 "outs" => [ "DST", "SRC", "M" ],
1165 "units" => [ "GP" ],
1171 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
1172 "comment" => "construct Conv Int -> Int",
1173 "units" => [ "GP" ],
1174 "mode" => "mode_Iu",
1178 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
1179 "comment" => "construct Conv Int -> Int",
1180 "units" => [ "GP" ],
1181 "mode" => "mode_Iu",
1185 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
1186 "comment" => "construct Conv Int -> Floating Point",
1188 "units" => [ "SSE" ],
1193 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
1194 "comment" => "construct Conv Floating Point -> Int",
1196 "units" => [ "SSE" ],
1197 "mode" => "mode_Iu",
1201 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
1202 "comment" => "construct Conv Floating Point -> Floating Point",
1204 "units" => [ "SSE" ],
1210 "comment" => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
1211 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "in_r4" ] },
1213 "units" => [ "GP" ],
1214 "mode" => "mode_Iu",
1219 "comment" => "check if Psi condition tree evaluates to true and move result accordingly",
1220 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r3" ] },
1222 "units" => [ "GP" ],
1223 "mode" => "mode_Iu",
1228 "comment" => "construct Conditional Move: SSE Compare + int CMov ",
1229 "reg_req" => { "in" => [ "xmm", "xmm", "gp", "gp" ], "out" => [ "in_r4" ] },
1231 "units" => [ "SSE" ],
1232 "mode" => "mode_Iu",
1237 "comment" => "construct Conditional Move: x87 Compare + int CMov",
1238 "reg_req" => { "in" => [ "vfp", "vfp", "gp", "gp" ], "out" => [ "in_r4" ] },
1240 "units" => [ "VFP" ],
1241 "mode" => "mode_Iu",
1246 "comment" => "construct Set: Set(sel) == sel ? 1 : 0",
1247 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax ebx ecx edx" ] },
1249 "units" => [ "GP" ],
1250 "mode" => "mode_Iu",
1255 "comment" => "check if Psi condition tree evaluates to true and set result accordingly",
1256 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax ebx ecx edx" ] },
1258 "units" => [ "GP" ],
1259 "mode" => "mode_Iu",
1264 "comment" => "construct Set: SSE Compare + int Set",
1265 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "eax ebx ecx edx" ] },
1267 "units" => [ "SSE" ],
1268 "mode" => "mode_Iu",
1273 "comment" => "construct Set: x87 Compare + int Set",
1274 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "eax ebx ecx edx" ] },
1276 "units" => [ "VFP" ],
1277 "mode" => "mode_Iu",
1282 "comment" => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
1283 "reg_req" => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] },
1285 "units" => [ "VFP" ],
1289 #----------------------------------------------------------#
1291 # (_) | | | | / _| | | | #
1292 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
1293 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
1294 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
1295 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
1297 # _ __ ___ __| | ___ ___ #
1298 # | '_ \ / _ \ / _` |/ _ \/ __| #
1299 # | | | | (_) | (_| | __/\__ \ #
1300 # |_| |_|\___/ \__,_|\___||___/ #
1301 #----------------------------------------------------------#
1305 "comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
1306 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1308 "units" => [ "VFP" ],
1314 "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1315 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1317 "units" => [ "VFP" ],
1323 "cmp_attr" => "return 1;",
1324 "comment" => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1330 "comment" => "virtual fp Sub: Sub(a, b) = a - b",
1331 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1333 "units" => [ "VFP" ],
1338 "cmp_attr" => "return 1;",
1339 "comment" => "lowered virtual fp Sub: Sub(a, b) = a - b",
1344 "comment" => "virtual fp Div: Div(a, b) = a / b",
1345 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1346 "outs" => [ "res", "M" ],
1348 "units" => [ "VFP" ],
1352 "cmp_attr" => "return 1;",
1353 "comment" => "lowered virtual fp Div: Div(a, b) = a / b",
1354 "outs" => [ "res", "M" ],
1359 "comment" => "virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1360 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1362 "units" => [ "VFP" ],
1367 "cmp_attr" => "return 1;",
1368 "comment" => "lowered virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1374 "comment" => "virtual fp Abs: Abs(a) = |a|",
1375 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1377 "units" => [ "VFP" ],
1383 "comment" => "virtual fp Chs: Chs(a) = -a",
1384 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1386 "units" => [ "VFP" ],
1392 "comment" => "virtual fp Sin: Sin(a) = sin(a)",
1393 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1395 "units" => [ "VFP" ],
1401 "comment" => "virtual fp Cos: Cos(a) = cos(a)",
1402 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1404 "units" => [ "VFP" ],
1410 "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
1411 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1413 "units" => [ "VFP" ],
1417 # virtual Load and Store
1420 "op_flags" => "L|F",
1421 "state" => "exc_pinned",
1422 "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
1423 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1424 "outs" => [ "res", "M" ],
1426 "units" => [ "VFP" ],
1430 "op_flags" => "L|F",
1431 "state" => "exc_pinned",
1432 "comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
1433 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1435 "units" => [ "VFP" ],
1442 "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1443 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1444 "outs" => [ "res", "M" ],
1446 "units" => [ "VFP" ],
1450 "cmp_attr" => "return 1;",
1451 "comment" => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1452 "outs" => [ "res", "M" ],
1457 "comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1458 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1460 "units" => [ "VFP" ],
1465 "cmp_attr" => "return 1;",
1466 "comment" => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1476 "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg",
1477 "reg_req" => { "out" => [ "vfp" ] },
1479 "units" => [ "VFP" ],
1485 "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg",
1486 "reg_req" => { "out" => [ "vfp" ] },
1488 "units" => [ "VFP" ],
1494 "comment" => "virtual fp Load pi: Ld pi -> reg",
1495 "reg_req" => { "out" => [ "vfp" ] },
1497 "units" => [ "VFP" ],
1503 "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg",
1504 "reg_req" => { "out" => [ "vfp" ] },
1506 "units" => [ "VFP" ],
1512 "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg",
1513 "reg_req" => { "out" => [ "vfp" ] },
1515 "units" => [ "VFP" ],
1521 "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg",
1522 "reg_req" => { "out" => [ "vfp" ] },
1524 "units" => [ "VFP" ],
1530 "comment" => "virtual fp Load ld e: Ld ld e -> reg",
1531 "reg_req" => { "out" => [ "vfp" ] },
1533 "units" => [ "VFP" ],
1540 # "init_attr" => " set_ia32_ls_mode(res, mode);",
1541 "comment" => "represents a virtual floating point constant",
1542 "reg_req" => { "out" => [ "vfp" ] },
1544 "units" => [ "VFP" ],
1551 "op_flags" => "L|X|Y",
1552 "comment" => "represents a virtual floating point compare",
1553 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] },
1554 "outs" => [ "false", "true", "temp_reg_eax" ],
1556 "units" => [ "VFP" ],
1559 #------------------------------------------------------------------------#
1560 # ___ _____ __ _ _ _ #
1561 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1562 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1563 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1564 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1565 #------------------------------------------------------------------------#
1567 # Note: gas is strangely buggy: fdivrp and fdivp as well as fsubrp and fsubp
1568 # are swapped, we work this around in the emitter...
1572 "rd_constructor" => "NONE",
1573 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1575 "emit" => '. fadd%XM %x87_binop',
1580 "rd_constructor" => "NONE",
1581 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1583 "emit" => '. faddp %x87_binop',
1588 "rd_constructor" => "NONE",
1589 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1591 "emit" => '. fmul%XM %x87_binop',
1596 "rd_constructor" => "NONE",
1597 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1599 "emit" => '. fmulp %x87_binop',,
1604 "rd_constructor" => "NONE",
1605 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1607 "emit" => '. fsub%XM %x87_binop',
1612 "rd_constructor" => "NONE",
1613 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1615 # see note about gas bugs
1616 "emit" => '. fsubrp %x87_binop',
1621 "rd_constructor" => "NONE",
1623 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1625 "emit" => '. fsubr%XM %x87_binop',
1630 "rd_constructor" => "NONE",
1632 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1634 # see note about gas bugs
1635 "emit" => '. fsubp %x87_binop',
1640 "rd_constructor" => "NONE",
1641 "comment" => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1643 "emit" => '. fprem1',
1646 # this node is just here, to keep the simulator running
1647 # we can omit this when a fprem simulation function exists
1650 "rd_constructor" => "NONE",
1651 "comment" => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1653 "emit" => '. fprem1',
1658 "rd_constructor" => "NONE",
1659 "comment" => "x87 fp Div: Div(a, b) = a / b",
1661 "emit" => '. fdiv%XM %x87_binop',
1666 "rd_constructor" => "NONE",
1667 "comment" => "x87 fp Div: Div(a, b) = a / b",
1669 # see note about gas bugs
1670 "emit" => '. fdivrp %x87_binop',
1675 "rd_constructor" => "NONE",
1676 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1678 "emit" => '. fdivr%XM %x87_binop',
1683 "rd_constructor" => "NONE",
1684 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1686 # see note about gas bugs
1687 "emit" => '. fdivp %x87_binop',
1692 "rd_constructor" => "NONE",
1693 "comment" => "x87 fp Abs: Abs(a) = |a|",
1700 "rd_constructor" => "NONE",
1701 "comment" => "x87 fp Chs: Chs(a) = -a",
1708 "rd_constructor" => "NONE",
1709 "comment" => "x87 fp Sin: Sin(a) = sin(a)",
1716 "rd_constructor" => "NONE",
1717 "comment" => "x87 fp Cos: Cos(a) = cos(a)",
1724 "rd_constructor" => "NONE",
1725 "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1727 "emit" => '. fsqrt $',
1730 # x87 Load and Store
1733 "rd_constructor" => "NONE",
1734 "op_flags" => "R|L|F",
1735 "state" => "exc_pinned",
1736 "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1738 "emit" => '. fld%XM %AM',
1742 "rd_constructor" => "NONE",
1743 "op_flags" => "R|L|F",
1744 "state" => "exc_pinned",
1745 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1747 "emit" => '. fst%XM %AM',
1752 "rd_constructor" => "NONE",
1753 "op_flags" => "R|L|F",
1754 "state" => "exc_pinned",
1755 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1757 "emit" => '. fstp%XM %AM',
1765 "rd_constructor" => "NONE",
1766 "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1768 "emit" => '. fild%XM %AM',
1773 "rd_constructor" => "NONE",
1774 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1776 "emit" => '. fist%M %AM',
1782 "rd_constructor" => "NONE",
1783 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1785 "emit" => '. fistp%M %AM',
1792 "op_flags" => "R|c",
1794 "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
1800 "op_flags" => "R|c",
1802 "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
1808 "op_flags" => "R|c",
1810 "comment" => "x87 fp Load pi: Ld pi -> reg",
1812 "emit" => '. fldpi',
1816 "op_flags" => "R|c",
1818 "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
1820 "emit" => '. fldln2',
1824 "op_flags" => "R|c",
1826 "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
1828 "emit" => '. fldlg2',
1832 "op_flags" => "R|c",
1834 "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
1836 "emit" => '. fldll2t',
1840 "op_flags" => "R|c",
1842 "comment" => "x87 fp Load ld e: Ld ld e -> reg",
1844 "emit" => '. fldl2e',
1848 # Note that it is NEVER allowed to do CSE on these nodes
1849 # Moreover, note the virtual register requierements!
1852 "op_flags" => "R|K",
1853 "comment" => "x87 stack exchange",
1855 "cmp_attr" => "return 1;",
1856 "emit" => '. fxch %X1',
1860 "op_flags" => "R|K",
1861 "comment" => "x87 stack push",
1863 "cmp_attr" => "return 1;",
1864 "emit" => '. fld %X1',
1869 "comment" => "x87 stack push",
1870 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1871 "cmp_attr" => "return 1;",
1872 "emit" => '. fld %X1',
1876 "op_flags" => "R|K",
1877 "comment" => "x87 stack pop",
1879 "cmp_attr" => "return 1;",
1880 "emit" => '. fstp %X1',
1886 "op_flags" => "L|X|Y",
1887 "comment" => "floating point compare",
1892 "op_flags" => "L|X|Y",
1893 "comment" => "floating point compare and pop",
1898 "op_flags" => "L|X|Y",
1899 "comment" => "floating point compare and pop twice",
1904 "op_flags" => "L|X|Y",
1905 "comment" => "floating point compare reverse",
1910 "op_flags" => "L|X|Y",
1911 "comment" => "floating point compare reverse and pop",
1916 "op_flags" => "L|X|Y",
1917 "comment" => "floating point compare reverse and pop twice",
1922 # -------------------------------------------------------------------------------- #
1923 # ____ ____ _____ _ _ #
1924 # / ___/ ___|| ____| __ _____ ___| |_ ___ _ __ _ __ ___ __| | ___ ___ #
1925 # \___ \___ \| _| \ \ / / _ \/ __| __/ _ \| '__| | '_ \ / _ \ / _` |/ _ \/ __| #
1926 # ___) |__) | |___ \ V / __/ (__| || (_) | | | | | | (_) | (_| | __/\__ \ #
1927 # |____/____/|_____| \_/ \___|\___|\__\___/|_| |_| |_|\___/ \__,_|\___||___/ #
1929 # -------------------------------------------------------------------------------- #
1932 # Spilling and reloading of SSE registers, hardcoded, not generated #
1935 "op_flags" => "L|F",
1936 "state" => "exc_pinned",
1937 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
1938 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
1939 "emit" => '. movdqu %D1, %AM',
1940 "outs" => [ "res", "M" ],
1941 "units" => [ "SSE" ],
1945 "op_flags" => "L|F",
1946 "state" => "exc_pinned",
1947 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
1948 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
1949 "emit" => '. movdqu %binop',
1950 "units" => [ "SSE" ],
1956 # Include the generated SIMD node specification written by the SIMD optimization
1957 $my_script_name = dirname($myname) . "/../ia32/ia32_simd_spec.pl";
1958 unless ($return = do $my_script_name) {
1959 warn "couldn't parse $my_script_name: $@" if $@;
1960 warn "couldn't do $my_script_name: $!" unless defined $return;
1961 warn "couldn't run $my_script_name" unless $return;