3 # This is the specification for the ia32 assembler Firm-operations
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
8 # this string marks the beginning of a comment in emit
9 $comment_string = "/*";
11 # the number of additional opcodes you want to register
12 $additional_opcodes = 0;
14 # The node description is done as a perl hash initializer with the
15 # following structure:
20 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
21 # "irn_flags" => "R|N|I"
22 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
23 # "state" => "floats|pinned|mem_pinned|exc_pinned",
25 # { "type" => "type 1", "name" => "name 1" },
26 # { "type" => "type 2", "name" => "name 2" },
29 # "comment" => "any comment for constructor",
30 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
31 # "cmp_attr" => "c source code for comparing node attributes",
32 # "emit" => "emit code with templates",
33 # "rd_constructor" => "c source code which constructs an ir_node"
36 # ... # (all nodes you need to describe)
38 # ); # close the %nodes initializer
40 # op_flags: flags for the operation, OPTIONAL (default is "N")
41 # the op_flags correspond to the firm irop_flags:
44 # C irop_flag_commutative
45 # X irop_flag_cfopcode
46 # I irop_flag_ip_cfopcode
49 # H irop_flag_highlevel
50 # c irop_flag_constlike
53 # irn_flags: special node flags, OPTIONAL (default is 0)
54 # following irn_flags are supported:
57 # I ignore for register allocation
59 # state: state of the operation, OPTIONAL (default is "floats")
61 # arity: arity of the operation, MUST NOT BE OMITTED
63 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
64 # are always the first 3 arguments and are always autmatically
66 # If this key is missing the following arguments will be created:
67 # for i = 1 .. arity: ir_node *op_i
70 # comment: OPTIONAL comment for the node constructor
72 # rd_constructor: for every operation there will be a
73 # new_rd_<arch>_<op-name> function with the arguments from above
74 # which creates the ir_node corresponding to the defined operation
75 # you can either put the complete source code of this function here
77 # This key is OPTIONAL. If omitted, the following constructor will
79 # if (!op_<arch>_<op-name>) assert(0);
83 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
86 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
90 # 1 - caller save (register must be saved by the caller of a function)
91 # 2 - callee save (register must be saved by the called function)
92 # 4 - ignore (do not assign this register)
93 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
96 { "name" => "eax", "type" => 1 },
97 { "name" => "edx", "type" => 1 },
98 { "name" => "ebx", "type" => 2 },
99 { "name" => "ecx", "type" => 1 },
100 { "name" => "esi", "type" => 2 },
101 { "name" => "edi", "type" => 2 },
102 { "name" => "ebp", "type" => 2 },
103 { "name" => "esp", "type" => 4 },
104 { "name" => "xxx", "type" => 6 }, # we need a dummy register for NoReg and Unknown nodes
105 { "mode" => "mode_P" }
108 { "name" => "xmm0", "type" => 1 },
109 { "name" => "xmm1", "type" => 1 },
110 { "name" => "xmm2", "type" => 1 },
111 { "name" => "xmm3", "type" => 1 },
112 { "name" => "xmm4", "type" => 1 },
113 { "name" => "xmm5", "type" => 1 },
114 { "name" => "xmm6", "type" => 1 },
115 { "name" => "xmm7", "type" => 1 },
116 { "name" => "xxxx", "type" => 6 }, # we need a dummy register for NoReg and Unknown nodes
117 { "mode" => "mode_D" }
121 #--------------------------------------------------#
124 # _ __ _____ __ _ _ __ ___ _ __ ___ #
125 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
126 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
127 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
130 #--------------------------------------------------#
134 #-----------------------------------------------------------------#
137 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
138 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
139 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
140 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
143 #-----------------------------------------------------------------#
145 # commutative operations
148 # All nodes supporting Addressmode have 5 INs:
149 # 1 - base r1 == NoReg in case of no AM or no base
150 # 2 - index r2 == NoReg in case of no AM or no index
151 # 3 - op1 r3 == always present
152 # 4 - op2 r4 == NoReg in case of immediate operation
153 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
157 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
158 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
159 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
160 "emit" => '. add %ia32_emit_binop /* Add(%A1, %A2) -> %D1 */'
161 # "params" => "int a_x, int a_y",
162 # "init" => " attr.x = x; attr.y = y;"
167 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
168 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
169 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
170 "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */'
173 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
175 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
176 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
177 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r3", "edx in_r4" ] },
178 "emit" => '. imul %ia32_emit_unop /* Mulh(%A1, %A2) -> %D1 */'
183 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
184 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
185 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
186 "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */'
191 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
192 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
193 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
194 "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */'
199 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
200 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
201 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
202 "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */'
207 "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
208 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
210 '2. cmp %S1, %S2 /* prepare Max (%S1 - %S2), (%A1, %A2) */
211 if (mode_is_signed(get_irn_mode(n))) {
212 4. cmovl %D1, %S2 /* %S1 is less %S2 */
215 4. cmovb %D1, %S2 /* %S1 is below %S2 */
222 "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
223 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
225 '2. cmp %S1, %S2 /* prepare Min (%S1 - %S2), (%A1, %A2) */
226 if (mode_is_signed(get_irn_mode(n))) {
227 2. cmovg %D1, %S2 /* %S1 is greater %S2 */
230 2. cmova %D1, %S2, %D1 /* %S1 is above %S2 */
237 "comment" => "construct Mux: Mux(sel, a, b) == sel ? a : b",
238 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r2" ] },
240 '. cmp %S1, 0 /* compare Sel for CMov (%A2, %A3) */
241 . cmovne %D1, %S3 /* sel == true -> return %S3 */
245 # not commutative operations
249 "comment" => "construct Sub: Sub(a, b) = a - b",
250 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
251 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
252 "emit" => '. sub %ia32_emit_binop /* Sub(%A1, %A2) -> %D1 */'
257 "state" => "exc_pinned",
258 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "eax in_r1", "edx in_r3" ] },
260 ' if (mode_is_signed(get_irn_mode(n))) {
261 4. idiv %S2 /* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
264 4. div %S2 /* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
271 "comment" => "construct Shl: Shl(a, b) = a << b",
272 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
273 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
274 "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */'
279 "comment" => "construct Shr: Shr(a, b) = a >> b",
280 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
281 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
282 "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */'
287 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
288 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
289 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
290 "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */'
295 "comment" => "construct RotR: RotR(a, b) = a ROTR b",
296 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
297 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
298 "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */'
303 "comment" => "construct RotL: RotL(a, b) = a ROTL b",
304 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
305 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
306 "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */'
313 "comment" => "construct Minus: Minus(a) = -a",
314 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
315 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
316 "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */'
321 "comment" => "construct Increment: Inc(a) = a++",
322 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
323 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
324 "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */'
329 "comment" => "construct Decrement: Dec(a) = a--",
330 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
331 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
332 "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */'
337 "comment" => "construct Not: Not(a) = !a",
338 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
339 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
340 "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */'
346 "op_flags" => "L|X|Y",
347 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
348 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
349 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
353 "op_flags" => "L|X|Y",
354 "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
355 "reg_req" => { "in" => [ "gp", "gp" ] },
356 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
360 "op_flags" => "L|X|Y",
361 "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
362 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
363 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
367 "op_flags" => "L|X|Y",
368 "comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
369 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
370 "reg_req" => { "in" => [ "gp", "gp" ] },
374 "op_flags" => "L|X|Y",
375 "comment" => "construct switch",
376 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
377 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
383 "comment" => "represents an integer constant",
384 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
385 "reg_req" => { "out" => [ "gp" ] },
387 ' if (get_ia32_Immop_tarval(n) == get_tarval_null(get_irn_mode(n))) {
388 4. sub %D1, %D1 /* optimized mov 0 to register */
391 if (get_ia32_sc(n)) {
392 6. mov %D1, OFFSET FLAT:%C /* Move address of SymConst into register */
395 6. mov %D1, %C /* Mov Const into register */
403 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
404 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
405 "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */'
413 "state" => "exc_pinned",
414 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
415 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
416 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
418 ' if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) {
419 4. mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
422 4. mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
429 "state" => "exc_pinned",
430 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
431 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
432 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
433 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */'
438 "state" => "exc_pinned",
439 "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
440 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
441 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
442 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */'
447 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
448 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
449 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
450 "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */'
453 #--------------------------------------------------------#
456 # | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
457 # | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
458 # | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
459 # |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
460 #--------------------------------------------------------#
462 # commutative operations
466 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
467 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
468 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
469 "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */'
474 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
475 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
476 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
477 "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */'
482 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
483 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
484 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
485 "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */'
490 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
491 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
492 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
493 "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */'
498 "comment" => "construct SSE And: And(a, b) = a AND b",
499 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
500 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
501 "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */'
506 "comment" => "construct SSE Or: Or(a, b) = a OR b",
507 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
508 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
509 "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */'
514 "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
515 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
516 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
517 "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */'
520 # not commutative operations
524 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
525 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
526 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
527 "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */'
532 "comment" => "construct SSE Div: Div(a, b) = a / b",
533 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
534 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3 !in_r4" ] },
535 "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */'
541 "op_flags" => "L|X|Y",
542 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
543 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
544 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "none", "none" ] },
550 "comment" => "represents a SSE constant",
551 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
552 "reg_req" => { "out" => [ "fp" ] },
553 "emit" => '. mov%M %D1, %C /* Load fConst into register */',
561 "state" => "exc_pinned",
562 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
563 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
564 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "fp" ] },
565 "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */'
570 "state" => "exc_pinned",
571 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
572 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
573 "reg_req" => { "in" => [ "gp", "gp", "fp", "none" ] },
574 "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */'
582 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
583 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "none" ] },
589 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
590 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
591 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "none" ] },
597 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "gp", "none" ] },
598 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
599 "comment" => "construct Conv Int -> Int"
603 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "fp", "none" ] },
604 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
605 "comment" => "construct Conv Int -> Floating Point"
609 "reg_req" => { "in" => [ "gp", "gp", "fp", "none" ], "out" => [ "gp", "none" ] },
610 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
611 "comment" => "construct Conv Floating Point -> Int"
615 "reg_req" => { "in" => [ "gp", "gp", "fp", "none" ], "out" => [ "fp", "none" ] },
616 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
617 "comment" => "construct Conv Floating Point -> Floating Point",