3 # This is the specification for the ia32 assembler Firm-operations
10 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
13 # The node description is done as a perl hash initializer with the
14 # following structure:
19 # op_flags => "N|L|C|X|I|F|Y|H|c|K",
20 # irn_flags => "R|N|I|S"
21 # arity => "0|1|2|3 ... |variable|dynamic|any",
22 # state => "floats|pinned|mem_pinned|exc_pinned",
24 # { type => "type 1", name => "name 1" },
25 # { type => "type 2", name => "name 2" },
28 # comment => "any comment for constructor",
29 # reg_req => { in => [ "reg_class|register" ], out => [ "reg_class|register|in_rX" ] },
30 # cmp_attr => "c source code for comparing node attributes",
31 # emit => "emit code with templates",
32 # attr => "attitional attribute arguments for constructor"
33 # init_attr => "emit attribute initialization template"
34 # rd_constructor => "c source code which constructs an ir_node"
35 # latency => "latency of this operation (can be float)"
38 # ... # (all nodes you need to describe)
40 # ); # close the %nodes initializer
42 # op_flags: flags for the operation, OPTIONAL (default is "N")
43 # the op_flags correspond to the firm irop_flags:
46 # C irop_flag_commutative
47 # X irop_flag_cfopcode
48 # I irop_flag_ip_cfopcode
51 # H irop_flag_highlevel
52 # c irop_flag_constlike
55 # irn_flags: special node flags, OPTIONAL (default is 0)
56 # following irn_flags are supported:
59 # I ignore for register allocation
60 # S modifies stack pointer
62 # state: state of the operation, OPTIONAL (default is "floats")
64 # arity: arity of the operation, MUST NOT BE OMITTED
66 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
67 # are always the first 3 arguments and are always autmatically
69 # If this key is missing the following arguments will be created:
70 # for i = 1 .. arity: ir_node *op_i
73 # outs: if a node defines more than one output, the names of the projections
74 # nodes having outs having automatically the mode mode_T
75 # One can also annotate some flags for each out, additional to irn_flags.
76 # They are separated from name with a colon ':', and concatenated by pipe '|'
77 # Only I and S are available at the moment (same meaning as in irn_flags).
78 # example: [ "frame:I", "stack:I|S", "M" ]
80 # comment: OPTIONAL comment for the node constructor
82 # rd_constructor: for every operation there will be a
83 # new_rd_<arch>_<op-name> function with the arguments from above
84 # which creates the ir_node corresponding to the defined operation
85 # you can either put the complete source code of this function here
87 # This key is OPTIONAL. If omitted, the following constructor will
89 # if (!op_<arch>_<op-name>) assert(0);
93 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
96 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
98 # latency: the latency of the operation, default is 1
102 # 0 - no special type
103 # 1 - caller save (register must be saved by the caller of a function)
104 # 2 - callee save (register must be saved by the called function)
105 # 4 - ignore (do not assign this register)
106 # 8 - emitter can choose an arbitrary register of this class
107 # 16 - the register is a virtual one
108 # 32 - register represents a state
109 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
112 { name => "eax", type => 1 },
113 { name => "edx", type => 1 },
114 { name => "ebx", type => 2 },
115 { name => "ecx", type => 1 },
116 { name => "esi", type => 2 },
117 { name => "edi", type => 2 },
118 { name => "ebp", type => 2 },
119 { name => "esp", type => 4 },
120 { name => "gp_NOREG", type => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
121 { name => "gp_UKNWN", type => 4 | 8 | 16 }, # we need a dummy register for Unknown nodes
122 { mode => "mode_Iu" }
125 { name => "xmm0", type => 1 },
126 { name => "xmm1", type => 1 },
127 { name => "xmm2", type => 1 },
128 { name => "xmm3", type => 1 },
129 { name => "xmm4", type => 1 },
130 { name => "xmm5", type => 1 },
131 { name => "xmm6", type => 1 },
132 { name => "xmm7", type => 1 },
133 { name => "xmm_NOREG", type => 4 | 16 }, # we need a dummy register for NoReg nodes
134 { name => "xmm_UKNWN", type => 4 | 8 | 16}, # we need a dummy register for Unknown nodes
138 { name => "vf0", type => 1 | 16 },
139 { name => "vf1", type => 1 | 16 },
140 { name => "vf2", type => 1 | 16 },
141 { name => "vf3", type => 1 | 16 },
142 { name => "vf4", type => 1 | 16 },
143 { name => "vf5", type => 1 | 16 },
144 { name => "vf6", type => 1 | 16 },
145 { name => "vf7", type => 1 | 16 },
146 { name => "vfp_NOREG", type => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
147 { name => "vfp_UKNWN", type => 4 | 8 | 16 }, # we need a dummy register for Unknown nodes
151 { name => "st0", realname => "st", type => 4 },
152 { name => "st1", realname => "st(1)", type => 4 },
153 { name => "st2", realname => "st(2)", type => 4 },
154 { name => "st3", realname => "st(3)", type => 4 },
155 { name => "st4", realname => "st(4)", type => 4 },
156 { name => "st5", realname => "st(5)", type => 4 },
157 { name => "st6", realname => "st(6)", type => 4 },
158 { name => "st7", realname => "st(7)", type => 4 },
161 fp_cw => [ # the floating point control word
162 { name => "fpcw", type => 4 | 32},
163 { mode => "mode_fpcw" }
166 { name => "eflags", type => 4 },
167 { mode => "mode_Iu" }
170 { name => "fpsw", type => 4 },
171 { mode => "mode_Hu" }
176 CF => { reg => "eflags", bit => 0 },
177 PF => { reg => "eflags", bit => 2 },
178 AF => { reg => "eflags", bit => 4 },
179 ZF => { reg => "eflags", bit => 6 },
180 SF => { reg => "eflags", bit => 7 },
181 TF => { reg => "eflags", bit => 8 },
182 IF => { reg => "eflags", bit => 9 },
183 DF => { reg => "eflags", bit => 10 },
184 OF => { reg => "eflags", bit => 11 },
185 IOPL0 => { reg => "eflags", bit => 12 },
186 IOPL1 => { reg => "eflags", bit => 13 },
187 NT => { reg => "eflags", bit => 14 },
188 RF => { reg => "eflags", bit => 16 },
189 VM => { reg => "eflags", bit => 17 },
190 AC => { reg => "eflags", bit => 18 },
191 VIF => { reg => "eflags", bit => 19 },
192 VIP => { reg => "eflags", bit => 20 },
193 ID => { reg => "eflags", bit => 21 },
195 FP_IE => { reg => "fpsw", bit => 0 },
196 FP_DE => { reg => "fpsw", bit => 1 },
197 FP_ZE => { reg => "fpsw", bit => 2 },
198 FP_OE => { reg => "fpsw", bit => 3 },
199 FP_UE => { reg => "fpsw", bit => 4 },
200 FP_PE => { reg => "fpsw", bit => 5 },
201 FP_SF => { reg => "fpsw", bit => 6 },
202 FP_ES => { reg => "fpsw", bit => 7 },
203 FP_C0 => { reg => "fpsw", bit => 8 },
204 FP_C1 => { reg => "fpsw", bit => 9 },
205 FP_C2 => { reg => "fpsw", bit => 10 },
206 FP_TOP0 => { reg => "fpsw", bit => 11 },
207 FP_TOP1 => { reg => "fpsw", bit => 12 },
208 FP_TOP2 => { reg => "fpsw", bit => 13 },
209 FP_C3 => { reg => "fpsw", bit => 14 },
210 FP_B => { reg => "fpsw", bit => 15 },
212 FP_IM => { reg => "fpcw", bit => 0 },
213 FP_DM => { reg => "fpcw", bit => 1 },
214 FP_ZM => { reg => "fpcw", bit => 2 },
215 FP_OM => { reg => "fpcw", bit => 3 },
216 FP_UM => { reg => "fpcw", bit => 4 },
217 FP_PM => { reg => "fpcw", bit => 5 },
218 FP_PC0 => { reg => "fpcw", bit => 8 },
219 FP_PC1 => { reg => "fpcw", bit => 9 },
220 FP_RC0 => { reg => "fpcw", bit => 10 },
221 FP_RC1 => { reg => "fpcw", bit => 11 },
222 FP_X => { reg => "fpcw", bit => 12 }
226 GP => [ 1, "GP_EAX", "GP_EBX", "GP_ECX", "GP_EDX", "GP_ESI", "GP_EDI", "GP_EBP" ],
227 SSE => [ 1, "SSE_XMM0", "SSE_XMM1", "SSE_XMM2", "SSE_XMM3", "SSE_XMM4", "SSE_XMM5", "SSE_XMM6", "SSE_XMM7" ],
228 VFP => [ 1, "VFP_VF0", "VFP_VF1", "VFP_VF2", "VFP_VF3", "VFP_VF4", "VFP_VF5", "VFP_VF6", "VFP_VF7" ],
229 BRANCH => [ 1, "BRANCH1", "BRANCH2" ],
234 bundels_per_cycle => 1
238 S0 => "${arch}_emit_source_register(env, node, 0);",
239 S1 => "${arch}_emit_source_register(env, node, 1);",
240 S2 => "${arch}_emit_source_register(env, node, 2);",
241 S3 => "${arch}_emit_source_register(env, node, 3);",
242 S4 => "${arch}_emit_source_register(env, node, 4);",
243 S5 => "${arch}_emit_source_register(env, node, 5);",
244 D0 => "${arch}_emit_dest_register(env, node, 0);",
245 D1 => "${arch}_emit_dest_register(env, node, 1);",
246 D2 => "${arch}_emit_dest_register(env, node, 2);",
247 D3 => "${arch}_emit_dest_register(env, node, 3);",
248 D4 => "${arch}_emit_dest_register(env, node, 4);",
249 D5 => "${arch}_emit_dest_register(env, node, 5);",
250 X0 => "${arch}_emit_x87_name(env, node, 0);",
251 X1 => "${arch}_emit_x87_name(env, node, 1);",
252 X2 => "${arch}_emit_x87_name(env, node, 2);",
253 C => "${arch}_emit_immediate(env, node);",
254 SE => "${arch}_emit_extend_suffix(env, get_ia32_ls_mode(node));",
255 ME => "if(get_mode_size_bits(get_ia32_ls_mode(node)) != 32)\n
256 ia32_emit_mode_suffix(env, get_ia32_ls_mode(node));",
257 M => "${arch}_emit_mode_suffix(env, get_ia32_ls_mode(node));",
258 XM => "${arch}_emit_x87_mode_suffix(env, node);",
259 XXM => "${arch}_emit_xmm_mode_suffix(env, node);",
260 XSD => "${arch}_emit_xmm_mode_suffix_s(env, node);",
261 AM => "${arch}_emit_am(env, node);",
262 unop => "${arch}_emit_unop(env, node);",
263 binop => "${arch}_emit_binop(env, node);",
264 x87_binop => "${arch}_emit_x87_binop(env, node);",
267 #--------------------------------------------------#
270 # _ __ _____ __ _ _ __ ___ _ __ ___ #
271 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
272 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
273 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
276 #--------------------------------------------------#
278 $default_cmp_attr = "return ia32_compare_attr(attr_a, attr_b);";
283 $mode_xmm = "mode_E";
284 $mode_gp = "mode_Iu";
285 $mode_fpcw = "mode_fpcw";
286 $status_flags = [ "CF", "PF", "AF", "ZF", "SF", "OF" ];
287 $fpcw_flags = [ "FP_IM", "FP_DM", "FP_ZM", "FP_OM", "FP_UM", "FP_PM",
288 "FP_PC0", "FP_PC1", "FP_RC0", "FP_RC1", "FP_X" ];
292 #-----------------------------------------------------------------#
295 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
296 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
297 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
298 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
301 #-----------------------------------------------------------------#
303 # commutative operations
306 # All nodes supporting Addressmode have 5 INs:
307 # 1 - base r1 == NoReg in case of no AM or no base
308 # 2 - index r2 == NoReg in case of no AM or no index
309 # 3 - op1 r3 == always present
310 # 4 - op2 r4 == NoReg in case of immediate operation
311 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
315 comment => "construct Add: Add(a, b) = Add(b, a) = a + b",
316 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
317 emit => '. addl %binop',
320 modified_flags => $status_flags
324 comment => "construct Add with Carry: Adc(a, b) = Add(b, a) = a + b + carry",
325 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
326 emit => '. adcl %binop',
329 modified_flags => $status_flags
334 comment => "construct 64Bit Add: Add(a_l, a_h, b_l, b_h) = a_l + b_l; a_h + b_h + carry",
336 reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
343 outs => [ "low_res", "high_res" ],
345 modified_flags => $status_flags
351 cmp_attr => "return 1;",
352 comment => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
358 cmp_attr => "return 1;",
359 comment => "construct lowered Add with Carry: Adc(a, b) = Adc(b, a) = a + b + carry",
364 # we should not rematrialize this node. It produces 2 results and has
365 # very strict constrains
366 comment => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
367 reg_req => { in => [ "gp", "gp", "eax", "gp", "none" ], out => [ "eax", "edx", "none" ] },
368 emit => '. mull %unop',
369 outs => [ "EAX", "EDX", "M" ],
372 modified_flags => $status_flags
376 # we should not rematrialize this node. It produces 2 results and has
377 # very strict constrains
379 cmp_attr => "return 1;",
380 comment => "construct lowered MulS: Mul(a, b) = Mul(b, a) = a * b",
381 outs => [ "EAX", "EDX", "M" ],
387 comment => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
388 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
389 emit => '. imull %binop',
393 modified_flags => $status_flags
398 comment => "construct Mul (1 operand format): Mul(a, b) = Mul(b, a) = a * b",
399 reg_req => { in => [ "gp", "gp", "eax", "gp", "none" ], out => [ "eax", "edx", "none" ] },
400 emit => '. imull %unop',
401 outs => [ "EAX", "EDX", "M" ],
404 modified_flags => $status_flags
409 cmp_attr => "return 1;",
410 comment => "construct lowered IMul: IMul(a, b) = IMul(b, a) = a * b",
416 comment => "construct And: And(a, b) = And(b, a) = a AND b",
417 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
418 emit => '. andl %binop',
421 modified_flags => $status_flags
426 comment => "construct Or: Or(a, b) = Or(b, a) = a OR b",
427 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
428 emit => '. orl %binop',
431 modified_flags => $status_flags
436 comment => "construct Xor: Xor(a, b) = Xor(b, a) = a EOR b",
437 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
438 emit => '. xorl %binop',
441 modified_flags => $status_flags
446 cmp_attr => "return 1;",
447 comment => "construct lowered Xor: Xor(a, b) = Xor(b, a) = a XOR b",
449 modified_flags => $status_flags
452 # not commutative operations
456 comment => "construct Sub: Sub(a, b) = a - b",
457 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
458 emit => '. subl %binop',
461 modified_flags => $status_flags
465 comment => "construct Sub with Carry: SubC(a, b) = a - b - carry",
466 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3 !in_r4" ] },
467 emit => '. sbbl %binop',
470 modified_flags => $status_flags
475 comment => "construct 64Bit Sub: Sub(a_l, a_h, b_l, b_h) = a_l - b_l; a_h - b_h - borrow",
477 reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
484 outs => [ "low_res", "high_res" ],
486 modified_flags => $status_flags
491 cmp_attr => "return 1;",
492 comment => "construct lowered Sub: Sub(a, b) = a - b",
497 cmp_attr => "return 1;",
498 comment => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
504 state => "exc_pinned",
505 reg_req => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ], out => [ "eax", "edx", "none" ] },
506 attr => "ia32_op_flavour_t dm_flav",
507 init_attr => "attr->data.op_flav = dm_flav;",
508 emit => ". idivl %unop",
509 outs => [ "div_res", "mod_res", "M" ],
512 modified_flags => $status_flags
517 state => "exc_pinned",
518 reg_req => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ], out => [ "eax", "edx", "none" ] },
519 attr => "ia32_op_flavour_t dm_flav",
520 init_attr => "attr->data.op_flav = dm_flav;",
521 emit => ". divl %unop",
522 outs => [ "div_res", "mod_res", "M" ],
525 modified_flags => $status_flags
530 comment => "construct Shl: Shl(a, b) = a << b",
531 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
532 emit => '. shll %binop',
535 modified_flags => $status_flags
539 cmp_attr => "return 1;",
540 comment => "construct lowered Shl: Shl(a, b) = a << b",
546 comment => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
547 # Out requirements is: different from all in
548 # This is because, out must be different from LowPart and ShiftCount.
549 # We could say "!ecx !in_r4" but it can occur, that all values live through
550 # this Shift and the only value dying is the ShiftCount. Then there would be a
551 # register missing, as result must not be ecx and all other registers are
552 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
553 # (and probably never will). So we create artificial interferences of the result
554 # with all inputs, so the spiller can always assure a free register.
555 reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
558 if (get_ia32_immop_type(node) == ia32_ImmNone) {
559 if (get_ia32_op_type(node) == ia32_AddrModeD) {
560 . shldl %%cl, %S3, %AM
562 . shldl %%cl, %S3, %S2
565 if (get_ia32_op_type(node) == ia32_AddrModeD) {
575 modified_flags => $status_flags
579 cmp_attr => "return 1;",
580 comment => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
586 comment => "construct Shr: Shr(a, b) = a >> b",
587 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
588 emit => '. shrl %binop',
591 modified_flags => $status_flags
595 cmp_attr => "return 1;",
596 comment => "construct lowered Shr: Shr(a, b) = a << b",
602 comment => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
603 # Out requirements is: different from all in
604 # This is because, out must be different from LowPart and ShiftCount.
605 # We could say "!ecx !in_r4" but it can occur, that all values live through
606 # this Shift and the only value dying is the ShiftCount. Then there would be a
607 # register missing, as result must not be ecx and all other registers are
608 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
609 # (and probably never will). So we create artificial interferences of the result
610 # with all inputs, so the spiller can always assure a free register.
611 reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
613 if (get_ia32_immop_type(node) == ia32_ImmNone) {
614 if (get_ia32_op_type(node) == ia32_AddrModeD) {
615 . shrdl %%cl, %S3, %AM
617 . shrdl %%cl, %S3, %S2
620 if (get_ia32_op_type(node) == ia32_AddrModeD) {
630 modified_flags => $status_flags
634 cmp_attr => "return 1;",
635 comment => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
641 comment => "construct Shrs: Shrs(a, b) = a >> b",
642 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
643 emit => '. sarl %binop',
646 modified_flags => $status_flags
650 cmp_attr => "return 1;",
651 comment => "construct lowered Sar: Sar(a, b) = a << b",
657 comment => "construct Ror: Ror(a, b) = a ROR b",
658 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
659 emit => '. rorl %binop',
662 modified_flags => $status_flags
667 comment => "construct Rol: Rol(a, b) = a ROL b",
668 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
669 emit => '. roll %binop',
672 modified_flags => $status_flags
679 comment => "construct Minus: Minus(a) = -a",
680 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
681 emit => '. negl %unop',
684 modified_flags => $status_flags
689 comment => "construct 64Bit Minus: Minus(a_l, a_h, 0) = 0 - a_l; 0 - a_h - borrow",
691 reg_req => { in => [ "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
698 outs => [ "low_res", "high_res" ],
700 modified_flags => $status_flags
705 cmp_attr => "return 1;",
706 comment => "construct lowered Minus: Minus(a) = -a",
712 comment => "construct Increment: Inc(a) = a++",
713 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
714 emit => '. incl %unop',
717 modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
722 comment => "construct Decrement: Dec(a) = a--",
723 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
724 emit => '. decl %unop',
727 modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
732 comment => "construct Not: Not(a) = !a",
733 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
734 emit => '. notl %unop',
745 comment => "construct conditional jump: CMP A, B && JMPxx LABEL",
746 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ] },
747 outs => [ "false", "true" ],
749 units => [ "BRANCH" ],
755 comment => "construct conditional jump: TEST A, B && JMPxx LABEL",
756 reg_req => { in => [ "gp", "gp" ] },
757 outs => [ "false", "true" ],
759 units => [ "BRANCH" ],
765 comment => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
766 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "none", "none" ] },
767 outs => [ "false", "true" ],
768 units => [ "BRANCH" ],
774 comment => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
775 reg_req => { in => [ "gp", "gp" ] },
776 units => [ "BRANCH" ],
782 comment => "construct switch",
783 reg_req => { in => [ "gp" ], out => [ "none" ] },
785 units => [ "BRANCH" ],
791 comment => "represents an integer constant",
792 reg_req => { out => [ "gp" ] },
801 comment => "unknown value",
802 reg_req => { out => [ "gp_UKNWN" ] },
812 comment => "unknown value",
813 reg_req => { out => [ "vfp_UKNWN" ] },
823 comment => "unknown value",
824 reg_req => { out => [ "xmm_UKNWN" ] },
834 comment => "noreg GP value",
835 reg_req => { out => [ "gp_NOREG" ] },
845 comment => "noreg VFP value",
846 reg_req => { out => [ "vfp_NOREG" ] },
856 comment => "noreg XMM value",
857 reg_req => { out => [ "xmm_NOREG" ] },
867 comment => "change floating point control word",
868 reg_req => { out => [ "fp_cw" ] },
872 modified_flags => $fpcw_flags
877 state => "exc_pinned",
878 comment => "load floating point control word FldCW(ptr, mem) = LD ptr -> reg",
879 reg_req => { in => [ "gp", "gp", "none" ], out => [ "fp_cw" ] },
881 emit => ". fldcw %AM",
884 modified_flags => $fpcw_flags
889 state => "exc_pinned",
890 comment => "store floating point control word: FstCW(ptr, mem) = ST ptr -> reg",
891 reg_req => { in => [ "gp", "gp", "fp_cw", "none" ], out => [ "none" ] },
893 emit => ". fnstcw %AM",
899 # we should not rematrialize this node. It produces 2 results and has
900 # very strict constrains
901 comment => "construct CDQ: sign extend EAX -> EDX:EAX",
902 reg_req => { in => [ "gp" ], out => [ "eax in_r1", "edx" ] },
904 outs => [ "EAX", "EDX" ],
912 state => "exc_pinned",
913 comment => "construct Load: Load(ptr, mem) = LD ptr -> reg",
914 reg_req => { in => [ "gp", "gp", "none" ], out => [ "gp", "none" ] },
916 emit => ". mov%SE%ME%.l %AM, %D0",
917 outs => [ "res", "M" ],
923 cmp_attr => "return 1;",
924 comment => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg",
925 outs => [ "res", "M" ],
931 cmp_attr => "return 1;",
932 state => "exc_pinned",
933 comment => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val",
940 state => "exc_pinned",
941 comment => "construct Store: Store(ptr, val, mem) = ST ptr,val",
942 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "none" ] },
943 emit => '. mov%M %binop',
951 state => "exc_pinned",
952 comment => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
953 reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => ["none" ] },
954 emit => '. mov%M %binop',
962 comment => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
963 reg_req => { in => [ "gp", "gp" ], out => [ "in_r1" ] },
964 emit => '. leal %AM, %D0',
968 modified_flags => [],
972 comment => "push on the stack",
973 reg_req => { in => [ "gp", "gp", "gp", "esp", "none" ], out => [ "esp", "none" ] },
974 emit => '. pushl %unop',
975 outs => [ "stack:I|S", "M" ],
978 modified_flags => [],
982 comment => "pop a gp register from the stack",
983 reg_req => { in => [ "gp", "gp", "esp", "none" ], out => [ "esp", "gp", "none" ] },
984 emit => '. popl %unop',
985 outs => [ "stack:I|S", "res", "M" ],
988 modified_flags => [],
992 comment => "create stack frame",
993 reg_req => { in => [ "esp" ], out => [ "ebp", "esp" ] },
995 outs => [ "frame:I", "stack:I|S", "M" ],
1001 comment => "destroy stack frame",
1002 reg_req => { in => [ "esp", "ebp" ], out => [ "ebp", "esp" ] },
1004 outs => [ "frame:I", "stack:I|S" ],
1011 comment => "allocate space on stack",
1012 reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "none" ] },
1013 emit => '. addl %binop',
1014 outs => [ "stack:S", "M" ],
1016 modified_flags => $status_flags
1021 comment => "free space on stack",
1022 reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "none" ] },
1023 emit => '. subl %binop',
1024 outs => [ "stack:S", "M" ],
1026 modified_flags => $status_flags
1031 comment => "get the TLS base address",
1032 reg_req => { out => [ "gp" ] },
1038 #-----------------------------------------------------------------------------#
1039 # _____ _____ ______ __ _ _ _ #
1040 # / ____/ ____| ____| / _| | | | | | #
1041 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1042 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1043 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1044 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1045 #-----------------------------------------------------------------------------#
1047 # commutative operations
1051 comment => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
1052 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1053 emit => '. add%XXM %binop',
1061 comment => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
1062 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1063 emit => '. mul%XXM %binop',
1071 comment => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
1072 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1073 emit => '. max%XXM %binop',
1081 comment => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
1082 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1083 emit => '. min%XXM %binop',
1091 comment => "construct SSE And: And(a, b) = a AND b",
1092 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1093 emit => '. andp%XSD %binop',
1101 comment => "construct SSE Or: Or(a, b) = a OR b",
1102 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1103 emit => '. orp%XSD %binop',
1110 comment => "construct SSE Xor: Xor(a, b) = a XOR b",
1111 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1112 emit => '. xorp%XSD %binop',
1118 # not commutative operations
1122 comment => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
1123 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] },
1124 emit => '. andnp%XSD %binop',
1132 comment => "construct SSE Sub: Sub(a, b) = a - b",
1133 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1134 emit => '. sub%XXM %binop',
1142 comment => "construct SSE Div: Div(a, b) = a / b",
1143 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] },
1144 outs => [ "res", "M" ],
1145 emit => '. div%XXM %binop',
1154 comment => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
1155 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] },
1163 op_flags => "L|X|Y",
1164 comment => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
1165 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "none", "none" ] },
1166 outs => [ "false", "true" ],
1174 comment => "represents a SSE constant",
1175 reg_req => { out => [ "xmm" ] },
1176 emit => '. mov%XXM %C, %D0',
1186 state => "exc_pinned",
1187 comment => "construct SSE Load: Load(ptr, mem) = LD ptr",
1188 reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none" ] },
1189 emit => '. mov%XXM %AM, %D0',
1190 outs => [ "res", "M" ],
1197 state => "exc_pinned",
1198 comment => "construct Store: Store(ptr, val, mem) = ST ptr,val",
1199 reg_req => { in => [ "gp", "gp", "xmm", "none" ] },
1200 emit => '. mov%XXM %binop',
1208 state => "exc_pinned",
1209 comment => "construct Store without index: Store(ptr, val, mem) = ST ptr,val",
1210 reg_req => { in => [ "gp", "xmm", "none" ] },
1211 emit => '. mov%XXM %S1, %AM',
1219 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm" ] },
1220 emit => '. cvtsi2ss %D0, %AM',
1228 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm" ] },
1229 emit => '. cvtsi2sd %unop',
1238 comment => "construct: transfer a value from x87 FPU into a SSE register",
1239 cmp_attr => "return 1;",
1245 comment => "construct: transfer a value from SSE register to x87 FPU",
1246 cmp_attr => "return 1;",
1253 state => "exc_pinned",
1254 comment => "store ST0 onto stack",
1255 reg_req => { in => [ "gp", "gp", "none" ] },
1256 emit => '. fstp%XM %AM',
1265 state => "exc_pinned",
1266 comment => "load ST0 from stack",
1267 reg_req => { in => [ "gp", "none" ], out => [ "vf0", "none" ] },
1268 emit => '. fld%M %AM',
1269 outs => [ "res", "M" ],
1279 comment => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
1280 reg_req => { in => [ "edi", "esi", "ecx", "none" ], out => [ "edi", "esi", "ecx", "none" ] },
1281 outs => [ "DST", "SRC", "CNT", "M" ],
1283 modified_flags => [ "DF" ]
1289 comment => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
1290 reg_req => { in => [ "edi", "esi", "none" ], out => [ "edi", "esi", "none" ] },
1291 outs => [ "DST", "SRC", "M" ],
1293 modified_flags => [ "DF" ]
1299 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3", "none" ] },
1300 comment => "construct Conv Int -> Int",
1303 modified_flags => $status_flags
1307 reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => [ "in_r3", "none" ] },
1308 comment => "construct Conv Int -> Int",
1311 modified_flags => $status_flags
1315 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm", "none" ] },
1316 comment => "construct Conv Int -> Floating Point",
1323 reg_req => { in => [ "gp", "gp", "xmm", "none" ], out => [ "gp", "none" ] },
1324 comment => "construct Conv Floating Point -> Int",
1331 reg_req => { in => [ "gp", "gp", "xmm", "none" ], out => [ "xmm", "none" ] },
1332 comment => "construct Conv Floating Point -> Floating Point",
1340 comment => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
1341 reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "in_r4" ] },
1349 comment => "check if Psi condition tree evaluates to true and move result accordingly",
1350 reg_req => { in => [ "gp", "gp", "gp" ], out => [ "in_r3" ] },
1358 comment => "construct Conditional Move: SSE Compare + int CMov ",
1359 reg_req => { in => [ "xmm", "xmm", "gp", "gp" ], out => [ "in_r4" ] },
1367 comment => "construct Conditional Move: x87 Compare + int CMov",
1368 reg_req => { in => [ "vfp", "vfp", "gp", "gp" ], out => [ "in_r4" ] },
1376 comment => "construct Set: Set(sel) == sel ? 1 : 0",
1377 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "eax ebx ecx edx" ] },
1385 comment => "check if Psi condition tree evaluates to true and set result accordingly",
1386 reg_req => { in => [ "gp" ], out => [ "eax ebx ecx edx" ] },
1394 comment => "construct Set: SSE Compare + int Set",
1395 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "eax ebx ecx edx" ] },
1403 comment => "construct Set: x87 Compare + int Set",
1404 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "eax ebx ecx edx" ] },
1412 comment => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
1413 reg_req => { in => [ "vfp", "vfp", "vfp", "vfp" ], out => [ "vfp" ] },
1419 #----------------------------------------------------------#
1421 # (_) | | | | / _| | | | #
1422 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
1423 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
1424 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
1425 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
1427 # _ __ ___ __| | ___ ___ #
1428 # | '_ \ / _ \ / _` |/ _ \/ __| #
1429 # | | | | (_) | (_| | __/\__ \ #
1430 # |_| |_|\___/ \__,_|\___||___/ #
1431 #----------------------------------------------------------#
1435 comment => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
1436 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1444 comment => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1445 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1453 cmp_attr => "return 1;",
1454 comment => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1460 comment => "virtual fp Sub: Sub(a, b) = a - b",
1461 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1468 cmp_attr => "return 1;",
1469 comment => "lowered virtual fp Sub: Sub(a, b) = a - b",
1474 comment => "virtual fp Div: Div(a, b) = a / b",
1475 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1476 outs => [ "res", "M" ],
1482 cmp_attr => "return 1;",
1483 comment => "lowered virtual fp Div: Div(a, b) = a / b",
1484 outs => [ "res", "M" ],
1489 comment => "virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1490 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1497 cmp_attr => "return 1;",
1498 comment => "lowered virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1504 comment => "virtual fp Abs: Abs(a) = |a|",
1505 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1513 comment => "virtual fp Chs: Chs(a) = -a",
1514 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1522 comment => "virtual fp Sin: Sin(a) = sin(a)",
1523 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1531 comment => "virtual fp Cos: Cos(a) = cos(a)",
1532 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1540 comment => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
1541 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1547 # virtual Load and Store
1551 state => "exc_pinned",
1552 comment => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
1553 reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] },
1554 outs => [ "res", "M" ],
1561 state => "exc_pinned",
1562 comment => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
1563 reg_req => { in => [ "gp", "gp", "vfp", "none" ] },
1572 comment => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1573 reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] },
1574 outs => [ "res", "M" ],
1580 cmp_attr => "return 1;",
1581 comment => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1582 outs => [ "res", "M" ],
1587 comment => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1588 reg_req => { in => [ "gp", "gp", "vfp", "fpcw", "none" ] },
1595 cmp_attr => "return 1;",
1596 comment => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1606 comment => "virtual fp Load 0.0: Ld 0.0 -> reg",
1607 reg_req => { out => [ "vfp" ] },
1615 comment => "virtual fp Load 1.0: Ld 1.0 -> reg",
1616 reg_req => { out => [ "vfp" ] },
1624 comment => "virtual fp Load pi: Ld pi -> reg",
1625 reg_req => { out => [ "vfp" ] },
1633 comment => "virtual fp Load ln 2: Ld ln 2 -> reg",
1634 reg_req => { out => [ "vfp" ] },
1642 comment => "virtual fp Load lg 2: Ld lg 2 -> reg",
1643 reg_req => { out => [ "vfp" ] },
1651 comment => "virtual fp Load ld 10: Ld ld 10 -> reg",
1652 reg_req => { out => [ "vfp" ] },
1660 comment => "virtual fp Load ld e: Ld ld e -> reg",
1661 reg_req => { out => [ "vfp" ] },
1670 # init_attr => " set_ia32_ls_mode(res, mode);",
1671 comment => "represents a virtual floating point constant",
1672 reg_req => { out => [ "vfp" ] },
1682 op_flags => "L|X|Y",
1683 comment => "represents a virtual floating point compare",
1684 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "none", "none", "eax" ] },
1685 outs => [ "false", "true", "temp_reg_eax" ],
1690 #------------------------------------------------------------------------#
1691 # ___ _____ __ _ _ _ #
1692 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1693 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1694 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1695 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1696 #------------------------------------------------------------------------#
1698 # Note: gas is strangely buggy: fdivrp and fdivp as well as fsubrp and fsubp
1699 # are swapped, we work this around in the emitter...
1703 rd_constructor => "NONE",
1704 comment => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1706 emit => '. fadd%XM %x87_binop',
1711 rd_constructor => "NONE",
1712 comment => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1714 emit => '. faddp %x87_binop',
1719 rd_constructor => "NONE",
1720 comment => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1722 emit => '. fmul%XM %x87_binop',
1727 rd_constructor => "NONE",
1728 comment => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1730 emit => '. fmulp %x87_binop',,
1735 rd_constructor => "NONE",
1736 comment => "x87 fp Sub: Sub(a, b) = a - b",
1738 emit => '. fsub%XM %x87_binop',
1743 rd_constructor => "NONE",
1744 comment => "x87 fp Sub: Sub(a, b) = a - b",
1746 # see note about gas bugs
1747 emit => '. fsubrp %x87_binop',
1752 rd_constructor => "NONE",
1754 comment => "x87 fp SubR: SubR(a, b) = b - a",
1756 emit => '. fsubr%XM %x87_binop',
1761 rd_constructor => "NONE",
1763 comment => "x87 fp SubR: SubR(a, b) = b - a",
1765 # see note about gas bugs
1766 emit => '. fsubp %x87_binop',
1771 rd_constructor => "NONE",
1772 comment => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1777 # this node is just here, to keep the simulator running
1778 # we can omit this when a fprem simulation function exists
1781 rd_constructor => "NONE",
1782 comment => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1789 rd_constructor => "NONE",
1790 comment => "x87 fp Div: Div(a, b) = a / b",
1792 emit => '. fdiv%XM %x87_binop',
1797 rd_constructor => "NONE",
1798 comment => "x87 fp Div: Div(a, b) = a / b",
1800 # see note about gas bugs
1801 emit => '. fdivrp %x87_binop',
1806 rd_constructor => "NONE",
1807 comment => "x87 fp DivR: DivR(a, b) = b / a",
1809 emit => '. fdivr%XM %x87_binop',
1814 rd_constructor => "NONE",
1815 comment => "x87 fp DivR: DivR(a, b) = b / a",
1817 # see note about gas bugs
1818 emit => '. fdivp %x87_binop',
1823 rd_constructor => "NONE",
1824 comment => "x87 fp Abs: Abs(a) = |a|",
1831 rd_constructor => "NONE",
1832 comment => "x87 fp Chs: Chs(a) = -a",
1839 rd_constructor => "NONE",
1840 comment => "x87 fp Sin: Sin(a) = sin(a)",
1847 rd_constructor => "NONE",
1848 comment => "x87 fp Cos: Cos(a) = cos(a)",
1855 rd_constructor => "NONE",
1856 comment => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1858 emit => '. fsqrt $',
1861 # x87 Load and Store
1864 rd_constructor => "NONE",
1865 op_flags => "R|L|F",
1866 state => "exc_pinned",
1867 comment => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1869 emit => '. fld%XM %AM',
1873 rd_constructor => "NONE",
1874 op_flags => "R|L|F",
1875 state => "exc_pinned",
1876 comment => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1878 emit => '. fst%XM %AM',
1883 rd_constructor => "NONE",
1884 op_flags => "R|L|F",
1885 state => "exc_pinned",
1886 comment => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1888 emit => '. fstp%XM %AM',
1896 rd_constructor => "NONE",
1897 comment => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1899 emit => '. fild%XM %AM',
1904 rd_constructor => "NONE",
1905 comment => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1907 emit => '. fist%M %AM',
1913 rd_constructor => "NONE",
1914 comment => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1916 emit => '. fistp%M %AM',
1925 comment => "x87 fp Load 0.0: Ld 0.0 -> reg",
1933 comment => "x87 fp Load 1.0: Ld 1.0 -> reg",
1941 comment => "x87 fp Load pi: Ld pi -> reg",
1949 comment => "x87 fp Load ln 2: Ld ln 2 -> reg",
1957 comment => "x87 fp Load lg 2: Ld lg 2 -> reg",
1965 comment => "x87 fp Load ld 10: Ld ld 10 -> reg",
1967 emit => '. fldll2t',
1973 comment => "x87 fp Load ld e: Ld ld e -> reg",
1979 # Note that it is NEVER allowed to do CSE on these nodes
1980 # Moreover, note the virtual register requierements!
1984 comment => "x87 stack exchange",
1986 cmp_attr => "return 1;",
1987 emit => '. fxch %X0',
1992 comment => "x87 stack push",
1994 cmp_attr => "return 1;",
1995 emit => '. fld %X0',
2000 comment => "x87 stack push",
2001 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
2002 cmp_attr => "return 1;",
2003 emit => '. fld %X0',
2008 comment => "x87 stack pop",
2010 cmp_attr => "return 1;",
2011 emit => '. fstp %X0',
2017 op_flags => "L|X|Y",
2018 comment => "floating point compare",
2023 op_flags => "L|X|Y",
2024 comment => "floating point compare and pop",
2029 op_flags => "L|X|Y",
2030 comment => "floating point compare and pop twice",
2035 op_flags => "L|X|Y",
2036 comment => "floating point compare reverse",
2041 op_flags => "L|X|Y",
2042 comment => "floating point compare reverse and pop",
2047 op_flags => "L|X|Y",
2048 comment => "floating point compare reverse and pop twice",
2053 # -------------------------------------------------------------------------------- #
2054 # ____ ____ _____ _ _ #
2055 # / ___/ ___|| ____| __ _____ ___| |_ ___ _ __ _ __ ___ __| | ___ ___ #
2056 # \___ \___ \| _| \ \ / / _ \/ __| __/ _ \| '__| | '_ \ / _ \ / _` |/ _ \/ __| #
2057 # ___) |__) | |___ \ V / __/ (__| || (_) | | | | | | (_) | (_| | __/\__ \ #
2058 # |____/____/|_____| \_/ \___|\___|\__\___/|_| |_| |_|\___/ \__,_|\___||___/ #
2060 # -------------------------------------------------------------------------------- #
2063 # Spilling and reloading of SSE registers, hardcoded, not generated #
2067 state => "exc_pinned",
2068 comment => "construct SSE Load: Load(ptr, mem) = LD ptr",
2069 reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none" ] },
2070 emit => '. movdqu %D0, %AM',
2071 outs => [ "res", "M" ],
2077 state => "exc_pinned",
2078 comment => "construct Store: Store(ptr, val, mem) = ST ptr,val",
2079 reg_req => { in => [ "gp", "gp", "xmm", "none" ] },
2080 emit => '. movdqu %binop',
2087 # Include the generated SIMD node specification written by the SIMD optimization
2088 $my_script_name = dirname($myname) . "/../ia32/ia32_simd_spec.pl";
2089 unless ($return = do $my_script_name) {
2090 warn "couldn't parse $my_script_name: $@" if $@;
2091 warn "couldn't do $my_script_name: $!" unless defined $return;
2092 warn "couldn't run $my_script_name" unless $return;