3 # This is the specification for the ia32 assembler Firm-operations
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
8 # this string marks the beginning of a comment in emit
9 $comment_string = "/*";
11 # the number of additional opcodes you want to register
12 #$additional_opcodes = 0;
14 # The node description is done as a perl hash initializer with the
15 # following structure:
20 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
21 # "irn_flags" => "R|N|I"
22 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
23 # "state" => "floats|pinned|mem_pinned|exc_pinned",
25 # { "type" => "type 1", "name" => "name 1" },
26 # { "type" => "type 2", "name" => "name 2" },
29 # "comment" => "any comment for constructor",
30 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
31 # "cmp_attr" => "c source code for comparing node attributes",
32 # "emit" => "emit code with templates",
33 # "attr" => "attitional attribute arguments for constructor"
34 # "init_attr" => "emit attribute initialization template"
35 # "rd_constructor" => "c source code which constructs an ir_node"
38 # ... # (all nodes you need to describe)
40 # ); # close the %nodes initializer
42 # op_flags: flags for the operation, OPTIONAL (default is "N")
43 # the op_flags correspond to the firm irop_flags:
46 # C irop_flag_commutative
47 # X irop_flag_cfopcode
48 # I irop_flag_ip_cfopcode
51 # H irop_flag_highlevel
52 # c irop_flag_constlike
55 # irn_flags: special node flags, OPTIONAL (default is 0)
56 # following irn_flags are supported:
59 # I ignore for register allocation
61 # state: state of the operation, OPTIONAL (default is "floats")
63 # arity: arity of the operation, MUST NOT BE OMITTED
65 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
66 # are always the first 3 arguments and are always autmatically
68 # If this key is missing the following arguments will be created:
69 # for i = 1 .. arity: ir_node *op_i
72 # comment: OPTIONAL comment for the node constructor
74 # rd_constructor: for every operation there will be a
75 # new_rd_<arch>_<op-name> function with the arguments from above
76 # which creates the ir_node corresponding to the defined operation
77 # you can either put the complete source code of this function here
79 # This key is OPTIONAL. If omitted, the following constructor will
81 # if (!op_<arch>_<op-name>) assert(0);
85 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
88 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
92 # 1 - caller save (register must be saved by the caller of a function)
93 # 2 - callee save (register must be saved by the called function)
94 # 4 - ignore (do not assign this register)
95 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
98 { "name" => "eax", "type" => 1 },
99 { "name" => "edx", "type" => 1 },
100 { "name" => "ebx", "type" => 2 },
101 { "name" => "ecx", "type" => 1 },
102 { "name" => "esi", "type" => 2 },
103 { "name" => "edi", "type" => 2 },
104 { "name" => "ebp", "type" => 2 },
105 { "name" => "esp", "type" => 4 },
106 { "name" => "gp_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
107 { "name" => "gp_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
108 { "mode" => "mode_P" }
111 { "name" => "xmm0", "type" => 1 },
112 { "name" => "xmm1", "type" => 1 },
113 { "name" => "xmm2", "type" => 1 },
114 { "name" => "xmm3", "type" => 1 },
115 { "name" => "xmm4", "type" => 1 },
116 { "name" => "xmm5", "type" => 1 },
117 { "name" => "xmm6", "type" => 1 },
118 { "name" => "xmm7", "type" => 1 },
119 { "name" => "xmm_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
120 { "name" => "xmm_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
121 { "mode" => "mode_D" }
124 { "name" => "vf0", "type" => 1 },
125 { "name" => "vf1", "type" => 1 },
126 { "name" => "vf2", "type" => 1 },
127 { "name" => "vf3", "type" => 1 },
128 { "name" => "vf4", "type" => 1 },
129 { "name" => "vf5", "type" => 1 },
130 { "name" => "vf6", "type" => 1 },
131 { "name" => "vf7", "type" => 1 },
132 { "name" => "vfp_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
133 { "name" => "vfp_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
134 { "mode" => "mode_E" }
137 { "name" => "st0", "type" => 1 },
138 { "name" => "st1", "type" => 1 },
139 { "name" => "st2", "type" => 1 },
140 { "name" => "st3", "type" => 1 },
141 { "name" => "st4", "type" => 1 },
142 { "name" => "st5", "type" => 1 },
143 { "name" => "st6", "type" => 1 },
144 { "name" => "st7", "type" => 1 },
145 { "name" => "st_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
146 { "name" => "st_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
147 { "mode" => "mode_E" }
151 #--------------------------------------------------#
154 # _ __ _____ __ _ _ __ ___ _ __ ___ #
155 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
156 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
157 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
160 #--------------------------------------------------#
164 #-----------------------------------------------------------------#
167 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
168 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
169 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
170 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
173 #-----------------------------------------------------------------#
175 # commutative operations
178 # All nodes supporting Addressmode have 5 INs:
179 # 1 - base r1 == NoReg in case of no AM or no base
180 # 2 - index r2 == NoReg in case of no AM or no index
181 # 3 - op1 r3 == always present
182 # 4 - op2 r4 == NoReg in case of immediate operation
183 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
187 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
188 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
189 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
190 "emit" => '. add %ia32_emit_binop /* Add(%A1, %A2) -> %D1 */',
195 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
196 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
197 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
198 "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */'
201 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
203 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
204 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
205 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r3", "edx in_r4" ] },
206 "emit" => '. imul %ia32_emit_binop /* Mulh(%A1, %A2) -> %D1 */'
211 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
212 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
213 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
214 "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */'
219 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
220 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
221 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
222 "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */'
227 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
228 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
229 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
230 "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */'
235 "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
236 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
238 '2. cmp %S1, %S2 /* prepare Max (%S1 - %S2), (%A1, %A2) */
239 if (mode_is_signed(get_irn_mode(n))) {
240 4. cmovl %D1, %S2 /* %S1 is less %S2 */
243 4. cmovb %D1, %S2 /* %S1 is below %S2 */
250 "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
251 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
253 '2. cmp %S1, %S2 /* prepare Min (%S1 - %S2), (%A1, %A2) */
254 if (mode_is_signed(get_irn_mode(n))) {
255 2. cmovg %D1, %S2 /* %S1 is greater %S2 */
258 2. cmova %D1, %S2, %D1 /* %S1 is above %S2 */
265 "comment" => "construct Mux: Mux(sel, a, b) == sel ? a : b",
266 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r2" ] },
268 '. cmp %S1, 0 /* compare Sel for CMov (%A2, %A3) */
269 . cmovne %D1, %S3 /* sel == true -> return %S3 */
273 # not commutative operations
277 "comment" => "construct Sub: Sub(a, b) = a - b",
278 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
279 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
280 "emit" => '. sub %ia32_emit_binop /* Sub(%A1, %A2) -> %D1 */'
285 "state" => "exc_pinned",
286 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "eax in_r1", "edx in_r3" ] },
287 "attr" => "ia32_op_flavour_t dm_flav",
288 "init_attr" => " attr->data.op_flav = dm_flav;",
289 "cmp_attr" => " return attr_a->data.op_flav != attr_b->data.op_flav;\n",
291 ' if (mode_is_signed(get_irn_mode(n))) {
292 4. idiv %S2 /* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
295 4. div %S2 /* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
302 "comment" => "construct Shl: Shl(a, b) = a << b",
303 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
304 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
305 "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */'
310 "comment" => "construct Shr: Shr(a, b) = a >> b",
311 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
312 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
313 "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */'
318 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
319 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
320 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
321 "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */'
326 "comment" => "construct RotR: RotR(a, b) = a ROTR b",
327 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
328 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
329 "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */'
334 "comment" => "construct RotL: RotL(a, b) = a ROTL b",
335 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
336 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
337 "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */'
344 "comment" => "construct Minus: Minus(a) = -a",
345 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
346 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
347 "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */'
352 "comment" => "construct Increment: Inc(a) = a++",
353 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
354 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
355 "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */'
360 "comment" => "construct Decrement: Dec(a) = a--",
361 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
362 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
363 "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */'
368 "comment" => "construct Not: Not(a) = !a",
369 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
370 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
371 "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */'
377 "op_flags" => "L|X|Y",
378 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
379 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
380 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
384 "op_flags" => "L|X|Y",
385 "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
386 "reg_req" => { "in" => [ "gp", "gp" ] },
387 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
391 "op_flags" => "L|X|Y",
392 "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
393 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
394 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
398 "op_flags" => "L|X|Y",
399 "comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
400 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
401 "reg_req" => { "in" => [ "gp", "gp" ] },
405 "op_flags" => "L|X|Y",
406 "comment" => "construct switch",
407 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
408 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
414 "comment" => "represents an integer constant",
415 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
416 "reg_req" => { "out" => [ "gp" ] },
418 ' if (get_ia32_Immop_tarval(n) == get_tarval_null(get_irn_mode(n))) {
419 4. sub %D1, %D1 /* optimized mov 0 to register */
422 if (get_ia32_op_type(n) == ia32_SymConst) {
423 6. mov %D1, OFFSET FLAT:%C /* Move address of SymConst into register */
426 6. mov %D1, %C /* Mov Const into register */
434 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
435 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
436 "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */'
444 "state" => "exc_pinned",
445 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
446 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
447 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
449 ' if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) {
450 4. mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
453 4. mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
460 "state" => "exc_pinned",
461 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
462 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
463 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
464 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */'
469 "state" => "exc_pinned",
470 "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
471 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
472 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
473 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */'
478 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
479 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
480 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
481 "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */'
485 "comment" => "push a gp register on the stack",
486 "reg_req" => { "in" => [ "esp", "gp", "none" ], "out" => [ "gp" ] },
487 "emit" => '. push %S2 /* Push(%A2) */'
491 "comment" => "pop a gp register from the stack",
492 "reg_req" => { "in" => [ "esp", "none" ], "out" => [ "gp", "esp" ] },
493 "emit" => '. pop %D1 /* Pop -> %D1 */'
497 "comment" => "create stack frame",
498 "reg_req" => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] },
499 "emit" => '. enter /* Enter */'
503 "comment" => "destroy stack frame",
504 "reg_req" => { "in" => [ "esp", "ebp" ], "out" => [ "esp" ] },
505 "emit" => '. leave /* Enter */'
508 #-----------------------------------------------------------------------------#
509 # _____ _____ ______ __ _ _ _ #
510 # / ____/ ____| ____| / _| | | | | | #
511 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
512 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
513 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
514 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
515 #-----------------------------------------------------------------------------#
517 # commutative operations
521 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
522 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
523 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
524 "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */'
529 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
530 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
531 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
532 "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */'
537 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
538 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
539 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
540 "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */'
545 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
546 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
547 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
548 "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */'
553 "comment" => "construct SSE And: And(a, b) = a AND b",
554 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
555 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
556 "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */'
561 "comment" => "construct SSE Or: Or(a, b) = a OR b",
562 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
563 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
564 "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */'
569 "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
570 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
571 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
572 "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */'
575 # not commutative operations
579 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
580 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
581 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
582 "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */'
587 "comment" => "construct SSE Div: Div(a, b) = a / b",
588 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
589 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
590 "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */'
596 "op_flags" => "L|X|Y",
597 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
598 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
599 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
605 "comment" => "represents a SSE constant",
606 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
607 "reg_req" => { "out" => [ "xmm" ] },
608 "emit" => '. mov%M %D1, %C /* Load fConst into register */',
616 "state" => "exc_pinned",
617 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
618 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
619 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm" ] },
620 "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */'
625 "state" => "exc_pinned",
626 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
627 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
628 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
629 "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */'
637 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
638 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "none" ] },
644 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
645 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
646 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "none" ] },
652 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
653 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
654 "comment" => "construct Conv Int -> Int"
658 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
659 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
660 "comment" => "construct Conv Int -> Int"
664 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
665 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
666 "comment" => "construct Conv Int -> Floating Point"
670 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
671 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
672 "comment" => "construct Conv Floating Point -> Int"
676 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
677 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
678 "comment" => "construct Conv Floating Point -> Floating Point",
681 #----------------------------------------------------------#
683 # (_) | | | | / _| | | | #
684 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
685 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
686 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
687 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
689 # _ __ ___ __| | ___ ___ #
690 # | '_ \ / _ \ / _` |/ _ \/ __| #
691 # | | | | (_) | (_| | __/\__ \ #
692 # |_| |_|\___/ \__,_|\___||___/ #
693 #----------------------------------------------------------#
697 "comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
698 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
699 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
704 "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a + b",
705 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
706 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
711 "comment" => "virtual fp Sub: Sub(a, b) = a - b",
712 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
713 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
717 "comment" => "virtual fp Div: Div(a, b) = a / b",
718 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
719 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
724 "comment" => "virtual fp Abs: Abs(a) = |a|",
725 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
730 "comment" => "virtual fp Chs: Chs(a) = -a",
731 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
736 "comment" => "virtual fp Sin: Sin(a) = sin(a)",
737 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
742 "comment" => "virtual fp Cos: Cos(a) = cos(a)",
743 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
748 "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
749 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
752 # virtual Load and Store
757 "state" => "exc_pinned",
758 "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
759 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
760 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp" ] },
765 "state" => "exc_pinned",
766 "comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
767 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
768 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
775 "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
776 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
777 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp" ] },
781 "comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
782 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
783 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
790 "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg",
791 "reg_req" => { "out" => [ "vfp" ] },
796 "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg",
797 "reg_req" => { "out" => [ "vfp" ] },
802 "comment" => "virtual fp Load pi: Ld pi -> reg",
803 "reg_req" => { "out" => [ "vfp" ] },
808 "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg",
809 "reg_req" => { "out" => [ "vfp" ] },
814 "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg",
815 "reg_req" => { "out" => [ "vfp" ] },
820 "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg",
821 "reg_req" => { "out" => [ "vfp" ] },
826 "comment" => "virtual fp Load ld e: Ld ld e -> reg",
827 "reg_req" => { "out" => [ "vfp" ] },
833 "comment" => "represents a virtual floating point constant",
834 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
835 "reg_req" => { "out" => [ "vfp" ] },
838 #------------------------------------------------------------------------#
839 # ___ _____ __ _ _ _ #
840 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
841 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
842 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
843 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
844 #------------------------------------------------------------------------#
848 "rd_constructor" => "NONE",
849 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
851 "emit" => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */'
856 "rd_constructor" => "NONE",
857 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
859 "emit" => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */'
864 "rd_constructor" => "NONE",
865 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
867 "emit" => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */'
872 "rd_constructor" => "NONE",
873 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
875 "emit" => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */'
880 "rd_constructor" => "NONE",
881 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
883 "emit" => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */'
888 "rd_constructor" => "NONE",
889 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
891 "emit" => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */'
896 "rd_constructor" => "NONE",
898 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
900 "emit" => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */'
905 "rd_constructor" => "NONE",
907 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
909 "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */'
914 "rd_constructor" => "NONE",
915 "comment" => "x87 fp Div: Div(a, b) = a / b",
917 "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */'
922 "rd_constructor" => "NONE",
923 "comment" => "x87 fp Div: Div(a, b) = a / b",
925 "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */'
930 "rd_constructor" => "NONE",
931 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
933 "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */'
938 "rd_constructor" => "NONE",
939 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
941 "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */'
946 "rd_constructor" => "NONE",
947 "comment" => "x87 fp Abs: Abs(a) = |a|",
949 "emit" => '. fabs /* x87 fabs(%S1) -> %D1 */'
954 "rd_constructor" => "NONE",
955 "comment" => "x87 fp Chs: Chs(a) = -a",
957 "emit" => '. fchs /* x87 fchs(%S1) -> %D1 */'
962 "rd_constructor" => "NONE",
963 "comment" => "x87 fp Sin: Sin(a) = sin(a)",
965 "emit" => '. fsin /* x87 sin(%S1) -> %D1 */'
970 "rd_constructor" => "NONE",
971 "comment" => "x87 fp Cos: Cos(a) = cos(a)",
973 "emit" => '. fcos /* x87 cos(%S1) -> %D1 */'
978 "rd_constructor" => "NONE",
979 "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
981 "emit" => '. fsqrt $ /* x87 sqrt(%S1) -> %D1 */'
987 "rd_constructor" => "NONE",
988 "op_flags" => "R|L|F",
989 "state" => "exc_pinned",
990 "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
992 "emit" => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */'
996 "rd_constructor" => "NONE",
997 "op_flags" => "R|L|F",
998 "state" => "exc_pinned",
999 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1001 "emit" => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */'
1005 "rd_constructor" => "NONE",
1006 "op_flags" => "R|L|F",
1007 "state" => "exc_pinned",
1008 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1010 "emit" => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */'
1018 "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1020 "emit" => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */'
1025 "rd_constructor" => "NONE",
1026 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1028 "emit" => '. fist %ia32_emit_am /* integer Store(%A3) -> (%A1) */'
1033 "rd_constructor" => "NONE",
1034 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1036 "emit" => '. fistp %ia32_emit_am /* integer Store(%A3) -> (%A1) and pop */'
1043 "rd_constructor" => "NONE",
1044 "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
1046 "emit" => '. fldz /* x87 0.0 -> %D1 */'
1051 "rd_constructor" => "NONE",
1052 "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
1054 "emit" => '. fld1 /* x87 1.0 -> %D1 */'
1059 "rd_constructor" => "NONE",
1060 "comment" => "x87 fp Load pi: Ld pi -> reg",
1062 "emit" => '. fldpi /* x87 pi -> %D1 */'
1067 "rd_constructor" => "NONE",
1068 "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
1070 "emit" => '. fldln2 /* x87 ln(2) -> %D1 */'
1075 "rd_constructor" => "NONE",
1076 "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
1078 "emit" => '. fldlg2 /* x87 log(2) -> %D1 */'
1083 "rd_constructor" => "NONE",
1084 "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
1086 "emit" => '. fldll2t /* x87 ld(10) -> %D1 */'
1091 "rd_constructor" => "NONE",
1092 "comment" => "x87 fp Load ld e: Ld ld e -> reg",
1094 "emit" => '. fldl2e /* x87 ld(e) -> %D1 */'
1101 "comment" => "represents a x87 constant",
1102 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1103 "reg_req" => { "out" => [ "st" ] },
1104 "emit" => '. fld%M %C /* Load fConst into register -> %D1 */',
1108 # Note that it is NEVER allowed to do CSE on these nodes
1111 "op_flags" => "R|K",
1112 "comment" => "x87 stack exchange",
1113 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1114 "cmp_attr" => " return 1;\n",
1115 "emit" => '. fxch %X1 /* x87 swap %X1, %X3 */',
1120 "comment" => "x87 stack push",
1121 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1122 "cmp_attr" => " return 1;\n",
1123 "emit" => '. fld %X1 /* x87 push %X1 */',