3 # This is the specification for the ia32 assembler Firm-operations
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
8 # this string marks the beginning of a comment in emit
9 $comment_string = "/*";
11 # the number of additional opcodes you want to register
12 #$additional_opcodes = 0;
14 # The node description is done as a perl hash initializer with the
15 # following structure:
20 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
21 # "irn_flags" => "R|N|I|S"
22 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
23 # "state" => "floats|pinned|mem_pinned|exc_pinned",
25 # { "type" => "type 1", "name" => "name 1" },
26 # { "type" => "type 2", "name" => "name 2" },
29 # "comment" => "any comment for constructor",
30 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
31 # "cmp_attr" => "c source code for comparing node attributes",
32 # "emit" => "emit code with templates",
33 # "attr" => "attitional attribute arguments for constructor"
34 # "init_attr" => "emit attribute initialization template"
35 # "rd_constructor" => "c source code which constructs an ir_node"
36 # "latency" => "latency of this operation (can be float)"
39 # ... # (all nodes you need to describe)
41 # ); # close the %nodes initializer
43 # op_flags: flags for the operation, OPTIONAL (default is "N")
44 # the op_flags correspond to the firm irop_flags:
47 # C irop_flag_commutative
48 # X irop_flag_cfopcode
49 # I irop_flag_ip_cfopcode
52 # H irop_flag_highlevel
53 # c irop_flag_constlike
56 # irn_flags: special node flags, OPTIONAL (default is 0)
57 # following irn_flags are supported:
60 # I ignore for register allocation
61 # S modifies stack pointer
63 # state: state of the operation, OPTIONAL (default is "floats")
65 # arity: arity of the operation, MUST NOT BE OMITTED
67 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
68 # are always the first 3 arguments and are always autmatically
70 # If this key is missing the following arguments will be created:
71 # for i = 1 .. arity: ir_node *op_i
74 # outs: if a node defines more than one output, the names of the projections
75 # nodes having outs having automatically the mode mode_T
77 # comment: OPTIONAL comment for the node constructor
79 # rd_constructor: for every operation there will be a
80 # new_rd_<arch>_<op-name> function with the arguments from above
81 # which creates the ir_node corresponding to the defined operation
82 # you can either put the complete source code of this function here
84 # This key is OPTIONAL. If omitted, the following constructor will
86 # if (!op_<arch>_<op-name>) assert(0);
90 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
93 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
95 # latency: the latency of the operation, default is 1
100 # 1 - caller save (register must be saved by the caller of a function)
101 # 2 - callee save (register must be saved by the called function)
102 # 4 - ignore (do not assign this register)
103 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
106 { "name" => "eax", "type" => 1 },
107 { "name" => "edx", "type" => 1 },
108 { "name" => "ebx", "type" => 2 },
109 { "name" => "ecx", "type" => 1 },
110 { "name" => "esi", "type" => 2 },
111 { "name" => "edi", "type" => 2 },
112 # { "name" => "r11", "type" => 1 },
113 # { "name" => "r12", "type" => 1 },
114 # { "name" => "r13", "type" => 1 },
115 # { "name" => "r14", "type" => 1 },
116 # { "name" => "r15", "type" => 1 },
117 # { "name" => "r16", "type" => 1 },
118 # { "name" => "r17", "type" => 1 },
119 # { "name" => "r18", "type" => 1 },
120 # { "name" => "r19", "type" => 1 },
121 # { "name" => "r20", "type" => 1 },
122 # { "name" => "r21", "type" => 1 },
123 # { "name" => "r22", "type" => 1 },
124 # { "name" => "r23", "type" => 1 },
125 # { "name" => "r24", "type" => 1 },
126 # { "name" => "r25", "type" => 1 },
127 # { "name" => "r26", "type" => 1 },
128 # { "name" => "r27", "type" => 1 },
129 # { "name" => "r28", "type" => 1 },
130 # { "name" => "r29", "type" => 1 },
131 # { "name" => "r30", "type" => 1 },
132 # { "name" => "r31", "type" => 1 },
133 # { "name" => "r32", "type" => 1 },
134 { "name" => "ebp", "type" => 2 },
135 { "name" => "esp", "type" => 4 },
136 { "name" => "gp_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
137 { "name" => "gp_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
138 { "mode" => "mode_P" }
141 { "name" => "xmm0", "type" => 1 },
142 { "name" => "xmm1", "type" => 1 },
143 { "name" => "xmm2", "type" => 1 },
144 { "name" => "xmm3", "type" => 1 },
145 { "name" => "xmm4", "type" => 1 },
146 { "name" => "xmm5", "type" => 1 },
147 { "name" => "xmm6", "type" => 1 },
148 { "name" => "xmm7", "type" => 1 },
149 { "name" => "xmm_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
150 { "name" => "xmm_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
151 { "mode" => "mode_D" }
154 { "name" => "vf0", "type" => 1 },
155 { "name" => "vf1", "type" => 1 },
156 { "name" => "vf2", "type" => 1 },
157 { "name" => "vf3", "type" => 1 },
158 { "name" => "vf4", "type" => 1 },
159 { "name" => "vf5", "type" => 1 },
160 { "name" => "vf6", "type" => 1 },
161 { "name" => "vf7", "type" => 1 },
162 { "name" => "vfp_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes
163 { "name" => "vfp_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes
164 { "mode" => "mode_E" }
167 { "name" => "st0", "type" => 1 },
168 { "name" => "st1", "type" => 1 },
169 { "name" => "st2", "type" => 1 },
170 { "name" => "st3", "type" => 1 },
171 { "name" => "st4", "type" => 1 },
172 { "name" => "st5", "type" => 1 },
173 { "name" => "st6", "type" => 1 },
174 { "name" => "st7", "type" => 1 },
175 { "mode" => "mode_E" }
179 #--------------------------------------------------#
182 # _ __ _____ __ _ _ __ ___ _ __ ___ #
183 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
184 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
185 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
188 #--------------------------------------------------#
195 #-----------------------------------------------------------------#
198 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
199 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
200 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
201 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
204 #-----------------------------------------------------------------#
206 # commutative operations
209 # All nodes supporting Addressmode have 5 INs:
210 # 1 - base r1 == NoReg in case of no AM or no base
211 # 2 - index r2 == NoReg in case of no AM or no index
212 # 3 - op1 r3 == always present
213 # 4 - op2 r4 == NoReg in case of immediate operation
214 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
218 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
219 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
220 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
221 "emit" => '. add %ia32_emit_binop /* Add(%A3, %A4) -> %D1 */',
222 "outs" => [ "res", "M" ],
226 "comment" => "construct Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
227 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
228 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
229 "emit" => '. adc %ia32_emit_binop /* AddC(%A3, %A4) -> %D1 */',
230 "outs" => [ "res", "M" ],
236 "cmp_attr" => " return 1;\n",
237 "comment" => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
243 "cmp_attr" => " return 1;\n",
244 "comment" => "construct lowered Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
249 "comment" => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
250 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
251 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] },
252 "emit" => '. mul %ia32_emit_unop /* Mul(%A1, %A2) -> %D1 */',
253 "outs" => [ "EAX", "EDX", "M" ],
259 "cmp_attr" => " return 1;\n",
260 "comment" => "construct lowered MulS: MulS(a, b) = MulS(b, a) = a * b",
261 "outs" => [ "EAX", "EDX", "M" ],
267 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
268 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
269 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
270 "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */',
271 "outs" => [ "res", "M" ],
277 "cmp_attr" => " return 1;\n",
278 "comment" => "construct lowered Mul: Mul(a, b) = Mul(b, a) = a * b",
282 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
284 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
285 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
286 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] },
287 "emit" => '. imul %ia32_emit_unop /* Mulh(%A1, %A2) -> %D1 */',
288 "outs" => [ "EAX", "EDX", "M" ],
294 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
295 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
296 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
297 "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */',
298 "outs" => [ "res", "M" ],
303 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
304 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
305 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
306 "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */',
307 "outs" => [ "res", "M" ],
312 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
313 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
314 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
315 "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */',
316 "outs" => [ "res", "M" ],
321 "cmp_attr" => " return 1;\n",
322 "comment" => "construct lowered Eor: Eor(a, b) = Eor(b, a) = a EOR b",
328 "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
329 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
331 '2. cmp %S1, %S2 /* prepare Max (%S1 - %S2), (%A1, %A2) */
332 if (mode_is_signed(get_irn_mode(n))) {
333 4. cmovl %D1, %S2 /* %S1 is less %S2 */
336 4. cmovb %D1, %S2 /* %S1 is below %S2 */
344 "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
345 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
347 '2. cmp %S1, %S2 /* prepare Min (%S1 - %S2), (%A1, %A2) */
348 if (mode_is_signed(get_irn_mode(n))) {
349 2. cmovg %D1, %S2 /* %S1 is greater %S2 */
352 2. cmova %D1, %S2, %D1 /* %S1 is above %S2 */
358 # not commutative operations
362 "comment" => "construct Sub: Sub(a, b) = a - b",
363 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
364 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
365 "emit" => '. sub %ia32_emit_binop /* Sub(%A3, %A4) -> %D1 */',
366 "outs" => [ "res", "M" ],
370 "comment" => "construct Sub with Carry: SubC(a, b) = a - b - carry",
371 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
372 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
373 "emit" => '. sbb %ia32_emit_binop /* SubC(%A3, %A4) -> %D1 */',
374 "outs" => [ "res", "M" ],
379 "cmp_attr" => " return 1;\n",
380 "comment" => "construct lowered Sub: Sub(a, b) = a - b",
385 "cmp_attr" => " return 1;\n",
386 "comment" => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
392 "state" => "exc_pinned",
393 "reg_req" => { "in" => [ "eax", "gp", "edx", "none" ], "out" => [ "eax", "edx" ] },
394 "attr" => "ia32_op_flavour_t dm_flav",
395 "init_attr" => " attr->data.op_flav = dm_flav;",
396 "cmp_attr" => " return attr_a->data.op_flav != attr_b->data.op_flav;\n",
398 ' if (mode_is_signed(get_ia32_res_mode(n))) {
399 4. idiv %S2 /* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
402 4. div %S2 /* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
405 "outs" => [ "div_res", "mod_res", "M" ],
411 "comment" => "construct Shl: Shl(a, b) = a << b",
412 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
413 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
414 "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */',
415 "outs" => [ "res", "M" ],
419 "cmp_attr" => " return 1;\n",
420 "comment" => "construct lowered Shl: Shl(a, b) = a << b",
426 "comment" => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
427 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
428 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r5" ] },
431 if (get_ia32_immop_type(n) == ia32_ImmNone) {
432 if (get_ia32_op_type(n) == ia32_AddrModeD) {
433 4. shld %ia32_emit_am, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
436 4. shld %S3, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
440 if (get_ia32_op_type(n) == ia32_AddrModeD) {
441 4. shld %ia32_emit_am, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
444 4. shld %S3, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
448 "outs" => [ "res", "M" ],
453 "cmp_attr" => " return 1;\n",
454 "comment" => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
460 "comment" => "construct Shr: Shr(a, b) = a >> b",
461 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
462 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
463 "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */',
464 "outs" => [ "res", "M" ],
468 "cmp_attr" => " return 1;\n",
469 "comment" => "construct lowered Shr: Shr(a, b) = a << b",
475 "comment" => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
476 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
477 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r5" ] },
480 if (get_ia32_immop_type(n) == ia32_ImmNone) {
481 if (get_ia32_op_type(n) == ia32_AddrModeD) {
482 4. shrd %ia32_emit_am, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
485 4. shrd %S3, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
489 if (get_ia32_op_type(n) == ia32_AddrModeD) {
490 4. shrd %ia32_emit_am, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
493 4. shrd %S3, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
497 "outs" => [ "res", "M" ],
502 "cmp_attr" => " return 1;\n",
503 "comment" => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
509 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
510 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
511 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
512 "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */',
513 "outs" => [ "res", "M" ],
517 "cmp_attr" => " return 1;\n",
518 "comment" => "construct lowered Shrs: Shrs(a, b) = a << b",
524 "comment" => "construct RotR: RotR(a, b) = a ROTR b",
525 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
526 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
527 "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */',
528 "outs" => [ "res", "M" ],
533 "comment" => "construct RotL: RotL(a, b) = a ROTL b",
534 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
535 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
536 "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */',
537 "outs" => [ "res", "M" ],
544 "comment" => "construct Minus: Minus(a) = -a",
545 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
546 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
547 "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */',
548 "outs" => [ "res", "M" ],
552 "cmp_attr" => " return 1;\n",
553 "comment" => "construct lowered Minus: Minus(a) = -a",
559 "comment" => "construct Increment: Inc(a) = a++",
560 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
561 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
562 "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */',
563 "outs" => [ "res", "M" ],
568 "comment" => "construct Decrement: Dec(a) = a--",
569 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
570 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
571 "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */',
572 "outs" => [ "res", "M" ],
577 "comment" => "construct Not: Not(a) = !a",
578 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
579 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
580 "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */',
581 "outs" => [ "res", "M" ],
587 "op_flags" => "L|X|Y",
588 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
589 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
590 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
591 "outs" => [ "false", "true" ],
596 "op_flags" => "L|X|Y",
597 "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
598 "reg_req" => { "in" => [ "gp", "gp" ] },
599 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
600 "outs" => [ "false", "true" ],
605 "op_flags" => "L|X|Y",
606 "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
607 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
608 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
609 "outs" => [ "false", "true" ],
613 "op_flags" => "L|X|Y",
614 "comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
615 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
616 "reg_req" => { "in" => [ "gp", "gp" ] },
620 "op_flags" => "L|X|Y",
621 "comment" => "construct switch",
622 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
623 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
630 "comment" => "represents an integer constant",
631 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
632 "reg_req" => { "in" => [ "none" ], "out" => [ "gp" ] },
637 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
638 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
639 "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */',
640 "outs" => [ "EAX", "EDX" ],
647 "state" => "exc_pinned",
648 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
649 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
650 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
652 ' if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) {
653 4. mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
656 4. mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
659 "outs" => [ "res", "M" ],
664 "cmp_attr" => " return 1;\n",
665 "comment" => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg",
666 "outs" => [ "res", "M" ],
672 "cmp_attr" => " return 1;\n",
673 "state" => "exc_pinned",
674 "comment" => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val",
681 "state" => "exc_pinned",
682 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
683 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
684 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
685 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
691 "state" => "exc_pinned",
692 "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
693 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
694 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
695 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
701 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
702 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
703 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
704 "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */',
709 "comment" => "push a gp register on the stack",
710 "reg_req" => { "in" => [ "esp", "gp", "none" ], "out" => [ "esp" ] },
712 if (get_ia32_id_cnst(n)) {
713 if (get_ia32_immop_type(n) == ia32_ImmConst) {
714 4. push %C /* Push const on stack */
716 4. push OFFSET FLAT:%C /* Push symconst on stack */
719 else if (get_ia32_op_type(n) == ia32_Normal) {
720 2. push %S2 /* Push(%A2) */
723 2. push %ia32_emit_am /* Push memory to stack */
726 "outs" => [ "stack", "M" ],
731 "comment" => "pop a gp register from the stack",
732 "reg_req" => { "in" => [ "esp", "none" ], "out" => [ "gp", "esp" ] },
734 if (get_ia32_op_type(n) == ia32_Normal) {
735 2. pop %D1 /* Pop from stack into %D1 */
738 2. pop %ia32_emit_am /* Pop from stack into memory */
741 "outs" => [ "res", "stack", "M" ],
746 "comment" => "create stack frame",
747 "reg_req" => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] },
748 "emit" => '. enter /* Enter */',
749 "outs" => [ "frame", "stack", "M" ],
754 "comment" => "destroy stack frame",
755 "reg_req" => { "in" => [ "esp", "ebp" ], "out" => [ "ebp", "esp" ] },
756 "emit" => '. leave /* Leave */',
757 "outs" => [ "frame", "stack", "M" ],
762 "irn_flags" => "S|I",
763 "comment" => "allocate space on stack",
764 "reg_req" => { "in" => [ "esp", "gp" ], "out" => [ "esp", "none" ] },
765 "outs" => [ "stack", "M" ],
768 #-----------------------------------------------------------------------------#
769 # _____ _____ ______ __ _ _ _ #
770 # / ____/ ____| ____| / _| | | | | | #
771 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
772 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
773 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
774 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
775 #-----------------------------------------------------------------------------#
777 # commutative operations
781 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
782 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
783 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
784 "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */',
785 "outs" => [ "res", "M" ],
791 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
792 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
793 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
794 "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */',
795 "outs" => [ "res", "M" ],
801 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
802 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
803 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
804 "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */',
805 "outs" => [ "res", "M" ],
811 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
812 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
813 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
814 "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */',
815 "outs" => [ "res", "M" ],
821 "comment" => "construct SSE And: And(a, b) = a AND b",
822 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
823 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
824 "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */',
825 "outs" => [ "res", "M" ],
831 "comment" => "construct SSE Or: Or(a, b) = a OR b",
832 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
833 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
834 "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */',
835 "outs" => [ "res", "M" ],
840 "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
841 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
842 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
843 "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */',
844 "outs" => [ "res", "M" ],
848 # not commutative operations
852 "comment" => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
853 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
854 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
855 "emit" => '. andnp%M %ia32_emit_binop /* SSE AndNot(%A3, %A4) -> %D1 */',
856 "outs" => [ "res", "M" ],
862 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
863 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
864 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
865 "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */',
866 "outs" => [ "res", "M" ],
872 "comment" => "construct SSE Div: Div(a, b) = a / b",
873 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
874 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
875 "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */',
876 "outs" => [ "res", "M" ],
884 "comment" => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
885 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
886 "outs" => [ "res", "M" ],
891 "op_flags" => "L|X|Y",
892 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
893 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
894 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
895 "outs" => [ "false", "true" ],
902 "comment" => "represents a SSE constant",
903 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
904 "reg_req" => { "in" => [ "none" ], "out" => [ "xmm" ] },
905 "emit" => '. movs%M %D1, %C /* Load fConst into register */',
913 "state" => "exc_pinned",
914 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
915 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
916 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm" ] },
917 "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */',
918 "outs" => [ "res", "M" ],
924 "state" => "exc_pinned",
925 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
926 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
927 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
928 "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */',
935 "state" => "exc_pinned",
936 "comment" => "construct Store without index: Store(ptr, val, mem) = ST ptr,val",
937 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
938 "reg_req" => { "in" => [ "gp", "xmm", "none" ] },
939 "emit" => '. movs%M %ia32_emit_am, %S2 /* store XMM0 onto stack */',
946 "comment" => "construct: transfer a value from x87 FPU into a SSE register",
947 "cmp_attr" => " return 1;\n",
953 "comment" => "construct: transfer a value from SSE register to x87 FPU",
954 "cmp_attr" => " return 1;\n",
961 "state" => "exc_pinned",
962 "comment" => "store ST0 onto stack",
963 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
964 "reg_req" => { "in" => [ "gp", "none" ] },
965 "emit" => '. fstp %ia32_emit_am /* store ST0 onto stack */',
973 "state" => "exc_pinned",
974 "comment" => "load ST0 from stack",
975 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
976 "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "st0", "none" ] },
977 "emit" => '. fld %ia32_emit_am /* load ST0 from stack */',
978 "outs" => [ "res", "M" ],
987 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
988 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "edi", "esi", "ecx", "none" ] },
989 "outs" => [ "DST", "SRC", "CNT", "M" ],
995 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
996 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
997 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "edi", "esi", "none" ] },
998 "outs" => [ "DST", "SRC", "M" ],
1004 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
1005 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1006 "comment" => "construct Conv Int -> Int",
1007 "outs" => [ "res", "M" ],
1011 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
1012 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1013 "comment" => "construct Conv Int -> Int",
1014 "outs" => [ "res", "M" ],
1018 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
1019 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1020 "comment" => "construct Conv Int -> Floating Point",
1021 "outs" => [ "res", "M" ],
1026 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
1027 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1028 "comment" => "construct Conv Floating Point -> Int",
1029 "outs" => [ "res", "M" ],
1034 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
1035 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1036 "comment" => "construct Conv Floating Point -> Floating Point",
1037 "outs" => [ "res", "M" ],
1043 "comment" => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
1044 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "in_r4" ] },
1050 "comment" => "check if Psi condition tree evaluates to true and move result accordingly",
1051 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r3" ] },
1057 "comment" => "construct Conditional Move: SSE Compare + int CMov ",
1058 "reg_req" => { "in" => [ "xmm", "xmm", "gp", "gp" ], "out" => [ "in_r4" ] },
1064 "comment" => "construct Conditional Move: x87 Compare + int CMov",
1065 "reg_req" => { "in" => [ "vfp", "vfp", "gp", "gp" ], "out" => [ "in_r4" ] },
1071 "comment" => "construct Set: Set(sel) == sel ? 1 : 0",
1072 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1073 "outs" => [ "res", "M" ],
1079 "comment" => "check if Psi condition tree evaluates to true and set result accordingly",
1080 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax ebx ecx edx" ] },
1086 "comment" => "construct Set: SSE Compare + int Set",
1087 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1088 "outs" => [ "res", "M" ],
1094 "comment" => "construct Set: x87 Compare + int Set",
1095 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1096 "outs" => [ "res", "M" ],
1102 "comment" => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
1103 "reg_req" => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] },
1107 #----------------------------------------------------------#
1109 # (_) | | | | / _| | | | #
1110 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
1111 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
1112 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
1113 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
1115 # _ __ ___ __| | ___ ___ #
1116 # | '_ \ / _ \ / _` |/ _ \/ __| #
1117 # | | | | (_) | (_| | __/\__ \ #
1118 # |_| |_|\___/ \__,_|\___||___/ #
1119 #----------------------------------------------------------#
1123 "comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
1124 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1125 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1126 "outs" => [ "res", "M" ],
1132 "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1133 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1134 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1135 "outs" => [ "res", "M" ],
1141 "cmp_attr" => " return 1;\n",
1142 "comment" => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1148 "comment" => "virtual fp Sub: Sub(a, b) = a - b",
1149 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1150 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1151 "outs" => [ "res", "M" ],
1156 "cmp_attr" => " return 1;\n",
1157 "comment" => "lowered virtual fp Sub: Sub(a, b) = a - b",
1162 "comment" => "virtual fp Div: Div(a, b) = a / b",
1163 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1164 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1165 "outs" => [ "res", "M" ],
1170 "cmp_attr" => " return 1;\n",
1171 "comment" => "lowered virtual fp Div: Div(a, b) = a / b",
1177 "comment" => "virtual fp Abs: Abs(a) = |a|",
1178 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1184 "comment" => "virtual fp Chs: Chs(a) = -a",
1185 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1191 "comment" => "virtual fp Sin: Sin(a) = sin(a)",
1192 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1198 "comment" => "virtual fp Cos: Cos(a) = cos(a)",
1199 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1205 "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
1206 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1210 # virtual Load and Store
1213 "op_flags" => "L|F",
1214 "state" => "exc_pinned",
1215 "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
1216 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1217 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1218 "outs" => [ "res", "M" ],
1223 "op_flags" => "L|F",
1224 "state" => "exc_pinned",
1225 "comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
1226 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1227 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1235 "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1236 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1237 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1238 "outs" => [ "res", "M" ],
1243 "cmp_attr" => " return 1;\n",
1244 "comment" => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1245 "outs" => [ "res", "M" ],
1250 "comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1251 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1252 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1258 "cmp_attr" => " return 1;\n",
1259 "comment" => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1269 "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg",
1270 "reg_req" => { "out" => [ "vfp" ] },
1276 "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg",
1277 "reg_req" => { "out" => [ "vfp" ] },
1283 "comment" => "virtual fp Load pi: Ld pi -> reg",
1284 "reg_req" => { "out" => [ "vfp" ] },
1290 "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg",
1291 "reg_req" => { "out" => [ "vfp" ] },
1297 "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg",
1298 "reg_req" => { "out" => [ "vfp" ] },
1304 "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg",
1305 "reg_req" => { "out" => [ "vfp" ] },
1311 "comment" => "virtual fp Load ld e: Ld ld e -> reg",
1312 "reg_req" => { "out" => [ "vfp" ] },
1319 "init_attr" => " set_ia32_ls_mode(res, mode);",
1320 "comment" => "represents a virtual floating point constant",
1321 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1322 "reg_req" => { "in" => [ "none" ], "out" => [ "vfp" ] },
1329 "op_flags" => "L|X|Y",
1330 "comment" => "represents a virtual floating point compare",
1331 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1332 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] },
1333 "outs" => [ "false", "true", "temp_reg_eax" ],
1337 #------------------------------------------------------------------------#
1338 # ___ _____ __ _ _ _ #
1339 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1340 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1341 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1342 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1343 #------------------------------------------------------------------------#
1347 "rd_constructor" => "NONE",
1348 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1350 "emit" => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */',
1355 "rd_constructor" => "NONE",
1356 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1358 "emit" => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */',
1363 "rd_constructor" => "NONE",
1364 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1366 "emit" => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */',
1371 "rd_constructor" => "NONE",
1372 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1374 "emit" => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */',,
1379 "rd_constructor" => "NONE",
1380 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1382 "emit" => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */',
1387 "rd_constructor" => "NONE",
1388 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1390 "emit" => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */',
1395 "rd_constructor" => "NONE",
1397 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1399 "emit" => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */',
1404 "rd_constructor" => "NONE",
1406 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1408 "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */',
1413 "rd_constructor" => "NONE",
1414 "comment" => "x87 fp Div: Div(a, b) = a / b",
1416 "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */',
1421 "rd_constructor" => "NONE",
1422 "comment" => "x87 fp Div: Div(a, b) = a / b",
1424 "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */',
1429 "rd_constructor" => "NONE",
1430 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1432 "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */',
1437 "rd_constructor" => "NONE",
1438 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1440 "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */',
1445 "rd_constructor" => "NONE",
1446 "comment" => "x87 fp Abs: Abs(a) = |a|",
1448 "emit" => '. fabs /* x87 fabs(%S1) -> %D1 */',
1453 "rd_constructor" => "NONE",
1454 "comment" => "x87 fp Chs: Chs(a) = -a",
1456 "emit" => '. fchs /* x87 fchs(%S1) -> %D1 */',
1461 "rd_constructor" => "NONE",
1462 "comment" => "x87 fp Sin: Sin(a) = sin(a)",
1464 "emit" => '. fsin /* x87 sin(%S1) -> %D1 */',
1469 "rd_constructor" => "NONE",
1470 "comment" => "x87 fp Cos: Cos(a) = cos(a)",
1472 "emit" => '. fcos /* x87 cos(%S1) -> %D1 */',
1477 "rd_constructor" => "NONE",
1478 "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1480 "emit" => '. fsqrt $ /* x87 sqrt(%S1) -> %D1 */',
1483 # x87 Load and Store
1486 "rd_constructor" => "NONE",
1487 "op_flags" => "R|L|F",
1488 "state" => "exc_pinned",
1489 "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1491 "emit" => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */',
1495 "rd_constructor" => "NONE",
1496 "op_flags" => "R|L|F",
1497 "state" => "exc_pinned",
1498 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1500 "emit" => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */',
1504 "rd_constructor" => "NONE",
1505 "op_flags" => "R|L|F",
1506 "state" => "exc_pinned",
1507 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1509 "emit" => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */',
1516 "rd_constructor" => "NONE",
1517 "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1519 "emit" => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */',
1524 "rd_constructor" => "NONE",
1525 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1527 "emit" => '. fist %ia32_emit_am /* integer Store(%A3) -> (%A1) */',
1532 "rd_constructor" => "NONE",
1533 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1535 "emit" => '. fistp %ia32_emit_am /* integer Store(%A3) -> (%A1) and pop */',
1543 "rd_constructor" => "NONE",
1544 "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
1546 "emit" => '. fldz /* x87 0.0 -> %D1 */',
1552 "rd_constructor" => "NONE",
1553 "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
1555 "emit" => '. fld1 /* x87 1.0 -> %D1 */',
1561 "rd_constructor" => "NONE",
1562 "comment" => "x87 fp Load pi: Ld pi -> reg",
1564 "emit" => '. fldpi /* x87 pi -> %D1 */',
1570 "rd_constructor" => "NONE",
1571 "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
1573 "emit" => '. fldln2 /* x87 ln(2) -> %D1 */',
1579 "rd_constructor" => "NONE",
1580 "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
1582 "emit" => '. fldlg2 /* x87 log(2) -> %D1 */',
1588 "rd_constructor" => "NONE",
1589 "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
1591 "emit" => '. fldll2t /* x87 ld(10) -> %D1 */',
1597 "rd_constructor" => "NONE",
1598 "comment" => "x87 fp Load ld e: Ld ld e -> reg",
1600 "emit" => '. fldl2e /* x87 ld(e) -> %D1 */',
1604 "op_flags" => "R|c",
1606 "rd_constructor" => "NONE",
1607 "comment" => "represents a x87 constant",
1608 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1609 "reg_req" => { "out" => [ "st" ] },
1610 "emit" => '. fld %ia32_emit_adr /* Load fConst into register -> %D1 */',
1614 # Note that it is NEVER allowed to do CSE on these nodes
1617 "op_flags" => "R|K",
1618 "comment" => "x87 stack exchange",
1619 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1620 "cmp_attr" => " return 1;\n",
1621 "emit" => '. fxch %X1 /* x87 swap %X1, %X3 */',
1626 "comment" => "x87 stack push",
1627 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1628 "cmp_attr" => " return 1;\n",
1629 "emit" => '. fld %X1 /* x87 push %X1 */',
1633 "op_flags" => "R|K",
1634 "comment" => "x87 stack pop",
1635 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1636 "cmp_attr" => " return 1;\n",
1637 "emit" => '. fstp %X1 /* x87 pop %X1 */',
1643 "op_flags" => "L|X|Y",
1644 "comment" => "floating point compare",
1645 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1650 "op_flags" => "L|X|Y",
1651 "comment" => "floating point compare and pop",
1652 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1657 "op_flags" => "L|X|Y",
1658 "comment" => "floating point compare and pop twice",
1659 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1664 "op_flags" => "L|X|Y",
1665 "comment" => "floating point compare reverse",
1666 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1671 "op_flags" => "L|X|Y",
1672 "comment" => "floating point compare reverse and pop",
1673 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1678 "op_flags" => "L|X|Y",
1679 "comment" => "floating point compare reverse and pop twice",
1680 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",