3 # This is the specification for the ia32 assembler Firm-operations
7 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
10 # The node description is done as a perl hash initializer with the
11 # following structure:
16 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
17 # "irn_flags" => "R|N|I|S"
18 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
19 # "state" => "floats|pinned|mem_pinned|exc_pinned",
21 # { "type" => "type 1", "name" => "name 1" },
22 # { "type" => "type 2", "name" => "name 2" },
25 # "comment" => "any comment for constructor",
26 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
27 # "cmp_attr" => "c source code for comparing node attributes",
28 # "emit" => "emit code with templates",
29 # "attr" => "attitional attribute arguments for constructor"
30 # "init_attr" => "emit attribute initialization template"
31 # "rd_constructor" => "c source code which constructs an ir_node"
32 # "latency" => "latency of this operation (can be float)"
35 # ... # (all nodes you need to describe)
37 # ); # close the %nodes initializer
39 # op_flags: flags for the operation, OPTIONAL (default is "N")
40 # the op_flags correspond to the firm irop_flags:
43 # C irop_flag_commutative
44 # X irop_flag_cfopcode
45 # I irop_flag_ip_cfopcode
48 # H irop_flag_highlevel
49 # c irop_flag_constlike
52 # irn_flags: special node flags, OPTIONAL (default is 0)
53 # following irn_flags are supported:
56 # I ignore for register allocation
57 # S modifies stack pointer
59 # state: state of the operation, OPTIONAL (default is "floats")
61 # arity: arity of the operation, MUST NOT BE OMITTED
63 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
64 # are always the first 3 arguments and are always autmatically
66 # If this key is missing the following arguments will be created:
67 # for i = 1 .. arity: ir_node *op_i
70 # outs: if a node defines more than one output, the names of the projections
71 # nodes having outs having automatically the mode mode_T
72 # One can also annotate some flags for each out, additional to irn_flags.
73 # They are separated from name with a colon ':', and concatenated by pipe '|'
74 # Only I and S are available at the moment (same meaning as in irn_flags).
75 # example: [ "frame:I", "stack:I|S", "M" ]
77 # comment: OPTIONAL comment for the node constructor
79 # rd_constructor: for every operation there will be a
80 # new_rd_<arch>_<op-name> function with the arguments from above
81 # which creates the ir_node corresponding to the defined operation
82 # you can either put the complete source code of this function here
84 # This key is OPTIONAL. If omitted, the following constructor will
86 # if (!op_<arch>_<op-name>) assert(0);
90 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
93 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
95 # latency: the latency of the operation, default is 1
100 # 1 - caller save (register must be saved by the caller of a function)
101 # 2 - callee save (register must be saved by the called function)
102 # 4 - ignore (do not assign this register)
103 # 8 - emitter can choose an arbitrary register of this class
104 # 16 - the register is a virtual one
105 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
108 { "name" => "eax", "type" => 1 },
109 { "name" => "edx", "type" => 1 },
110 { "name" => "ebx", "type" => 2 },
111 { "name" => "ecx", "type" => 1 },
112 { "name" => "esi", "type" => 2 },
113 { "name" => "edi", "type" => 2 },
114 { "name" => "ebp", "type" => 2 },
115 { "name" => "esp", "type" => 4 },
116 { "name" => "gp_NOREG", "type" => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
117 { "name" => "gp_UKNWN", "type" => 4 | 8 | 16 }, # we need a dummy register for Unknown nodes
118 { "mode" => "mode_Iu" }
121 { "name" => "xmm0", "type" => 1 },
122 { "name" => "xmm1", "type" => 1 },
123 { "name" => "xmm2", "type" => 1 },
124 { "name" => "xmm3", "type" => 1 },
125 { "name" => "xmm4", "type" => 1 },
126 { "name" => "xmm5", "type" => 1 },
127 { "name" => "xmm6", "type" => 1 },
128 { "name" => "xmm7", "type" => 1 },
129 { "name" => "xmm_NOREG", "type" => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
130 { "name" => "xmm_UKNWN", "type" => 4 | 8 | 16 }, # we need a dummy register for Unknown nodes
131 { "mode" => "mode_E" }
134 { "name" => "vf0", "type" => 1 | 16 },
135 { "name" => "vf1", "type" => 1 | 16 },
136 { "name" => "vf2", "type" => 1 | 16 },
137 { "name" => "vf3", "type" => 1 | 16 },
138 { "name" => "vf4", "type" => 1 | 16 },
139 { "name" => "vf5", "type" => 1 | 16 },
140 { "name" => "vf6", "type" => 1 | 16 },
141 { "name" => "vf7", "type" => 1 | 16 },
142 { "name" => "vfp_NOREG", "type" => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
143 { "name" => "vfp_UKNWN", "type" => 4 | 8 | 16 }, # we need a dummy register for Unknown nodes
144 { "mode" => "mode_E" }
147 { "name" => "st0", "type" => 1 },
148 { "name" => "st1", "type" => 1 },
149 { "name" => "st2", "type" => 1 },
150 { "name" => "st3", "type" => 1 },
151 { "name" => "st4", "type" => 1 },
152 { "name" => "st5", "type" => 1 },
153 { "name" => "st6", "type" => 1 },
154 { "name" => "st7", "type" => 1 },
155 { "mode" => "mode_E" }
157 "fp_cw" => [ # the floating point control word
158 { "name" => "fpcw", "type" => 0 },
159 { "mode" => "mode_Hu" },
164 "GP" => [ 1, "GP_EAX", "GP_EBX", "GP_ECX", "GP_EDX", "GP_ESI", "GP_EDI", "GP_EBP" ],
165 "SSE" => [ 1, "SSE_XMM0", "SSE_XMM1", "SSE_XMM2", "SSE_XMM3", "SSE_XMM4", "SSE_XMM5", "SSE_XMM6", "SSE_XMM7" ],
166 "VFP" => [ 1, "VFP_VF0", "VFP_VF1", "VFP_VF2", "VFP_VF3", "VFP_VF4", "VFP_VF5", "VFP_VF6", "VFP_VF7" ],
167 "BRANCH" => [ 1, "BRANCH1", "BRANCH2" ],
172 "bundels_per_cycle" => 1
176 "S1" => "${arch}_emit_source_register(env, node, 0);",
177 "S2" => "${arch}_emit_source_register(env, node, 1);",
178 "S3" => "${arch}_emit_source_register(env, node, 2);",
179 "S4" => "${arch}_emit_source_register(env, node, 3);",
180 "S5" => "${arch}_emit_source_register(env, node, 4);",
181 "S6" => "${arch}_emit_source_register(env, node, 5);",
182 "D1" => "${arch}_emit_dest_register(env, node, 0);",
183 "D2" => "${arch}_emit_dest_register(env, node, 1);",
184 "D3" => "${arch}_emit_dest_register(env, node, 2);",
185 "D4" => "${arch}_emit_dest_register(env, node, 3);",
186 "D5" => "${arch}_emit_dest_register(env, node, 4);",
187 "D6" => "${arch}_emit_dest_register(env, node, 5);",
188 "A1" => "${arch}_emit_in_node_name(env, node, 0);",
189 "A2" => "${arch}_emit_in_node_name(env, node, 1);",
190 "A3" => "${arch}_emit_in_node_name(env, node, 2);",
191 "A4" => "${arch}_emit_in_node_name(env, node, 3);",
192 "A5" => "${arch}_emit_in_node_name(env, node, 4);",
193 "A6" => "${arch}_emit_in_node_name(env, node, 5);",
194 "X1" => "${arch}_emit_x87_name(env, node, 0);",
195 "X2" => "${arch}_emit_x87_name(env, node, 1);",
196 "X3" => "${arch}_emit_x87_name(env, node, 2);",
197 "C" => "${arch}_emit_immediate(env, node);",
198 "SE" => "${arch}_emit_extend_suffix(env, get_ia32_ls_mode(node));",
199 "ME" => "if(get_mode_size_bits(get_ia32_ls_mode(node)) != 32)\n
200 ${arch}_emit_mode_suffix(env, get_ia32_ls_mode(node));",
201 "M" => "${arch}_emit_mode_suffix(env, get_ia32_ls_mode(node));",
202 "XM" => "${arch}_emit_x87_mode_suffix(env, node);",
203 "AM" => "${arch}_emit_am(env, node);",
204 "unop" => "${arch}_emit_unop(env, node);",
205 "binop" => "${arch}_emit_binop(env, node);",
206 "x87_binop" => "${arch}_emit_x87_binop(env, node);",
209 #--------------------------------------------------#
212 # _ __ _____ __ _ _ __ ___ _ __ ___ #
213 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
214 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
215 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
218 #--------------------------------------------------#
220 $default_cmp_attr = "return ia32_compare_attr(attr_a, attr_b);";
227 #-----------------------------------------------------------------#
230 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
231 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
232 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
233 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
236 #-----------------------------------------------------------------#
238 # commutative operations
241 # All nodes supporting Addressmode have 5 INs:
242 # 1 - base r1 == NoReg in case of no AM or no base
243 # 2 - index r2 == NoReg in case of no AM or no index
244 # 3 - op1 r3 == always present
245 # 4 - op2 r4 == NoReg in case of immediate operation
246 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
250 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
251 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
252 "emit" => '. addl %binop',
258 "comment" => "construct Add with Carry: Adc(a, b) = Add(b, a) = a + b + carry",
259 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
260 "emit" => '. adcl %binop',
267 "comment" => "construct 64Bit Add: Add(a_l, a_h, b_l, b_h) = a_l + b_l; a_h + b_h + carry",
269 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
276 "outs" => [ "low_res", "high_res" ],
283 "cmp_attr" => "return 1;",
284 "comment" => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
290 "cmp_attr" => "return 1;",
291 "comment" => "construct lowered Add with Carry: Adc(a, b) = Adc(b, a) = a + b + carry",
296 # we should not rematrialize this node. It produces 2 results and has
297 # very strict constrains
298 "comment" => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
299 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx", "none" ] },
300 "emit" => '. mull %unop',
301 "outs" => [ "EAX", "EDX", "M" ],
307 # we should not rematrialize this node. It produces 2 results and has
308 # very strict constrains
310 "cmp_attr" => "return 1;",
311 "comment" => "construct lowered MulS: Mul(a, b) = Mul(b, a) = a * b",
312 "outs" => [ "EAX", "EDX", "M" ],
318 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
319 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
320 "emit" => '. imull %binop',
328 "comment" => "construct Mul (1 operand format): Mul(a, b) = Mul(b, a) = a * b",
329 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx", "none" ] },
330 "emit" => '. imull %unop',
331 "outs" => [ "EAX", "EDX", "M" ],
338 "cmp_attr" => "return 1;",
339 "comment" => "construct lowered IMul: IMul(a, b) = IMul(b, a) = a * b",
345 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
346 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
347 "emit" => '. andl %binop',
354 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
355 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
356 "emit" => '. orl %binop',
363 "comment" => "construct Xor: Xor(a, b) = Xor(b, a) = a EOR b",
364 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
365 "emit" => '. xorl %binop',
372 "cmp_attr" => "return 1;",
373 "comment" => "construct lowered Xor: Xor(a, b) = Xor(b, a) = a XOR b",
377 # not commutative operations
381 "comment" => "construct Sub: Sub(a, b) = a - b",
382 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
383 "emit" => '. subl %binop',
389 "comment" => "construct Sub with Carry: SubC(a, b) = a - b - carry",
390 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3 !in_r4" ] },
391 "emit" => '. sbbl %binop',
398 "comment" => "construct 64Bit Sub: Sub(a_l, a_h, b_l, b_h) = a_l - b_l; a_h - b_h - borrow",
400 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
407 "outs" => [ "low_res", "high_res" ],
413 "cmp_attr" => "return 1;",
414 "comment" => "construct lowered Sub: Sub(a, b) = a - b",
419 "cmp_attr" => "return 1;",
420 "comment" => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
426 "state" => "exc_pinned",
427 "reg_req" => { "in" => [ "gp", "gp", "eax", "edx", "gp", "none" ], "out" => [ "eax", "edx", "none" ] },
428 "attr" => "ia32_op_flavour_t dm_flav",
429 "init_attr" => "attr->data.op_flav = dm_flav;",
430 "emit" => ". idivl %unop",
431 "outs" => [ "div_res", "mod_res", "M" ],
438 "state" => "exc_pinned",
439 "reg_req" => { "in" => [ "gp", "gp", "eax", "edx", "gp", "none" ], "out" => [ "eax", "edx", "none" ] },
440 "attr" => "ia32_op_flavour_t dm_flav",
441 "init_attr" => "attr->data.op_flav = dm_flav;",
442 "emit" => ". divl %unop",
443 "outs" => [ "div_res", "mod_res", "M" ],
450 "comment" => "construct Shl: Shl(a, b) = a << b",
451 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
452 "emit" => '. shll %binop',
458 "cmp_attr" => "return 1;",
459 "comment" => "construct lowered Shl: Shl(a, b) = a << b",
465 "comment" => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
466 # Out requirements is: different from all in
467 # This is because, out must be different from LowPart and ShiftCount.
468 # We could say "!ecx !in_r4" but it can occur, that all values live through
469 # this Shift and the only value dying is the ShiftCount. Then there would be a
470 # register missing, as result must not be ecx and all other registers are
471 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
472 # (and probably never will). So we create artificial interferences of the result
473 # with all inputs, so the spiller can always assure a free register.
474 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!in" ] },
477 if (get_ia32_immop_type(node) == ia32_ImmNone) {
478 if (get_ia32_op_type(node) == ia32_AddrModeD) {
479 . shldl %%cl, %S4, %AM
481 . shldl %%cl, %S4, %S3
484 if (get_ia32_op_type(node) == ia32_AddrModeD) {
485 . shldl $%C, %S4, %AM
487 . shldl $%C, %S4, %S3
497 "cmp_attr" => "return 1;",
498 "comment" => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
504 "comment" => "construct Shr: Shr(a, b) = a >> b",
505 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
506 "emit" => '. shrl %binop',
512 "cmp_attr" => "return 1;",
513 "comment" => "construct lowered Shr: Shr(a, b) = a << b",
519 "comment" => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
520 # Out requirements is: different from all in
521 # This is because, out must be different from LowPart and ShiftCount.
522 # We could say "!ecx !in_r4" but it can occur, that all values live through
523 # this Shift and the only value dying is the ShiftCount. Then there would be a
524 # register missing, as result must not be ecx and all other registers are
525 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
526 # (and probably never will). So we create artificial interferences of the result
527 # with all inputs, so the spiller can always assure a free register.
528 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!in" ] },
530 if (get_ia32_immop_type(node) == ia32_ImmNone) {
531 if (get_ia32_op_type(node) == ia32_AddrModeD) {
532 . shrdl %%cl, %S4, %AM
534 . shrdl %%cl, %S4, %S3
537 if (get_ia32_op_type(node) == ia32_AddrModeD) {
538 . shrdl $%C, %S4, %AM
540 . shrdl $%C, %S4, %S3
550 "cmp_attr" => "return 1;",
551 "comment" => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
557 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
558 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
559 "emit" => '. sarl %binop',
565 "cmp_attr" => "return 1;",
566 "comment" => "construct lowered Sar: Sar(a, b) = a << b",
572 "comment" => "construct Ror: Ror(a, b) = a ROR b",
573 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
574 "emit" => '. rorl %binop',
581 "comment" => "construct Rol: Rol(a, b) = a ROL b",
582 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
583 "emit" => '. roll %binop',
592 "comment" => "construct Minus: Minus(a) = -a",
593 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
594 "emit" => '. negl %unop',
601 "comment" => "construct 64Bit Minus: Minus(a_l, a_h, 0) = 0 - a_l; 0 - a_h - borrow",
603 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
610 "outs" => [ "low_res", "high_res" ],
616 "cmp_attr" => "return 1;",
617 "comment" => "construct lowered Minus: Minus(a) = -a",
623 "comment" => "construct Increment: Inc(a) = a++",
624 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
625 "emit" => '. incl %unop',
632 "comment" => "construct Decrement: Dec(a) = a--",
633 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
634 "emit" => '. decl %unop',
641 "comment" => "construct Not: Not(a) = !a",
642 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
643 "emit" => '. notl %unop',
651 "op_flags" => "L|X|Y",
652 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
653 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
654 "outs" => [ "false", "true" ],
656 "units" => [ "BRANCH" ],
660 "op_flags" => "L|X|Y",
661 "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
662 "reg_req" => { "in" => [ "gp", "gp" ] },
663 "outs" => [ "false", "true" ],
665 "units" => [ "BRANCH" ],
669 "op_flags" => "L|X|Y",
670 "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
671 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
672 "outs" => [ "false", "true" ],
673 "units" => [ "BRANCH" ],
677 "op_flags" => "L|X|Y",
678 "comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
679 "reg_req" => { "in" => [ "gp", "gp" ] },
680 "units" => [ "BRANCH" ],
684 "op_flags" => "L|X|Y",
685 "comment" => "construct switch",
686 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
688 "units" => [ "BRANCH" ],
694 "comment" => "represents an integer constant",
695 "reg_req" => { "out" => [ "gp" ] },
703 "comment" => "unknown value",
704 "reg_req" => { "out" => [ "gp_UKNWN" ] },
713 "comment" => "unknown value",
714 "reg_req" => { "out" => [ "vfp_UKNWN" ] },
723 "comment" => "unknown value",
724 "reg_req" => { "out" => [ "xmm_UKNWN" ] },
733 "comment" => "unknown GP value",
734 "reg_req" => { "out" => [ "gp_NOREG" ] },
743 "comment" => "unknown VFP value",
744 "reg_req" => { "out" => [ "vfp_NOREG" ] },
753 "comment" => "unknown XMM value",
754 "reg_req" => { "out" => [ "xmm_NOREG" ] },
762 "comment" => "change floating point control word",
763 "reg_req" => { "out" => [ "fp_cw" ] },
771 "state" => "exc_pinned",
772 "comment" => "load floating point control word FldCW(ptr, mem) = LD ptr -> reg",
773 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "fp_cw" ] },
775 "emit" => ". fldcw %AM",
782 "state" => "exc_pinned",
783 "comment" => "store floating point control word: FstCW(ptr, mem) = ST ptr -> reg",
784 "reg_req" => { "in" => [ "gp", "gp", "fp_cw", "none" ] },
786 "emit" => ". fstcw %AM",
792 # we should not rematrialize this node. It produces 2 results and has
793 # very strict constrains
794 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
795 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
797 "outs" => [ "EAX", "EDX" ],
805 "state" => "exc_pinned",
806 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
807 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp", "none" ] },
809 "emit" => ". mov%SE%ME%.l %AM, %D1",
810 "outs" => [ "res", "M" ],
816 "cmp_attr" => "return 1;",
817 "comment" => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg",
818 "outs" => [ "res", "M" ],
824 "cmp_attr" => "return 1;",
825 "state" => "exc_pinned",
826 "comment" => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val",
833 "state" => "exc_pinned",
834 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
835 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
836 "emit" => '. mov%M %binop',
844 "state" => "exc_pinned",
845 "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
846 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
847 "emit" => '. mov%M %binop',
855 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
856 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
857 "emit" => '. leal %AM, %D1',
864 "comment" => "push on the stack",
865 "reg_req" => { "in" => [ "gp", "gp", "gp", "esp", "none" ], "out" => [ "esp", "none" ] },
866 "emit" => '. pushl %unop',
867 "outs" => [ "stack:I|S", "M" ],
873 "comment" => "pop a gp register from the stack",
874 "reg_req" => { "in" => [ "gp", "gp", "esp", "none" ], "out" => [ "esp", "gp", "none" ] },
875 "emit" => '. popl %unop',
876 "outs" => [ "stack:I|S", "res", "M" ],
882 "comment" => "create stack frame",
883 "reg_req" => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] },
885 "outs" => [ "frame:I", "stack:I|S", "M" ],
891 "comment" => "destroy stack frame",
892 "reg_req" => { "in" => [ "esp", "ebp" ], "out" => [ "ebp", "esp" ] },
894 "outs" => [ "frame:I", "stack:I|S" ],
901 "comment" => "allocate space on stack",
902 "reg_req" => { "in" => [ "gp", "gp", "esp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
903 "emit" => '. addl %binop',
904 "outs" => [ "stack:S", "M" ],
910 "comment" => "free space on stack",
911 "reg_req" => { "in" => [ "gp", "gp", "esp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
912 "emit" => '. subl %binop',
913 "outs" => [ "stack:S", "M" ],
919 "comment" => "get the TLS base address",
920 "reg_req" => { "out" => [ "gp" ] },
926 #-----------------------------------------------------------------------------#
927 # _____ _____ ______ __ _ _ _ #
928 # / ____/ ____| ____| / _| | | | | | #
929 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
930 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
931 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
932 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
933 #-----------------------------------------------------------------------------#
935 # commutative operations
939 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
940 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
941 "emit" => '. adds%M %binop',
943 "units" => [ "SSE" ],
949 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
950 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
951 "emit" => '. muls%M %binop',
953 "units" => [ "SSE" ],
959 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
960 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
961 "emit" => '. maxs%M %binop',
963 "units" => [ "SSE" ],
969 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
970 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
971 "emit" => '. mins%M %binop',
973 "units" => [ "SSE" ],
979 "comment" => "construct SSE And: And(a, b) = a AND b",
980 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
981 "emit" => '. andp%M %binop',
983 "units" => [ "SSE" ],
989 "comment" => "construct SSE Or: Or(a, b) = a OR b",
990 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
991 "emit" => '. orp%M %binop',
992 "units" => [ "SSE" ],
998 "comment" => "construct SSE Xor: Xor(a, b) = a XOR b",
999 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
1000 "emit" => '. xorp%M %binop',
1002 "units" => [ "SSE" ],
1006 # not commutative operations
1010 "comment" => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
1011 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
1012 "emit" => '. andnp%M %binop',
1014 "units" => [ "SSE" ],
1020 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
1021 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
1022 "emit" => '. subs%M %binop',
1024 "units" => [ "SSE" ],
1030 "comment" => "construct SSE Div: Div(a, b) = a / b",
1031 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
1032 "outs" => [ "res", "M" ],
1033 "emit" => '. divs%M %binop',
1035 "units" => [ "SSE" ],
1042 "comment" => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
1043 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
1045 "units" => [ "SSE" ],
1050 "op_flags" => "L|X|Y",
1051 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
1052 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
1053 "outs" => [ "false", "true" ],
1055 "units" => [ "SSE" ],
1061 "comment" => "represents a SSE constant",
1062 "reg_req" => { "out" => [ "xmm" ] },
1063 "emit" => '. movs%M %D1, $%C',
1065 "units" => [ "SSE" ],
1072 "op_flags" => "L|F",
1073 "state" => "exc_pinned",
1074 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
1075 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
1076 "emit" => '. movs%M %D1, %AM',
1077 "outs" => [ "res", "M" ],
1079 "units" => [ "SSE" ],
1083 "op_flags" => "L|F",
1084 "state" => "exc_pinned",
1085 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
1086 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
1087 "emit" => '. movs%M %binop',
1089 "units" => [ "SSE" ],
1094 "op_flags" => "L|F",
1095 "state" => "exc_pinned",
1096 "comment" => "construct Store without index: Store(ptr, val, mem) = ST ptr,val",
1097 "reg_req" => { "in" => [ "gp", "xmm", "none" ] },
1098 "emit" => '. movs%M %AM, %S2',
1100 "units" => [ "SSE" ],
1105 "op_flags" => "L|F",
1106 "comment" => "construct: transfer a value from x87 FPU into a SSE register",
1107 "cmp_attr" => "return 1;",
1112 "op_flags" => "L|F",
1113 "comment" => "construct: transfer a value from SSE register to x87 FPU",
1114 "cmp_attr" => "return 1;",
1119 "op_flags" => "L|F",
1121 "state" => "exc_pinned",
1122 "comment" => "store ST0 onto stack",
1123 "reg_req" => { "in" => [ "gp", "gp", "none" ] },
1124 "emit" => '. fstp%XM %AM',
1126 "units" => [ "SSE" ],
1131 "op_flags" => "L|F",
1133 "state" => "exc_pinned",
1134 "comment" => "load ST0 from stack",
1135 "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "vf0", "none" ] },
1136 "emit" => '. fld%M %AM',
1137 "outs" => [ "res", "M" ],
1139 "units" => [ "SSE" ],
1145 "op_flags" => "F|H",
1146 "state" => "pinned",
1147 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
1148 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "edi", "esi", "ecx", "none" ] },
1149 "outs" => [ "DST", "SRC", "CNT", "M" ],
1150 "units" => [ "GP" ],
1154 "op_flags" => "F|H",
1155 "state" => "pinned",
1156 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
1157 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "edi", "esi", "none" ] },
1158 "outs" => [ "DST", "SRC", "M" ],
1159 "units" => [ "GP" ],
1165 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
1166 "comment" => "construct Conv Int -> Int",
1167 "units" => [ "GP" ],
1168 "mode" => "mode_Iu",
1172 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
1173 "comment" => "construct Conv Int -> Int",
1174 "units" => [ "GP" ],
1175 "mode" => "mode_Iu",
1179 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
1180 "comment" => "construct Conv Int -> Floating Point",
1182 "units" => [ "SSE" ],
1187 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
1188 "comment" => "construct Conv Floating Point -> Int",
1190 "units" => [ "SSE" ],
1191 "mode" => "mode_Iu",
1195 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
1196 "comment" => "construct Conv Floating Point -> Floating Point",
1198 "units" => [ "SSE" ],
1204 "comment" => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
1205 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "in_r4" ] },
1207 "units" => [ "GP" ],
1208 "mode" => "mode_Iu",
1213 "comment" => "check if Psi condition tree evaluates to true and move result accordingly",
1214 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r3" ] },
1216 "units" => [ "GP" ],
1217 "mode" => "mode_Iu",
1222 "comment" => "construct Conditional Move: SSE Compare + int CMov ",
1223 "reg_req" => { "in" => [ "xmm", "xmm", "gp", "gp" ], "out" => [ "in_r4" ] },
1225 "units" => [ "SSE" ],
1226 "mode" => "mode_Iu",
1231 "comment" => "construct Conditional Move: x87 Compare + int CMov",
1232 "reg_req" => { "in" => [ "vfp", "vfp", "gp", "gp" ], "out" => [ "in_r4" ] },
1234 "units" => [ "VFP" ],
1235 "mode" => "mode_Iu",
1240 "comment" => "construct Set: Set(sel) == sel ? 1 : 0",
1241 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax ebx ecx edx" ] },
1243 "units" => [ "GP" ],
1244 "mode" => "mode_Iu",
1249 "comment" => "check if Psi condition tree evaluates to true and set result accordingly",
1250 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax ebx ecx edx" ] },
1252 "units" => [ "GP" ],
1253 "mode" => "mode_Iu",
1258 "comment" => "construct Set: SSE Compare + int Set",
1259 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "eax ebx ecx edx" ] },
1261 "units" => [ "SSE" ],
1262 "mode" => "mode_Iu",
1267 "comment" => "construct Set: x87 Compare + int Set",
1268 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "eax ebx ecx edx" ] },
1270 "units" => [ "VFP" ],
1271 "mode" => "mode_Iu",
1276 "comment" => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
1277 "reg_req" => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] },
1279 "units" => [ "VFP" ],
1283 #----------------------------------------------------------#
1285 # (_) | | | | / _| | | | #
1286 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
1287 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
1288 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
1289 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
1291 # _ __ ___ __| | ___ ___ #
1292 # | '_ \ / _ \ / _` |/ _ \/ __| #
1293 # | | | | (_) | (_| | __/\__ \ #
1294 # |_| |_|\___/ \__,_|\___||___/ #
1295 #----------------------------------------------------------#
1299 "comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
1300 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1302 "units" => [ "VFP" ],
1308 "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1309 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1311 "units" => [ "VFP" ],
1317 "cmp_attr" => "return 1;",
1318 "comment" => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1324 "comment" => "virtual fp Sub: Sub(a, b) = a - b",
1325 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1327 "units" => [ "VFP" ],
1332 "cmp_attr" => "return 1;",
1333 "comment" => "lowered virtual fp Sub: Sub(a, b) = a - b",
1338 "comment" => "virtual fp Div: Div(a, b) = a / b",
1339 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1340 "outs" => [ "res", "M" ],
1342 "units" => [ "VFP" ],
1346 "cmp_attr" => "return 1;",
1347 "comment" => "lowered virtual fp Div: Div(a, b) = a / b",
1348 "outs" => [ "res", "M" ],
1353 "comment" => "virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1354 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1356 "units" => [ "VFP" ],
1361 "cmp_attr" => "return 1;",
1362 "comment" => "lowered virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1368 "comment" => "virtual fp Abs: Abs(a) = |a|",
1369 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1371 "units" => [ "VFP" ],
1377 "comment" => "virtual fp Chs: Chs(a) = -a",
1378 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1380 "units" => [ "VFP" ],
1386 "comment" => "virtual fp Sin: Sin(a) = sin(a)",
1387 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1389 "units" => [ "VFP" ],
1395 "comment" => "virtual fp Cos: Cos(a) = cos(a)",
1396 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1398 "units" => [ "VFP" ],
1404 "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
1405 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1407 "units" => [ "VFP" ],
1411 # virtual Load and Store
1414 "op_flags" => "L|F",
1415 "state" => "exc_pinned",
1416 "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
1417 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1418 "outs" => [ "res", "M" ],
1420 "units" => [ "VFP" ],
1424 "op_flags" => "L|F",
1425 "state" => "exc_pinned",
1426 "comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
1427 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1429 "units" => [ "VFP" ],
1436 "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1437 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1438 "outs" => [ "res", "M" ],
1440 "units" => [ "VFP" ],
1444 "cmp_attr" => "return 1;",
1445 "comment" => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1446 "outs" => [ "res", "M" ],
1451 "comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1452 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1454 "units" => [ "VFP" ],
1459 "cmp_attr" => "return 1;",
1460 "comment" => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1470 "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg",
1471 "reg_req" => { "out" => [ "vfp" ] },
1473 "units" => [ "VFP" ],
1479 "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg",
1480 "reg_req" => { "out" => [ "vfp" ] },
1482 "units" => [ "VFP" ],
1488 "comment" => "virtual fp Load pi: Ld pi -> reg",
1489 "reg_req" => { "out" => [ "vfp" ] },
1491 "units" => [ "VFP" ],
1497 "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg",
1498 "reg_req" => { "out" => [ "vfp" ] },
1500 "units" => [ "VFP" ],
1506 "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg",
1507 "reg_req" => { "out" => [ "vfp" ] },
1509 "units" => [ "VFP" ],
1515 "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg",
1516 "reg_req" => { "out" => [ "vfp" ] },
1518 "units" => [ "VFP" ],
1524 "comment" => "virtual fp Load ld e: Ld ld e -> reg",
1525 "reg_req" => { "out" => [ "vfp" ] },
1527 "units" => [ "VFP" ],
1534 # "init_attr" => " set_ia32_ls_mode(res, mode);",
1535 "comment" => "represents a virtual floating point constant",
1536 "reg_req" => { "out" => [ "vfp" ] },
1538 "units" => [ "VFP" ],
1545 "op_flags" => "L|X|Y",
1546 "comment" => "represents a virtual floating point compare",
1547 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] },
1548 "outs" => [ "false", "true", "temp_reg_eax" ],
1550 "units" => [ "VFP" ],
1553 #------------------------------------------------------------------------#
1554 # ___ _____ __ _ _ _ #
1555 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1556 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1557 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1558 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1559 #------------------------------------------------------------------------#
1563 "rd_constructor" => "NONE",
1564 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1566 "emit" => '. fadd%XM %x87_binop',
1571 "rd_constructor" => "NONE",
1572 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1574 "emit" => '. faddp %x87_binop',
1579 "rd_constructor" => "NONE",
1580 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1582 "emit" => '. fmul%XM %x87_binop',
1587 "rd_constructor" => "NONE",
1588 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1590 "emit" => '. fmulp %x87_binop',,
1595 "rd_constructor" => "NONE",
1596 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1598 "emit" => '. fsub%XM %x87_binop',
1603 "rd_constructor" => "NONE",
1604 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1606 "emit" => '. fsubp %x87_binop',
1611 "rd_constructor" => "NONE",
1613 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1615 "emit" => '. fsubr%XM %x87_binop',
1620 "rd_constructor" => "NONE",
1622 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1624 "emit" => '. fsubrp %x87_binop',
1629 "rd_constructor" => "NONE",
1630 "comment" => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1632 "emit" => '. fprem1',
1635 # this node is just here, to keep the simulator running
1636 # we can omit this when a fprem simulation function exists
1639 "rd_constructor" => "NONE",
1640 "comment" => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1642 "emit" => '. fprem1',
1647 "rd_constructor" => "NONE",
1648 "comment" => "x87 fp Div: Div(a, b) = a / b",
1650 "emit" => '. fdiv%XM %x87_binop',
1655 "rd_constructor" => "NONE",
1656 "comment" => "x87 fp Div: Div(a, b) = a / b",
1658 "emit" => '. fdivp %x87_binop',
1663 "rd_constructor" => "NONE",
1664 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1666 "emit" => '. fdivr%XM %x87_binop',
1671 "rd_constructor" => "NONE",
1672 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1674 "emit" => '. fdivrp %x87_binop',
1679 "rd_constructor" => "NONE",
1680 "comment" => "x87 fp Abs: Abs(a) = |a|",
1687 "rd_constructor" => "NONE",
1688 "comment" => "x87 fp Chs: Chs(a) = -a",
1695 "rd_constructor" => "NONE",
1696 "comment" => "x87 fp Sin: Sin(a) = sin(a)",
1703 "rd_constructor" => "NONE",
1704 "comment" => "x87 fp Cos: Cos(a) = cos(a)",
1711 "rd_constructor" => "NONE",
1712 "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1714 "emit" => '. fsqrt $',
1717 # x87 Load and Store
1720 "rd_constructor" => "NONE",
1721 "op_flags" => "R|L|F",
1722 "state" => "exc_pinned",
1723 "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1725 "emit" => '. fld%XM %AM',
1729 "rd_constructor" => "NONE",
1730 "op_flags" => "R|L|F",
1731 "state" => "exc_pinned",
1732 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1734 "emit" => '. fst%XM %AM',
1739 "rd_constructor" => "NONE",
1740 "op_flags" => "R|L|F",
1741 "state" => "exc_pinned",
1742 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1744 "emit" => '. fstp%XM %AM',
1752 "rd_constructor" => "NONE",
1753 "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1755 "emit" => '. fild%XM %AM',
1760 "rd_constructor" => "NONE",
1761 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1763 "emit" => '. fist%M %AM',
1769 "rd_constructor" => "NONE",
1770 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1772 "emit" => '. fistp%M %AM',
1779 "op_flags" => "R|c",
1781 "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
1782 "reg_req" => { "out" => [ "vfp" ] },
1787 "op_flags" => "R|c",
1789 "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
1790 "reg_req" => { "out" => [ "vfp" ] },
1795 "op_flags" => "R|c",
1797 "comment" => "x87 fp Load pi: Ld pi -> reg",
1798 "reg_req" => { "out" => [ "vfp" ] },
1799 "emit" => '. fldpi',
1803 "op_flags" => "R|c",
1805 "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
1806 "reg_req" => { "out" => [ "vfp" ] },
1807 "emit" => '. fldln2',
1811 "op_flags" => "R|c",
1813 "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
1814 "reg_req" => { "out" => [ "vfp" ] },
1815 "emit" => '. fldlg2',
1819 "op_flags" => "R|c",
1821 "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
1822 "reg_req" => { "out" => [ "vfp" ] },
1823 "emit" => '. fldll2t',
1827 "op_flags" => "R|c",
1829 "comment" => "x87 fp Load ld e: Ld ld e -> reg",
1830 "reg_req" => { "out" => [ "vfp" ] },
1831 "emit" => '. fldl2e',
1835 "op_flags" => "R|c",
1837 "rd_constructor" => "NONE",
1838 "comment" => "represents a x87 constant",
1839 "reg_req" => { "out" => [ "vfp" ] },
1840 "emit" => '. fld $%C',
1844 # Note that it is NEVER allowed to do CSE on these nodes
1845 # Moreover, note the virtual register requierements!
1848 "op_flags" => "R|K",
1849 "comment" => "x87 stack exchange",
1851 "cmp_attr" => "return 1;",
1852 "emit" => '. fxch %X1',
1856 "op_flags" => "R|K",
1857 "comment" => "x87 stack push",
1859 "cmp_attr" => "return 1;",
1860 "emit" => '. fld %X1',
1865 "comment" => "x87 stack push",
1866 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1867 "cmp_attr" => "return 1;",
1868 "emit" => '. fld %X1',
1872 "op_flags" => "R|K",
1873 "comment" => "x87 stack pop",
1875 "cmp_attr" => "return 1;",
1876 "emit" => '. fstp %X1',
1882 "op_flags" => "L|X|Y",
1883 "comment" => "floating point compare",
1888 "op_flags" => "L|X|Y",
1889 "comment" => "floating point compare and pop",
1894 "op_flags" => "L|X|Y",
1895 "comment" => "floating point compare and pop twice",
1900 "op_flags" => "L|X|Y",
1901 "comment" => "floating point compare reverse",
1906 "op_flags" => "L|X|Y",
1907 "comment" => "floating point compare reverse and pop",
1912 "op_flags" => "L|X|Y",
1913 "comment" => "floating point compare reverse and pop twice",