3 # This is the specification for the ia32 assembler Firm-operations
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
8 # this strings mark the beginning and the end of a comment in emit
9 $comment_string = "/*";
10 $comment_string_end = "*/";
12 # the number of additional opcodes you want to register
13 #$additional_opcodes = 0;
15 # The node description is done as a perl hash initializer with the
16 # following structure:
21 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
22 # "irn_flags" => "R|N|I|S"
23 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
24 # "state" => "floats|pinned|mem_pinned|exc_pinned",
26 # { "type" => "type 1", "name" => "name 1" },
27 # { "type" => "type 2", "name" => "name 2" },
30 # "comment" => "any comment for constructor",
31 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
32 # "cmp_attr" => "c source code for comparing node attributes",
33 # "emit" => "emit code with templates",
34 # "attr" => "attitional attribute arguments for constructor"
35 # "init_attr" => "emit attribute initialization template"
36 # "rd_constructor" => "c source code which constructs an ir_node"
37 # "latency" => "latency of this operation (can be float)"
40 # ... # (all nodes you need to describe)
42 # ); # close the %nodes initializer
44 # op_flags: flags for the operation, OPTIONAL (default is "N")
45 # the op_flags correspond to the firm irop_flags:
48 # C irop_flag_commutative
49 # X irop_flag_cfopcode
50 # I irop_flag_ip_cfopcode
53 # H irop_flag_highlevel
54 # c irop_flag_constlike
57 # irn_flags: special node flags, OPTIONAL (default is 0)
58 # following irn_flags are supported:
61 # I ignore for register allocation
62 # S modifies stack pointer
64 # state: state of the operation, OPTIONAL (default is "floats")
66 # arity: arity of the operation, MUST NOT BE OMITTED
68 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
69 # are always the first 3 arguments and are always autmatically
71 # If this key is missing the following arguments will be created:
72 # for i = 1 .. arity: ir_node *op_i
75 # outs: if a node defines more than one output, the names of the projections
76 # nodes having outs having automatically the mode mode_T
77 # One can also annotate some flags for each out, additional to irn_flags.
78 # They are separated from name with a colon ':', and concatenated by pipe '|'
79 # Only I and S are available at the moment (same meaning as in irn_flags).
80 # example: [ "frame:I", "stack:I|S", "M" ]
82 # comment: OPTIONAL comment for the node constructor
84 # rd_constructor: for every operation there will be a
85 # new_rd_<arch>_<op-name> function with the arguments from above
86 # which creates the ir_node corresponding to the defined operation
87 # you can either put the complete source code of this function here
89 # This key is OPTIONAL. If omitted, the following constructor will
91 # if (!op_<arch>_<op-name>) assert(0);
95 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
98 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
100 # latency: the latency of the operation, default is 1
104 # 0 - no special type
105 # 1 - caller save (register must be saved by the caller of a function)
106 # 2 - callee save (register must be saved by the called function)
107 # 4 - ignore (do not assign this register)
108 # 8 - emitter can choose an arbitrary register of this class
109 # 16 - the register is a virtual one
110 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
113 { "name" => "eax", "type" => 1 },
114 { "name" => "edx", "type" => 1 },
115 { "name" => "ebx", "type" => 2 },
116 { "name" => "ecx", "type" => 1 },
117 { "name" => "esi", "type" => 2 },
118 { "name" => "edi", "type" => 2 },
119 { "name" => "ebp", "type" => 2 },
120 { "name" => "esp", "type" => 4 },
121 { "name" => "gp_NOREG", "type" => 4 | 16 }, # we need a dummy register for NoReg nodes
122 { "name" => "gp_UKNWN", "type" => 4 | 8 | 16}, # we need a dummy register for Unknown nodes
123 { "mode" => "mode_Iu" }
126 { "name" => "xmm0", "type" => 1 },
127 { "name" => "xmm1", "type" => 1 },
128 { "name" => "xmm2", "type" => 1 },
129 { "name" => "xmm3", "type" => 1 },
130 { "name" => "xmm4", "type" => 1 },
131 { "name" => "xmm5", "type" => 1 },
132 { "name" => "xmm6", "type" => 1 },
133 { "name" => "xmm7", "type" => 1 },
134 { "name" => "xmm_NOREG", "type" => 4 | 16 }, # we need a dummy register for NoReg nodes
135 { "name" => "xmm_UKNWN", "type" => 4 | 8 | 16}, # we need a dummy register for Unknown nodes
136 { "mode" => "mode_D" }
139 { "name" => "vf0", "type" => 1 | 16 },
140 { "name" => "vf1", "type" => 1 | 16 },
141 { "name" => "vf2", "type" => 1 | 16 },
142 { "name" => "vf3", "type" => 1 | 16 },
143 { "name" => "vf4", "type" => 1 | 16 },
144 { "name" => "vf5", "type" => 1 | 16 },
145 { "name" => "vf6", "type" => 1 | 16 },
146 { "name" => "vf7", "type" => 1 | 16 },
147 { "name" => "vfp_NOREG", "type" => 4 | 16 }, # we need a dummy register for NoReg nodes
148 { "name" => "vfp_UKNWN", "type" => 4 | 8 | 16}, # we need a dummy register for Unknown nodes
149 { "mode" => "mode_D" }
152 { "name" => "st0", "type" => 1 },
153 { "name" => "st1", "type" => 1 },
154 { "name" => "st2", "type" => 1 },
155 { "name" => "st3", "type" => 1 },
156 { "name" => "st4", "type" => 1 },
157 { "name" => "st5", "type" => 1 },
158 { "name" => "st6", "type" => 1 },
159 { "name" => "st7", "type" => 1 },
160 { "mode" => "mode_E" }
162 "fp_cw" => [ # the floating point control word
163 { "name" => "fpcw", "type" => 0 },
164 { "mode" => "mode_Hu" },
169 "ALU" => [ 1, "ALU1", "ALU2", "ALU3", "ALU4" ],
170 "MUL" => [ 1, "MUL1", "MUL2" ],
171 "SSE" => [ 1, "SSE1", "SSE2" ],
172 "FPU" => [ 1, "FPU1" ],
173 "MEM" => [ 1, "MEM1", "MEM2" ],
174 "BRANCH" => [ 1, "BRANCH1", "BRANCH2" ],
175 "DUMMY" => [ 1, "DUMMY1", "DUMMY2", "DUMMY3", "DUMMY4" ]
180 "bundels_per_cycle" => 2
183 #--------------------------------------------------#
186 # _ __ _____ __ _ _ __ ___ _ __ ___ #
187 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
188 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
189 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
192 #--------------------------------------------------#
194 $default_cmp_attr = "return ia32_compare_attr(attr_a, attr_b);";
201 #-----------------------------------------------------------------#
204 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
205 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
206 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
207 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
210 #-----------------------------------------------------------------#
212 # commutative operations
215 # All nodes supporting Addressmode have 5 INs:
216 # 1 - base r1 == NoReg in case of no AM or no base
217 # 2 - index r2 == NoReg in case of no AM or no index
218 # 3 - op1 r3 == always present
219 # 4 - op2 r4 == NoReg in case of immediate operation
220 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
224 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
225 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
226 "emit" => '. add %ia32_emit_binop /* Add(%A3, %A4) -> %D1 */',
227 "units" => [ "ALU", "MEM" ],
232 "comment" => "construct Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
233 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
234 "emit" => '. adc %ia32_emit_binop /* AddC(%A3, %A4) -> %D1 */',
235 "units" => [ "ALU", "MEM" ],
241 "comment" => "construct 64Bit Add: Add(a_l, a_h, b_l, b_h) = a_l + b_l; a_h + b_h + carry",
243 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
245 . mov %D1, %S1 /* mov a_l into assigned l_res register */
246 . mov %D2, %S2 /* mov a_h into assigned h_res register */
247 . add %D1, %S3 /* a_l + b_l */
248 . adc %D2, %S4 /* a_h + b_h + carry */
250 "outs" => [ "low_res", "high_res" ],
251 "units" => [ "ALU", "MEM" ],
257 "cmp_attr" => "return 1;",
258 "comment" => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
264 "cmp_attr" => "return 1;",
265 "comment" => "construct lowered Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
270 # we should not rematrialize this node. It produces 2 results and has
271 # very strict constrains
272 "comment" => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
273 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx", "none" ] },
274 "emit" => '. mul %ia32_emit_unop /* Mul(%A1, %A2) -> %D1 */',
275 "outs" => [ "EAX", "EDX", "M" ],
277 "units" => [ "MUL" ],
281 # we should not rematrialize this node. It produces 2 results and has
282 # very strict constrains
284 "cmp_attr" => "return 1;",
285 "comment" => "construct lowered MulS: MulS(a, b) = MulS(b, a) = a * b",
286 "outs" => [ "EAX", "EDX", "M" ],
292 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
293 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
294 "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */',
296 "units" => [ "MUL" ],
302 "cmp_attr" => "return 1;",
303 "comment" => "construct lowered Mul: Mul(a, b) = Mul(b, a) = a * b",
307 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
309 # we should not rematrialize this node. It produces 2 results and has
310 # very strict constrains
311 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
312 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] },
313 "emit" => '. imul %ia32_emit_unop /* Mulh(%A1, %A2) -> %D1 */',
314 "outs" => [ "EAX", "EDX", "M" ],
316 "units" => [ "MUL" ],
321 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
322 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
323 "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */',
324 "units" => [ "ALU" ],
330 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
331 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
332 "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */',
333 "units" => [ "ALU" ],
339 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
340 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
341 "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */',
342 "units" => [ "ALU" ],
348 "cmp_attr" => "return 1;",
349 "comment" => "construct lowered Eor: Eor(a, b) = Eor(b, a) = a EOR b",
353 # not commutative operations
357 "comment" => "construct Sub: Sub(a, b) = a - b",
358 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
359 "emit" => '. sub %ia32_emit_binop /* Sub(%A3, %A4) -> %D1 */',
360 "units" => [ "ALU" ],
365 "comment" => "construct Sub with Carry: SubC(a, b) = a - b - carry",
366 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3 !in_r4" ] },
367 "emit" => '. sbb %ia32_emit_binop /* SubC(%A3, %A4) -> %D1 */',
368 "units" => [ "ALU" ],
374 "comment" => "construct 64Bit Sub: Sub(a_l, a_h, b_l, b_h) = a_l - b_l; a_h - b_h - borrow",
376 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
378 . mov %D1, %S1 /* mov a_l into assigned l_res register */
379 . mov %D2, %S2 /* mov a_h into assigned h_res register */
380 . sub %D1, %S3 /* a_l - b_l */
381 . sbb %D2, %S4 /* a_h - b_h - borrow */
383 "outs" => [ "low_res", "high_res" ],
384 "units" => [ "ALU" ],
389 "cmp_attr" => "return 1;",
390 "comment" => "construct lowered Sub: Sub(a, b) = a - b",
395 "cmp_attr" => "return 1;",
396 "comment" => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
402 "state" => "exc_pinned",
403 "reg_req" => { "in" => [ "eax", "gp", "edx", "none" ], "out" => [ "eax", "edx" ] },
404 "attr" => "ia32_op_flavour_t dm_flav",
405 "init_attr" => "attr->data.op_flav = dm_flav;",
406 "emit" => ". idiv %S2 /* signed IDiv(%S1, %S2) -> %D1, (%A1, %A2, %A3) */",
407 "outs" => [ "div_res", "mod_res", "M" ],
409 "units" => [ "ALU" ],
414 "state" => "exc_pinned",
415 "reg_req" => { "in" => [ "eax", "gp", "edx", "none" ], "out" => [ "eax", "edx" ] },
416 "attr" => "ia32_op_flavour_t dm_flav",
417 "init_attr" => "attr->data.op_flav = dm_flav;",
418 "emit" => ". div %S2 /* unsigned Div(%S1, %S2) -> %D1, (%A1, %A2, %A3) */",
419 "outs" => [ "div_res", "mod_res", "M" ],
421 "units" => [ "ALU" ],
426 "comment" => "construct Shl: Shl(a, b) = a << b",
427 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
428 "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */',
429 "units" => [ "ALU1", "SSE1" ],
434 "cmp_attr" => "return 1;",
435 "comment" => "construct lowered Shl: Shl(a, b) = a << b",
441 "comment" => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
442 # Out requirements is: different from all in
443 # This is because, out must be different from LowPart and ShiftCount.
444 # We could say "!ecx !in_r4" but it can occur, that all values live through
445 # this Shift and the only value dying is the ShiftCount. Then there would be a
446 # register missing, as result must not be ecx and all other registers are
447 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
448 # (and probably never will). So we create artificial interferences of the result
449 # with all inputs, so the spiller can always assure a free register.
450 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!in" ] },
453 if (get_ia32_immop_type(n) == ia32_ImmNone) {
454 if (get_ia32_op_type(n) == ia32_AddrModeD) {
455 4. shld %ia32_emit_am, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
458 4. shld %S3, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
462 if (get_ia32_op_type(n) == ia32_AddrModeD) {
463 4. shld %ia32_emit_am, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
466 4. shld %S3, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
471 "units" => [ "ALU1", "SSE1" ],
476 "cmp_attr" => "return 1;",
477 "comment" => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
483 "comment" => "construct Shr: Shr(a, b) = a >> b",
484 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
485 "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */',
486 "units" => [ "ALU1", "SSE1" ],
491 "cmp_attr" => "return 1;",
492 "comment" => "construct lowered Shr: Shr(a, b) = a << b",
498 "comment" => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
499 # Out requirements is: different from all in
500 # This is because, out must be different from LowPart and ShiftCount.
501 # We could say "!ecx !in_r4" but it can occur, that all values live through
502 # this Shift and the only value dying is the ShiftCount. Then there would be a
503 # register missing, as result must not be ecx and all other registers are
504 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
505 # (and probably never will). So we create artificial interferences of the result
506 # with all inputs, so the spiller can always assure a free register.
507 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!in" ] },
510 if (get_ia32_immop_type(n) == ia32_ImmNone) {
511 if (get_ia32_op_type(n) == ia32_AddrModeD) {
512 4. shrd %ia32_emit_am, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
515 4. shrd %S3, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
519 if (get_ia32_op_type(n) == ia32_AddrModeD) {
520 4. shrd %ia32_emit_am, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
523 4. shrd %S3, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
528 "units" => [ "ALU1", "SSE1" ],
533 "cmp_attr" => "return 1;",
534 "comment" => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
540 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
541 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
542 "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */',
543 "units" => [ "ALU1", "SSE1" ],
548 "cmp_attr" => "return 1;",
549 "comment" => "construct lowered Shrs: Shrs(a, b) = a << b",
555 "comment" => "construct RotR: RotR(a, b) = a ROTR b",
556 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
557 "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */',
558 "units" => [ "ALU1", "SSE1" ],
564 "comment" => "construct RotL: RotL(a, b) = a ROTL b",
565 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
566 "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */',
567 "units" => [ "ALU1", "SSE1" ],
575 "comment" => "construct Minus: Minus(a) = -a",
576 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
577 "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */',
578 "units" => [ "ALU" ],
584 "comment" => "construct 64Bit Minus: Minus(a_l, a_h, 0) = 0 - a_l; 0 - a_h - borrow",
586 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
588 . mov %D1, %S1 /* l_res */
589 . mov %D2, %S1 /* h_res */
590 . sub %D1, %S2 /* 0 - a_l -> low_res */
591 . sbb %D2, %S3 /* 0 - a_h - borrow -> high_res */
593 "outs" => [ "low_res", "high_res" ],
594 "units" => [ "ALU" ],
599 "cmp_attr" => "return 1;",
600 "comment" => "construct lowered Minus: Minus(a) = -a",
606 "comment" => "construct Increment: Inc(a) = a++",
607 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
608 "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */',
609 "units" => [ "ALU" ],
615 "comment" => "construct Decrement: Dec(a) = a--",
616 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
617 "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */',
618 "units" => [ "ALU" ],
624 "comment" => "construct Not: Not(a) = !a",
625 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
626 "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */',
627 "units" => [ "ALU" ],
634 "op_flags" => "L|X|Y",
635 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
636 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
637 "outs" => [ "false", "true" ],
639 "units" => [ "BRANCH" ],
643 "op_flags" => "L|X|Y",
644 "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
645 "reg_req" => { "in" => [ "gp", "gp" ] },
646 "outs" => [ "false", "true" ],
648 "units" => [ "BRANCH" ],
652 "op_flags" => "L|X|Y",
653 "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
654 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
655 "outs" => [ "false", "true" ],
656 "units" => [ "BRANCH" ],
660 "op_flags" => "L|X|Y",
661 "comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
662 "reg_req" => { "in" => [ "gp", "gp" ] },
663 "units" => [ "BRANCH" ],
667 "op_flags" => "L|X|Y",
668 "comment" => "construct switch",
669 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
671 "units" => [ "BRANCH" ],
677 "comment" => "represents an integer constant",
678 "reg_req" => { "out" => [ "gp" ] },
679 "units" => [ "ALU" ],
686 "comment" => "unknown value",
687 "reg_req" => { "out" => [ "gp_UKNWN" ] },
696 "comment" => "unknown value",
697 "reg_req" => { "out" => [ "vfp_UKNWN" ] },
706 "comment" => "unknown value",
707 "reg_req" => { "out" => [ "xmm_UKNWN" ] },
716 "comment" => "unknown GP value",
717 "reg_req" => { "out" => [ "gp_NOREG" ] },
726 "comment" => "unknown VFP value",
727 "reg_req" => { "out" => [ "vfp_NOREG" ] },
736 "comment" => "unknown XMM value",
737 "reg_req" => { "out" => [ "xmm_NOREG" ] },
745 "comment" => "change floating point control word",
746 "reg_req" => { "out" => [ "fp_cw" ] },
749 "units" => [ "ALU" ],
754 "state" => "exc_pinned",
755 "comment" => "load floating point control word FldCW(ptr, mem) = LD ptr -> reg",
756 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "fp_cw" ] },
758 "emit" => ". fldcw %ia32_emit_am /* FldCW(%A1) -> %D1 */",
760 "units" => [ "MEM" ],
765 "state" => "exc_pinned",
766 "comment" => "store floating point control word: FstCW(ptr, mem) = ST ptr -> reg",
767 "reg_req" => { "in" => [ "gp", "gp", "fp_cw", "none" ] },
769 "emit" => ". fstcw %ia32_emit_am /* FstCW(%A3) -> %A1 */",
771 "units" => [ "MEM" ],
775 # we should not rematrialize this node. It produces 2 results and has
776 # very strict constrains
777 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
778 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
779 "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */',
780 "outs" => [ "EAX", "EDX" ],
781 "units" => [ "ALU" ],
788 "state" => "exc_pinned",
789 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
790 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp", "none" ] },
793 ' if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) {
794 4. mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
797 4. mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
800 "outs" => [ "res", "M" ],
801 "units" => [ "MEM" ],
806 "cmp_attr" => "return 1;",
807 "comment" => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg",
808 "outs" => [ "res", "M" ],
814 "cmp_attr" => "return 1;",
815 "state" => "exc_pinned",
816 "comment" => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val",
823 "state" => "exc_pinned",
824 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
825 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
826 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
828 "units" => [ "MEM" ],
834 "state" => "exc_pinned",
835 "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
836 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
837 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
839 "units" => [ "MEM" ],
845 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
846 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
847 "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */',
849 "units" => [ "ALU" ],
854 "comment" => "push on the stack",
855 "reg_req" => { "in" => [ "gp", "gp", "gp", "esp", "none" ], "out" => [ "esp" ] },
856 "emit" => '. push %ia32_emit_unop /* PUSH(%A1) */',
857 "outs" => [ "stack:I|S", "M" ],
859 "units" => [ "MEM" ],
863 "comment" => "pop a gp register from the stack",
864 "reg_req" => { "in" => [ "gp", "gp", "esp", "none" ], "out" => [ "esp", "gp" ] },
865 "emit" => '. pop %ia32_emit_unop /* POP(%A1) */',
866 "outs" => [ "stack:I|S", "res", "M" ],
868 "units" => [ "MEM" ],
872 "comment" => "create stack frame",
873 "reg_req" => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] },
874 "emit" => '. enter /* Enter */',
875 "outs" => [ "frame:I", "stack:I|S", "M" ],
877 "units" => [ "MEM" ],
881 "comment" => "destroy stack frame",
882 "reg_req" => { "in" => [ "esp", "ebp" ], "out" => [ "ebp", "esp" ] },
883 "emit" => '. leave /* Leave */',
884 "outs" => [ "frame:I", "stack:I|S" ],
886 "units" => [ "MEM" ],
891 "comment" => "allocate space on stack",
892 "reg_req" => { "in" => [ "esp", "gp" ], "out" => [ "esp", "none" ] },
893 "outs" => [ "stack:S", "M" ],
894 "units" => [ "ALU" ],
899 "comment" => "free space on stack",
900 "reg_req" => { "in" => [ "esp", "gp" ], "out" => [ "esp", "none" ] },
901 "outs" => [ "stack:S", "M" ],
902 "units" => [ "ALU" ],
907 "comment" => "get the TLS base address",
908 "reg_req" => { "out" => [ "gp" ] },
909 "units" => [ "MEM" ],
914 #-----------------------------------------------------------------------------#
915 # _____ _____ ______ __ _ _ _ #
916 # / ____/ ____| ____| / _| | | | | | #
917 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
918 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
919 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
920 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
921 #-----------------------------------------------------------------------------#
923 # commutative operations
927 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
928 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
929 "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */',
931 "units" => [ "SSE" ],
937 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
938 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
939 "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */',
941 "units" => [ "SSE" ],
947 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
948 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
949 "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */',
951 "units" => [ "SSE" ],
957 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
958 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
959 "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */',
961 "units" => [ "SSE" ],
967 "comment" => "construct SSE And: And(a, b) = a AND b",
968 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
969 "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */',
971 "units" => [ "SSE" ],
977 "comment" => "construct SSE Or: Or(a, b) = a OR b",
978 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
979 "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */',
980 "units" => [ "SSE" ],
986 "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
987 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
988 "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */',
990 "units" => [ "SSE" ],
994 # not commutative operations
998 "comment" => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
999 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
1000 "emit" => '. andnp%M %ia32_emit_binop /* SSE AndNot(%A3, %A4) -> %D1 */',
1002 "units" => [ "SSE" ],
1008 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
1009 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
1010 "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */',
1012 "units" => [ "SSE" ],
1018 "comment" => "construct SSE Div: Div(a, b) = a / b",
1019 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
1020 "outs" => [ "res", "M" ],
1021 "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */',
1023 "units" => [ "SSE" ],
1030 "comment" => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
1031 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
1033 "units" => [ "SSE" ],
1038 "op_flags" => "L|X|Y",
1039 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
1040 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
1041 "outs" => [ "false", "true" ],
1043 "units" => [ "SSE" ],
1049 "comment" => "represents a SSE constant",
1050 "reg_req" => { "out" => [ "xmm" ] },
1051 "emit" => '. movs%M %D1, %C /* Load fConst into register */',
1053 "units" => [ "SSE" ],
1060 "op_flags" => "L|F",
1061 "state" => "exc_pinned",
1062 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
1063 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
1064 "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */',
1065 "outs" => [ "res", "M" ],
1067 "units" => [ "SSE" ],
1071 "op_flags" => "L|F",
1072 "state" => "exc_pinned",
1073 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
1074 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
1075 "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */',
1077 "units" => [ "MEM" ],
1082 "op_flags" => "L|F",
1083 "state" => "exc_pinned",
1084 "comment" => "construct Store without index: Store(ptr, val, mem) = ST ptr,val",
1085 "reg_req" => { "in" => [ "gp", "xmm", "none" ] },
1086 "emit" => '. movs%M %ia32_emit_am, %S2 /* store XMM0 onto stack */',
1088 "units" => [ "MEM" ],
1093 "op_flags" => "L|F",
1094 "comment" => "construct: transfer a value from x87 FPU into a SSE register",
1095 "cmp_attr" => "return 1;",
1100 "op_flags" => "L|F",
1101 "comment" => "construct: transfer a value from SSE register to x87 FPU",
1102 "cmp_attr" => "return 1;",
1107 "op_flags" => "L|F",
1109 "state" => "exc_pinned",
1110 "comment" => "store ST0 onto stack",
1111 "reg_req" => { "in" => [ "gp", "gp", "none" ] },
1112 "emit" => '. fstp %ia32_emit_am /* store ST0 onto stack */',
1114 "units" => [ "MEM" ],
1119 "op_flags" => "L|F",
1121 "state" => "exc_pinned",
1122 "comment" => "load ST0 from stack",
1123 "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "vf0", "none" ] },
1124 "emit" => '. fld %ia32_emit_am /* load ST0 from stack */',
1125 "outs" => [ "res", "M" ],
1127 "units" => [ "MEM" ],
1133 "op_flags" => "F|H",
1134 "state" => "pinned",
1135 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
1136 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "edi", "esi", "ecx", "none" ] },
1137 "outs" => [ "DST", "SRC", "CNT", "M" ],
1138 "units" => [ "MEM" ],
1142 "op_flags" => "F|H",
1143 "state" => "pinned",
1144 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
1145 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "edi", "esi", "none" ] },
1146 "outs" => [ "DST", "SRC", "M" ],
1147 "units" => [ "MEM" ],
1153 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
1154 "comment" => "construct Conv Int -> Int",
1155 "units" => [ "ALU" ],
1156 "mode" => "mode_Iu",
1160 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
1161 "comment" => "construct Conv Int -> Int",
1162 "units" => [ "ALU" ],
1163 "mode" => "mode_Iu",
1167 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
1168 "comment" => "construct Conv Int -> Floating Point",
1170 "units" => [ "SSE" ],
1175 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
1176 "comment" => "construct Conv Floating Point -> Int",
1178 "units" => [ "SSE" ],
1179 "mode" => "mode_Iu",
1183 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
1184 "comment" => "construct Conv Floating Point -> Floating Point",
1186 "units" => [ "SSE" ],
1192 "comment" => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
1193 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "in_r4" ] },
1195 "units" => [ "ALU" ],
1196 "mode" => "mode_Iu",
1201 "comment" => "check if Psi condition tree evaluates to true and move result accordingly",
1202 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r3" ] },
1204 "units" => [ "ALU" ],
1205 "mode" => "mode_Iu",
1210 "comment" => "construct Conditional Move: SSE Compare + int CMov ",
1211 "reg_req" => { "in" => [ "xmm", "xmm", "gp", "gp" ], "out" => [ "in_r4" ] },
1213 "units" => [ "SSE" ],
1214 "mode" => "mode_Iu",
1219 "comment" => "construct Conditional Move: x87 Compare + int CMov",
1220 "reg_req" => { "in" => [ "vfp", "vfp", "gp", "gp" ], "out" => [ "in_r4" ] },
1222 "units" => [ "FPU" ],
1223 "mode" => "mode_Iu",
1228 "comment" => "construct Set: Set(sel) == sel ? 1 : 0",
1229 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax ebx ecx edx" ] },
1231 "units" => [ "ALU" ],
1232 "mode" => "mode_Iu",
1237 "comment" => "check if Psi condition tree evaluates to true and set result accordingly",
1238 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax ebx ecx edx" ] },
1240 "units" => [ "ALU" ],
1241 "mode" => "mode_Iu",
1246 "comment" => "construct Set: SSE Compare + int Set",
1247 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "eax ebx ecx edx" ] },
1249 "units" => [ "SSE" ],
1250 "mode" => "mode_Iu",
1255 "comment" => "construct Set: x87 Compare + int Set",
1256 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "eax ebx ecx edx" ] },
1258 "units" => [ "FPU" ],
1259 "mode" => "mode_Iu",
1264 "comment" => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
1265 "reg_req" => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] },
1267 "units" => [ "FPU" ],
1271 #----------------------------------------------------------#
1273 # (_) | | | | / _| | | | #
1274 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
1275 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
1276 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
1277 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
1279 # _ __ ___ __| | ___ ___ #
1280 # | '_ \ / _ \ / _` |/ _ \/ __| #
1281 # | | | | (_) | (_| | __/\__ \ #
1282 # |_| |_|\___/ \__,_|\___||___/ #
1283 #----------------------------------------------------------#
1287 "comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
1288 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1290 "units" => [ "FPU" ],
1296 "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1297 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1299 "units" => [ "FPU" ],
1305 "cmp_attr" => "return 1;",
1306 "comment" => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1312 "comment" => "virtual fp Sub: Sub(a, b) = a - b",
1313 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1315 "units" => [ "FPU" ],
1320 "cmp_attr" => "return 1;",
1321 "comment" => "lowered virtual fp Sub: Sub(a, b) = a - b",
1326 "comment" => "virtual fp Div: Div(a, b) = a / b",
1327 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1328 "outs" => [ "res", "M" ],
1330 "units" => [ "FPU" ],
1334 "cmp_attr" => "return 1;",
1335 "comment" => "lowered virtual fp Div: Div(a, b) = a / b",
1336 "outs" => [ "res", "M" ],
1341 "comment" => "virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1342 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1344 "units" => [ "FPU" ],
1349 "cmp_attr" => "return 1;",
1350 "comment" => "lowered virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1356 "comment" => "virtual fp Abs: Abs(a) = |a|",
1357 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1359 "units" => [ "FPU" ],
1365 "comment" => "virtual fp Chs: Chs(a) = -a",
1366 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1368 "units" => [ "FPU" ],
1374 "comment" => "virtual fp Sin: Sin(a) = sin(a)",
1375 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1377 "units" => [ "FPU" ],
1383 "comment" => "virtual fp Cos: Cos(a) = cos(a)",
1384 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1386 "units" => [ "FPU" ],
1392 "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
1393 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1395 "units" => [ "FPU" ],
1399 # virtual Load and Store
1402 "op_flags" => "L|F",
1403 "state" => "exc_pinned",
1404 "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
1405 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1406 "outs" => [ "res", "M" ],
1408 "units" => [ "FPU" ],
1412 "op_flags" => "L|F",
1413 "state" => "exc_pinned",
1414 "comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
1415 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1417 "units" => [ "FPU" ],
1424 "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1425 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1426 "outs" => [ "res", "M" ],
1428 "units" => [ "FPU" ],
1432 "cmp_attr" => "return 1;",
1433 "comment" => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1434 "outs" => [ "res", "M" ],
1439 "comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1440 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1442 "units" => [ "FPU" ],
1447 "cmp_attr" => "return 1;",
1448 "comment" => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1458 "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg",
1459 "reg_req" => { "out" => [ "vfp" ] },
1461 "units" => [ "FPU" ],
1467 "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg",
1468 "reg_req" => { "out" => [ "vfp" ] },
1470 "units" => [ "FPU" ],
1476 "comment" => "virtual fp Load pi: Ld pi -> reg",
1477 "reg_req" => { "out" => [ "vfp" ] },
1479 "units" => [ "FPU" ],
1485 "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg",
1486 "reg_req" => { "out" => [ "vfp" ] },
1488 "units" => [ "FPU" ],
1494 "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg",
1495 "reg_req" => { "out" => [ "vfp" ] },
1497 "units" => [ "FPU" ],
1503 "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg",
1504 "reg_req" => { "out" => [ "vfp" ] },
1506 "units" => [ "FPU" ],
1512 "comment" => "virtual fp Load ld e: Ld ld e -> reg",
1513 "reg_req" => { "out" => [ "vfp" ] },
1515 "units" => [ "FPU" ],
1522 # "init_attr" => " set_ia32_ls_mode(res, mode);",
1523 "comment" => "represents a virtual floating point constant",
1524 "reg_req" => { "out" => [ "vfp" ] },
1526 "units" => [ "FPU" ],
1533 "op_flags" => "L|X|Y",
1534 "comment" => "represents a virtual floating point compare",
1535 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] },
1536 "outs" => [ "false", "true", "temp_reg_eax" ],
1538 "units" => [ "FPU" ],
1541 #------------------------------------------------------------------------#
1542 # ___ _____ __ _ _ _ #
1543 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1544 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1545 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1546 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1547 #------------------------------------------------------------------------#
1551 "rd_constructor" => "NONE",
1552 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1554 "emit" => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A3, %A4) -> %D1 */',
1559 "rd_constructor" => "NONE",
1560 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1562 "emit" => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A3, %A4) -> %D1 */',
1567 "rd_constructor" => "NONE",
1568 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1570 "emit" => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A3, %A4) -> %D1 */',
1575 "rd_constructor" => "NONE",
1576 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1578 "emit" => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A3, %A4) -> %D1 */',,
1583 "rd_constructor" => "NONE",
1584 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1586 "emit" => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A3, %A4) -> %D1 */',
1591 "rd_constructor" => "NONE",
1592 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1594 "emit" => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A3, %A4) -> %D1 */',
1599 "rd_constructor" => "NONE",
1601 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1603 "emit" => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A3, %A4) -> %D1 */',
1608 "rd_constructor" => "NONE",
1610 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1612 "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A3, %A4) -> %D1 */',
1617 "rd_constructor" => "NONE",
1618 "comment" => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1620 "emit" => '. fprem1 /* x87 fprem(%A3, %A4) -> %D1 */',
1623 # this node is just here, to keep the simulator running
1624 # we can omit this when a fprem simulation function exists
1627 "rd_constructor" => "NONE",
1628 "comment" => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1630 "emit" => '. fprem1 /* x87 fprem(%A3, %A4) -> %D1 WITH POP */',
1635 "rd_constructor" => "NONE",
1636 "comment" => "x87 fp Div: Div(a, b) = a / b",
1638 "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A3, %A4) -> %D1 */',
1643 "rd_constructor" => "NONE",
1644 "comment" => "x87 fp Div: Div(a, b) = a / b",
1646 "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A3, %A4) -> %D1 */',
1651 "rd_constructor" => "NONE",
1652 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1654 "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A3, %A4) -> %D1 */',
1659 "rd_constructor" => "NONE",
1660 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1662 "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A3, %A4) -> %D1 */',
1667 "rd_constructor" => "NONE",
1668 "comment" => "x87 fp Abs: Abs(a) = |a|",
1670 "emit" => '. fabs /* x87 fabs(%A1) -> %D1 */',
1675 "rd_constructor" => "NONE",
1676 "comment" => "x87 fp Chs: Chs(a) = -a",
1678 "emit" => '. fchs /* x87 fchs(%A1) -> %D1 */',
1683 "rd_constructor" => "NONE",
1684 "comment" => "x87 fp Sin: Sin(a) = sin(a)",
1686 "emit" => '. fsin /* x87 sin(%A1) -> %D1 */',
1691 "rd_constructor" => "NONE",
1692 "comment" => "x87 fp Cos: Cos(a) = cos(a)",
1694 "emit" => '. fcos /* x87 cos(%A1) -> %D1 */',
1699 "rd_constructor" => "NONE",
1700 "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1702 "emit" => '. fsqrt $ /* x87 sqrt(%A1) -> %D1 */',
1705 # x87 Load and Store
1708 "rd_constructor" => "NONE",
1709 "op_flags" => "R|L|F",
1710 "state" => "exc_pinned",
1711 "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1713 "emit" => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */',
1717 "rd_constructor" => "NONE",
1718 "op_flags" => "R|L|F",
1719 "state" => "exc_pinned",
1720 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1722 "emit" => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */',
1727 "rd_constructor" => "NONE",
1728 "op_flags" => "R|L|F",
1729 "state" => "exc_pinned",
1730 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1732 "emit" => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */',
1740 "rd_constructor" => "NONE",
1741 "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1743 "emit" => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */',
1748 "rd_constructor" => "NONE",
1749 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1751 "emit" => '. fist %ia32_emit_am /* integer Store(%A3) -> (%A1) */',
1757 "rd_constructor" => "NONE",
1758 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1760 "emit" => '. fistp %ia32_emit_am /* integer Store(%A3) -> (%A1) and pop */',
1767 "op_flags" => "R|c",
1769 "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
1770 "reg_req" => { "out" => [ "vfp" ] },
1771 "emit" => '. fldz /* x87 0.0 -> %D1 */',
1775 "op_flags" => "R|c",
1777 "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
1778 "reg_req" => { "out" => [ "vfp" ] },
1779 "emit" => '. fld1 /* x87 1.0 -> %D1 */',
1783 "op_flags" => "R|c",
1785 "comment" => "x87 fp Load pi: Ld pi -> reg",
1786 "reg_req" => { "out" => [ "vfp" ] },
1787 "emit" => '. fldpi /* x87 pi -> %D1 */',
1791 "op_flags" => "R|c",
1793 "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
1794 "reg_req" => { "out" => [ "vfp" ] },
1795 "emit" => '. fldln2 /* x87 ln(2) -> %D1 */',
1799 "op_flags" => "R|c",
1801 "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
1802 "reg_req" => { "out" => [ "vfp" ] },
1803 "emit" => '. fldlg2 /* x87 log(2) -> %D1 */',
1807 "op_flags" => "R|c",
1809 "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
1810 "reg_req" => { "out" => [ "vfp" ] },
1811 "emit" => '. fldll2t /* x87 ld(10) -> %D1 */',
1815 "op_flags" => "R|c",
1817 "comment" => "x87 fp Load ld e: Ld ld e -> reg",
1818 "reg_req" => { "out" => [ "vfp" ] },
1819 "emit" => '. fldl2e /* x87 ld(e) -> %D1 */',
1823 "op_flags" => "R|c",
1825 "rd_constructor" => "NONE",
1826 "comment" => "represents a x87 constant",
1827 "reg_req" => { "out" => [ "vfp" ] },
1828 "emit" => '. fld %ia32_emit_adr /* Load fConst into register -> %D1 */',
1832 # Note that it is NEVER allowed to do CSE on these nodes
1833 # Moreover, note the virtual register requierements!
1836 "op_flags" => "R|K",
1837 "comment" => "x87 stack exchange",
1839 "cmp_attr" => "return 1;",
1840 "emit" => '. fxch %X1 /* x87 swap %X1, %X3 */',
1844 "op_flags" => "R|K",
1845 "comment" => "x87 stack push",
1847 "cmp_attr" => "return 1;",
1848 "emit" => '. fld %X1 /* x87 push %X1 */',
1853 "comment" => "x87 stack push",
1854 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1855 "cmp_attr" => "return 1;",
1856 "emit" => '. fld %X1 /* x87 push %X1 */',
1860 "op_flags" => "R|K",
1861 "comment" => "x87 stack pop",
1863 "cmp_attr" => "return 1;",
1864 "emit" => '. fstp %X1 /* x87 pop %X1 */',
1870 "op_flags" => "L|X|Y",
1871 "comment" => "floating point compare",
1876 "op_flags" => "L|X|Y",
1877 "comment" => "floating point compare and pop",
1882 "op_flags" => "L|X|Y",
1883 "comment" => "floating point compare and pop twice",
1888 "op_flags" => "L|X|Y",
1889 "comment" => "floating point compare reverse",
1894 "op_flags" => "L|X|Y",
1895 "comment" => "floating point compare reverse and pop",
1900 "op_flags" => "L|X|Y",
1901 "comment" => "floating point compare reverse and pop twice",