3 # This is the specification for the ia32 assembler Firm-operations
10 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
13 # The node description is done as a perl hash initializer with the
14 # following structure:
19 # op_flags => "N|L|C|X|I|F|Y|H|c|K",
20 # irn_flags => "R|N|I|S"
21 # arity => "0|1|2|3 ... |variable|dynamic|any",
22 # state => "floats|pinned|mem_pinned|exc_pinned",
24 # { type => "type 1", name => "name 1" },
25 # { type => "type 2", name => "name 2" },
28 # comment => "any comment for constructor",
29 # reg_req => { in => [ "reg_class|register" ], out => [ "reg_class|register|in_rX" ] },
30 # cmp_attr => "c source code for comparing node attributes",
31 # emit => "emit code with templates",
32 # attr => "attitional attribute arguments for constructor"
33 # init_attr => "emit attribute initialization template"
34 # rd_constructor => "c source code which constructs an ir_node"
35 # latency => "latency of this operation (can be float)"
38 # ... # (all nodes you need to describe)
40 # ); # close the %nodes initializer
42 # op_flags: flags for the operation, OPTIONAL (default is "N")
43 # the op_flags correspond to the firm irop_flags:
46 # C irop_flag_commutative
47 # X irop_flag_cfopcode
48 # I irop_flag_ip_cfopcode
51 # H irop_flag_highlevel
52 # c irop_flag_constlike
55 # irn_flags: special node flags, OPTIONAL (default is 0)
56 # following irn_flags are supported:
59 # I ignore for register allocation
60 # S modifies stack pointer
62 # state: state of the operation, OPTIONAL (default is "floats")
64 # arity: arity of the operation, MUST NOT BE OMITTED
66 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
67 # are always the first 3 arguments and are always autmatically
69 # If this key is missing the following arguments will be created:
70 # for i = 1 .. arity: ir_node *op_i
73 # outs: if a node defines more than one output, the names of the projections
74 # nodes having outs having automatically the mode mode_T
75 # One can also annotate some flags for each out, additional to irn_flags.
76 # They are separated from name with a colon ':', and concatenated by pipe '|'
77 # Only I and S are available at the moment (same meaning as in irn_flags).
78 # example: [ "frame:I", "stack:I|S", "M" ]
80 # comment: OPTIONAL comment for the node constructor
82 # rd_constructor: for every operation there will be a
83 # new_rd_<arch>_<op-name> function with the arguments from above
84 # which creates the ir_node corresponding to the defined operation
85 # you can either put the complete source code of this function here
87 # This key is OPTIONAL. If omitted, the following constructor will
89 # if (!op_<arch>_<op-name>) assert(0);
93 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
96 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
98 # latency: the latency of the operation, default is 1
102 # 0 - no special type
103 # 1 - caller save (register must be saved by the caller of a function)
104 # 2 - callee save (register must be saved by the called function)
105 # 4 - ignore (do not assign this register)
106 # 8 - emitter can choose an arbitrary register of this class
107 # 16 - the register is a virtual one
108 # 32 - register represents a state
109 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
112 { name => "eax", type => 1 },
113 { name => "edx", type => 1 },
114 { name => "ebx", type => 2 },
115 { name => "ecx", type => 1 },
116 { name => "esi", type => 2 },
117 { name => "edi", type => 2 },
118 { name => "ebp", type => 2 },
119 { name => "esp", type => 4 },
120 { name => "gp_NOREG", type => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
121 { name => "gp_UKNWN", type => 4 | 8 | 16 }, # we need a dummy register for Unknown nodes
122 { mode => "mode_Iu" }
125 { name => "xmm0", type => 1 },
126 { name => "xmm1", type => 1 },
127 { name => "xmm2", type => 1 },
128 { name => "xmm3", type => 1 },
129 { name => "xmm4", type => 1 },
130 { name => "xmm5", type => 1 },
131 { name => "xmm6", type => 1 },
132 { name => "xmm7", type => 1 },
133 { name => "xmm_NOREG", type => 4 | 16 }, # we need a dummy register for NoReg nodes
134 { name => "xmm_UKNWN", type => 4 | 8 | 16}, # we need a dummy register for Unknown nodes
138 { name => "vf0", type => 1 | 16 },
139 { name => "vf1", type => 1 | 16 },
140 { name => "vf2", type => 1 | 16 },
141 { name => "vf3", type => 1 | 16 },
142 { name => "vf4", type => 1 | 16 },
143 { name => "vf5", type => 1 | 16 },
144 { name => "vf6", type => 1 | 16 },
145 { name => "vf7", type => 1 | 16 },
146 { name => "vfp_NOREG", type => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
147 { name => "vfp_UKNWN", type => 4 | 8 | 16 }, # we need a dummy register for Unknown nodes
151 { name => "st0", realname => "st", type => 4 },
152 { name => "st1", realname => "st(1)", type => 4 },
153 { name => "st2", realname => "st(2)", type => 4 },
154 { name => "st3", realname => "st(3)", type => 4 },
155 { name => "st4", realname => "st(4)", type => 4 },
156 { name => "st5", realname => "st(5)", type => 4 },
157 { name => "st6", realname => "st(6)", type => 4 },
158 { name => "st7", realname => "st(7)", type => 4 },
161 fp_cw => [ # the floating point control word
162 { name => "fpcw", type => 4 | 32},
163 { mode => "mode_Hu" }
166 { name => "eflags", type => 4 },
167 { mode => "mode_Iu" }
170 { name => "fpsw", type => 4 },
171 { mode => "mode_Hu" }
176 CF => { reg => "eflags", bit => 0 },
177 PF => { reg => "eflags", bit => 2 },
178 AF => { reg => "eflags", bit => 4 },
179 ZF => { reg => "eflags", bit => 6 },
180 SF => { reg => "eflags", bit => 7 },
181 TF => { reg => "eflags", bit => 8 },
182 IF => { reg => "eflags", bit => 9 },
183 DF => { reg => "eflags", bit => 10 },
184 OF => { reg => "eflags", bit => 11 },
185 IOPL0 => { reg => "eflags", bit => 12 },
186 IOPL1 => { reg => "eflags", bit => 13 },
187 NT => { reg => "eflags", bit => 14 },
188 RF => { reg => "eflags", bit => 16 },
189 VM => { reg => "eflags", bit => 17 },
190 AC => { reg => "eflags", bit => 18 },
191 VIF => { reg => "eflags", bit => 19 },
192 VIP => { reg => "eflags", bit => 20 },
193 ID => { reg => "eflags", bit => 21 },
195 FP_IE => { reg => "fpsw", bit => 0 },
196 FP_DE => { reg => "fpsw", bit => 1 },
197 FP_ZE => { reg => "fpsw", bit => 2 },
198 FP_OE => { reg => "fpsw", bit => 3 },
199 FP_UE => { reg => "fpsw", bit => 4 },
200 FP_PE => { reg => "fpsw", bit => 5 },
201 FP_SF => { reg => "fpsw", bit => 6 },
202 FP_ES => { reg => "fpsw", bit => 7 },
203 FP_C0 => { reg => "fpsw", bit => 8 },
204 FP_C1 => { reg => "fpsw", bit => 9 },
205 FP_C2 => { reg => "fpsw", bit => 10 },
206 FP_TOP0 => { reg => "fpsw", bit => 11 },
207 FP_TOP1 => { reg => "fpsw", bit => 12 },
208 FP_TOP2 => { reg => "fpsw", bit => 13 },
209 FP_C3 => { reg => "fpsw", bit => 14 },
210 FP_B => { reg => "fpsw", bit => 15 },
212 FP_IM => { reg => "fpcw", bit => 0 },
213 FP_DM => { reg => "fpcw", bit => 1 },
214 FP_ZM => { reg => "fpcw", bit => 2 },
215 FP_OM => { reg => "fpcw", bit => 3 },
216 FP_UM => { reg => "fpcw", bit => 4 },
217 FP_PM => { reg => "fpcw", bit => 5 },
218 FP_PC0 => { reg => "fpcw", bit => 8 },
219 FP_PC1 => { reg => "fpcw", bit => 9 },
220 FP_RC0 => { reg => "fpcw", bit => 10 },
221 FP_RC1 => { reg => "fpcw", bit => 11 },
222 FP_X => { reg => "fpcw", bit => 12 }
226 GP => [ 1, "GP_EAX", "GP_EBX", "GP_ECX", "GP_EDX", "GP_ESI", "GP_EDI", "GP_EBP" ],
227 SSE => [ 1, "SSE_XMM0", "SSE_XMM1", "SSE_XMM2", "SSE_XMM3", "SSE_XMM4", "SSE_XMM5", "SSE_XMM6", "SSE_XMM7" ],
228 VFP => [ 1, "VFP_VF0", "VFP_VF1", "VFP_VF2", "VFP_VF3", "VFP_VF4", "VFP_VF5", "VFP_VF6", "VFP_VF7" ],
229 BRANCH => [ 1, "BRANCH1", "BRANCH2" ],
234 bundels_per_cycle => 1
238 S1 => "${arch}_emit_source_register(env, node, 0);",
239 S2 => "${arch}_emit_source_register(env, node, 1);",
240 S3 => "${arch}_emit_source_register(env, node, 2);",
241 S4 => "${arch}_emit_source_register(env, node, 3);",
242 S5 => "${arch}_emit_source_register(env, node, 4);",
243 S6 => "${arch}_emit_source_register(env, node, 5);",
244 D1 => "${arch}_emit_dest_register(env, node, 0);",
245 D2 => "${arch}_emit_dest_register(env, node, 1);",
246 D3 => "${arch}_emit_dest_register(env, node, 2);",
247 D4 => "${arch}_emit_dest_register(env, node, 3);",
248 D5 => "${arch}_emit_dest_register(env, node, 4);",
249 D6 => "${arch}_emit_dest_register(env, node, 5);",
250 A1 => "${arch}_emit_in_node_name(env, node, 0);",
251 A2 => "${arch}_emit_in_node_name(env, node, 1);",
252 A3 => "${arch}_emit_in_node_name(env, node, 2);",
253 A4 => "${arch}_emit_in_node_name(env, node, 3);",
254 A5 => "${arch}_emit_in_node_name(env, node, 4);",
255 A6 => "${arch}_emit_in_node_name(env, node, 5);",
256 X1 => "${arch}_emit_x87_name(env, node, 0);",
257 X2 => "${arch}_emit_x87_name(env, node, 1);",
258 X3 => "${arch}_emit_x87_name(env, node, 2);",
259 C => "${arch}_emit_immediate(env, node);",
260 SE => "${arch}_emit_extend_suffix(env, get_ia32_ls_mode(node));",
261 ME => "if(get_mode_size_bits(get_ia32_ls_mode(node)) != 32)\n
262 ia32_emit_mode_suffix(env, get_ia32_ls_mode(node));",
263 M => "${arch}_emit_mode_suffix(env, get_ia32_ls_mode(node));",
264 XM => "${arch}_emit_x87_mode_suffix(env, node);",
265 XXM => "${arch}_emit_xmm_mode_suffix(env, node);",
266 XSD => "${arch}_emit_xmm_mode_suffix_s(env, node);",
267 AM => "${arch}_emit_am(env, node);",
268 unop => "${arch}_emit_unop(env, node);",
269 binop => "${arch}_emit_binop(env, node);",
270 x87_binop => "${arch}_emit_x87_binop(env, node);",
273 #--------------------------------------------------#
276 # _ __ _____ __ _ _ __ ___ _ __ ___ #
277 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
278 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
279 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
282 #--------------------------------------------------#
284 $default_cmp_attr = "return ia32_compare_attr(attr_a, attr_b);";
289 $mode_xmm = "mode_E";
290 $mode_gp = "mode_Iu";
291 $status_flags = [ "CF", "PF", "AF", "ZF", "SF", "OF" ];
292 $fpcw_flags = [ "FP_IM", "FP_DM", "FP_ZM", "FP_OM", "FP_UM", "FP_PM",
293 "FP_PC0", "FP_PC1", "FP_RC0", "FP_RC1", "FP_X" ];
297 #-----------------------------------------------------------------#
300 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
301 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
302 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
303 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
306 #-----------------------------------------------------------------#
308 # commutative operations
311 # All nodes supporting Addressmode have 5 INs:
312 # 1 - base r1 == NoReg in case of no AM or no base
313 # 2 - index r2 == NoReg in case of no AM or no index
314 # 3 - op1 r3 == always present
315 # 4 - op2 r4 == NoReg in case of immediate operation
316 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
320 comment => "construct Add: Add(a, b) = Add(b, a) = a + b",
321 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
322 emit => '. addl %binop',
325 modified_flags => $status_flags
329 comment => "construct Add with Carry: Adc(a, b) = Add(b, a) = a + b + carry",
330 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
331 emit => '. adcl %binop',
334 modified_flags => $status_flags
339 comment => "construct 64Bit Add: Add(a_l, a_h, b_l, b_h) = a_l + b_l; a_h + b_h + carry",
341 reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
348 outs => [ "low_res", "high_res" ],
350 modified_flags => $status_flags
356 cmp_attr => "return 1;",
357 comment => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
363 cmp_attr => "return 1;",
364 comment => "construct lowered Add with Carry: Adc(a, b) = Adc(b, a) = a + b + carry",
369 # we should not rematrialize this node. It produces 2 results and has
370 # very strict constrains
371 comment => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
372 reg_req => { in => [ "gp", "gp", "eax", "gp", "none" ], out => [ "eax", "edx", "none" ] },
373 emit => '. mull %unop',
374 outs => [ "EAX", "EDX", "M" ],
377 modified_flags => $status_flags
381 # we should not rematrialize this node. It produces 2 results and has
382 # very strict constrains
384 cmp_attr => "return 1;",
385 comment => "construct lowered MulS: Mul(a, b) = Mul(b, a) = a * b",
386 outs => [ "EAX", "EDX", "M" ],
392 comment => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
393 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
394 emit => '. imull %binop',
398 modified_flags => $status_flags
403 comment => "construct Mul (1 operand format): Mul(a, b) = Mul(b, a) = a * b",
404 reg_req => { in => [ "gp", "gp", "eax", "gp", "none" ], out => [ "eax", "edx", "none" ] },
405 emit => '. imull %unop',
406 outs => [ "EAX", "EDX", "M" ],
409 modified_flags => $status_flags
414 cmp_attr => "return 1;",
415 comment => "construct lowered IMul: IMul(a, b) = IMul(b, a) = a * b",
421 comment => "construct And: And(a, b) = And(b, a) = a AND b",
422 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
423 emit => '. andl %binop',
426 modified_flags => $status_flags
431 comment => "construct Or: Or(a, b) = Or(b, a) = a OR b",
432 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
433 emit => '. orl %binop',
436 modified_flags => $status_flags
441 comment => "construct Xor: Xor(a, b) = Xor(b, a) = a EOR b",
442 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
443 emit => '. xorl %binop',
446 modified_flags => $status_flags
451 cmp_attr => "return 1;",
452 comment => "construct lowered Xor: Xor(a, b) = Xor(b, a) = a XOR b",
454 modified_flags => $status_flags
457 # not commutative operations
461 comment => "construct Sub: Sub(a, b) = a - b",
462 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
463 emit => '. subl %binop',
466 modified_flags => $status_flags
470 comment => "construct Sub with Carry: SubC(a, b) = a - b - carry",
471 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3 !in_r4" ] },
472 emit => '. sbbl %binop',
475 modified_flags => $status_flags
480 comment => "construct 64Bit Sub: Sub(a_l, a_h, b_l, b_h) = a_l - b_l; a_h - b_h - borrow",
482 reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
489 outs => [ "low_res", "high_res" ],
491 modified_flags => $status_flags
496 cmp_attr => "return 1;",
497 comment => "construct lowered Sub: Sub(a, b) = a - b",
502 cmp_attr => "return 1;",
503 comment => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
509 state => "exc_pinned",
510 reg_req => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ], out => [ "eax", "edx", "none" ] },
511 attr => "ia32_op_flavour_t dm_flav",
512 init_attr => "attr->data.op_flav = dm_flav;",
513 emit => ". idivl %unop",
514 outs => [ "div_res", "mod_res", "M" ],
517 modified_flags => $status_flags
522 state => "exc_pinned",
523 reg_req => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ], out => [ "eax", "edx", "none" ] },
524 attr => "ia32_op_flavour_t dm_flav",
525 init_attr => "attr->data.op_flav = dm_flav;",
526 emit => ". divl %unop",
527 outs => [ "div_res", "mod_res", "M" ],
530 modified_flags => $status_flags
535 comment => "construct Shl: Shl(a, b) = a << b",
536 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
537 emit => '. shll %binop',
540 modified_flags => $status_flags
544 cmp_attr => "return 1;",
545 comment => "construct lowered Shl: Shl(a, b) = a << b",
551 comment => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
552 # Out requirements is: different from all in
553 # This is because, out must be different from LowPart and ShiftCount.
554 # We could say "!ecx !in_r4" but it can occur, that all values live through
555 # this Shift and the only value dying is the ShiftCount. Then there would be a
556 # register missing, as result must not be ecx and all other registers are
557 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
558 # (and probably never will). So we create artificial interferences of the result
559 # with all inputs, so the spiller can always assure a free register.
560 reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
563 if (get_ia32_immop_type(node) == ia32_ImmNone) {
564 if (get_ia32_op_type(node) == ia32_AddrModeD) {
565 . shldl %%cl, %S4, %AM
567 . shldl %%cl, %S4, %S3
570 if (get_ia32_op_type(node) == ia32_AddrModeD) {
571 . shldl $%C, %S4, %AM
573 . shldl $%C, %S4, %S3
580 modified_flags => $status_flags
584 cmp_attr => "return 1;",
585 comment => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
591 comment => "construct Shr: Shr(a, b) = a >> b",
592 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
593 emit => '. shrl %binop',
596 modified_flags => $status_flags
600 cmp_attr => "return 1;",
601 comment => "construct lowered Shr: Shr(a, b) = a << b",
607 comment => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
608 # Out requirements is: different from all in
609 # This is because, out must be different from LowPart and ShiftCount.
610 # We could say "!ecx !in_r4" but it can occur, that all values live through
611 # this Shift and the only value dying is the ShiftCount. Then there would be a
612 # register missing, as result must not be ecx and all other registers are
613 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
614 # (and probably never will). So we create artificial interferences of the result
615 # with all inputs, so the spiller can always assure a free register.
616 reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
618 if (get_ia32_immop_type(node) == ia32_ImmNone) {
619 if (get_ia32_op_type(node) == ia32_AddrModeD) {
620 . shrdl %%cl, %S4, %AM
622 . shrdl %%cl, %S4, %S3
625 if (get_ia32_op_type(node) == ia32_AddrModeD) {
626 . shrdl $%C, %S4, %AM
628 . shrdl $%C, %S4, %S3
635 modified_flags => $status_flags
639 cmp_attr => "return 1;",
640 comment => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
646 comment => "construct Shrs: Shrs(a, b) = a >> b",
647 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
648 emit => '. sarl %binop',
651 modified_flags => $status_flags
655 cmp_attr => "return 1;",
656 comment => "construct lowered Sar: Sar(a, b) = a << b",
662 comment => "construct Ror: Ror(a, b) = a ROR b",
663 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
664 emit => '. rorl %binop',
667 modified_flags => $status_flags
672 comment => "construct Rol: Rol(a, b) = a ROL b",
673 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
674 emit => '. roll %binop',
677 modified_flags => $status_flags
684 comment => "construct Minus: Minus(a) = -a",
685 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
686 emit => '. negl %unop',
689 modified_flags => $status_flags
694 comment => "construct 64Bit Minus: Minus(a_l, a_h, 0) = 0 - a_l; 0 - a_h - borrow",
696 reg_req => { in => [ "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
703 outs => [ "low_res", "high_res" ],
705 modified_flags => $status_flags
710 cmp_attr => "return 1;",
711 comment => "construct lowered Minus: Minus(a) = -a",
717 comment => "construct Increment: Inc(a) = a++",
718 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
719 emit => '. incl %unop',
722 modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
727 comment => "construct Decrement: Dec(a) = a--",
728 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
729 emit => '. decl %unop',
732 modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
737 comment => "construct Not: Not(a) = !a",
738 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
739 emit => '. notl %unop',
750 comment => "construct conditional jump: CMP A, B && JMPxx LABEL",
751 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ] },
752 outs => [ "false", "true" ],
754 units => [ "BRANCH" ],
760 comment => "construct conditional jump: TEST A, B && JMPxx LABEL",
761 reg_req => { in => [ "gp", "gp" ] },
762 outs => [ "false", "true" ],
764 units => [ "BRANCH" ],
770 comment => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
771 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "none", "none" ] },
772 outs => [ "false", "true" ],
773 units => [ "BRANCH" ],
779 comment => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
780 reg_req => { in => [ "gp", "gp" ] },
781 units => [ "BRANCH" ],
787 comment => "construct switch",
788 reg_req => { in => [ "gp" ], out => [ "none" ] },
790 units => [ "BRANCH" ],
796 comment => "represents an integer constant",
797 reg_req => { out => [ "gp" ] },
806 comment => "unknown value",
807 reg_req => { out => [ "gp_UKNWN" ] },
817 comment => "unknown value",
818 reg_req => { out => [ "vfp_UKNWN" ] },
828 comment => "unknown value",
829 reg_req => { out => [ "xmm_UKNWN" ] },
839 comment => "noreg GP value",
840 reg_req => { out => [ "gp_NOREG" ] },
850 comment => "noreg VFP value",
851 reg_req => { out => [ "vfp_NOREG" ] },
861 comment => "noreg XMM value",
862 reg_req => { out => [ "xmm_NOREG" ] },
872 comment => "change floating point control word",
873 reg_req => { out => [ "fp_cw" ] },
877 modified_flags => $fpcw_flags
882 state => "exc_pinned",
883 comment => "load floating point control word FldCW(ptr, mem) = LD ptr -> reg",
884 reg_req => { in => [ "gp", "gp", "none" ], out => [ "fp_cw" ] },
886 emit => ". fldcw %AM",
889 modified_flags => $fpcw_flags
894 state => "exc_pinned",
895 comment => "store floating point control word: FstCW(ptr, mem) = ST ptr -> reg",
896 reg_req => { in => [ "gp", "gp", "fp_cw", "none" ], out => [ "none" ] },
898 emit => ". fnstcw %AM",
904 # we should not rematrialize this node. It produces 2 results and has
905 # very strict constrains
906 comment => "construct CDQ: sign extend EAX -> EDX:EAX",
907 reg_req => { in => [ "gp" ], out => [ "eax in_r1", "edx" ] },
909 outs => [ "EAX", "EDX" ],
917 state => "exc_pinned",
918 comment => "construct Load: Load(ptr, mem) = LD ptr -> reg",
919 reg_req => { in => [ "gp", "gp", "none" ], out => [ "gp", "none" ] },
921 emit => ". mov%SE%ME%.l %AM, %D1",
922 outs => [ "res", "M" ],
928 cmp_attr => "return 1;",
929 comment => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg",
930 outs => [ "res", "M" ],
936 cmp_attr => "return 1;",
937 state => "exc_pinned",
938 comment => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val",
945 state => "exc_pinned",
946 comment => "construct Store: Store(ptr, val, mem) = ST ptr,val",
947 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "none" ] },
948 emit => '. mov%M %binop',
956 state => "exc_pinned",
957 comment => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
958 reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => ["none" ] },
959 emit => '. mov%M %binop',
967 comment => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
968 reg_req => { in => [ "gp", "gp" ], out => [ "in_r1" ] },
969 emit => '. leal %AM, %D1',
973 modified_flags => [],
977 comment => "push on the stack",
978 reg_req => { in => [ "gp", "gp", "gp", "esp", "none" ], out => [ "esp", "none" ] },
979 emit => '. pushl %unop',
980 outs => [ "stack:I|S", "M" ],
983 modified_flags => [],
987 comment => "pop a gp register from the stack",
988 reg_req => { in => [ "gp", "gp", "esp", "none" ], out => [ "esp", "gp", "none" ] },
989 emit => '. popl %unop',
990 outs => [ "stack:I|S", "res", "M" ],
993 modified_flags => [],
997 comment => "create stack frame",
998 reg_req => { in => [ "esp" ], out => [ "ebp", "esp" ] },
1000 outs => [ "frame:I", "stack:I|S", "M" ],
1006 comment => "destroy stack frame",
1007 reg_req => { in => [ "esp", "ebp" ], out => [ "ebp", "esp" ] },
1009 outs => [ "frame:I", "stack:I|S" ],
1016 comment => "allocate space on stack",
1017 reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "none" ] },
1018 emit => '. addl %binop',
1019 outs => [ "stack:S", "M" ],
1021 modified_flags => $status_flags
1026 comment => "free space on stack",
1027 reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "none" ] },
1028 emit => '. subl %binop',
1029 outs => [ "stack:S", "M" ],
1031 modified_flags => $status_flags
1036 comment => "get the TLS base address",
1037 reg_req => { out => [ "gp" ] },
1043 #-----------------------------------------------------------------------------#
1044 # _____ _____ ______ __ _ _ _ #
1045 # / ____/ ____| ____| / _| | | | | | #
1046 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1047 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1048 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1049 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1050 #-----------------------------------------------------------------------------#
1052 # commutative operations
1056 comment => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
1057 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1058 emit => '. add%XXM %binop',
1066 comment => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
1067 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1068 emit => '. mul%XXM %binop',
1076 comment => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
1077 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1078 emit => '. max%XXM %binop',
1086 comment => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
1087 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1088 emit => '. min%XXM %binop',
1096 comment => "construct SSE And: And(a, b) = a AND b",
1097 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1098 emit => '. andp%XSD %binop',
1106 comment => "construct SSE Or: Or(a, b) = a OR b",
1107 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1108 emit => '. orp%XSD %binop',
1115 comment => "construct SSE Xor: Xor(a, b) = a XOR b",
1116 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1117 emit => '. xorp%XSD %binop',
1123 # not commutative operations
1127 comment => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
1128 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] },
1129 emit => '. andnp%XSD %binop',
1137 comment => "construct SSE Sub: Sub(a, b) = a - b",
1138 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1139 emit => '. sub%XXM %binop',
1147 comment => "construct SSE Div: Div(a, b) = a / b",
1148 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] },
1149 outs => [ "res", "M" ],
1150 emit => '. div%XXM %binop',
1159 comment => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
1160 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] },
1168 op_flags => "L|X|Y",
1169 comment => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
1170 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "none", "none" ] },
1171 outs => [ "false", "true" ],
1179 comment => "represents a SSE constant",
1180 reg_req => { out => [ "xmm" ] },
1181 emit => '. mov%XXM $%C, %D1',
1191 state => "exc_pinned",
1192 comment => "construct SSE Load: Load(ptr, mem) = LD ptr",
1193 reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none" ] },
1194 emit => '. mov%XXM %AM, %D1',
1195 outs => [ "res", "M" ],
1202 state => "exc_pinned",
1203 comment => "construct Store: Store(ptr, val, mem) = ST ptr,val",
1204 reg_req => { in => [ "gp", "gp", "xmm", "none" ] },
1205 emit => '. mov%XXM %binop',
1213 state => "exc_pinned",
1214 comment => "construct Store without index: Store(ptr, val, mem) = ST ptr,val",
1215 reg_req => { in => [ "gp", "xmm", "none" ] },
1216 emit => '. mov%XXM %S2, %AM',
1224 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm" ] },
1225 emit => '. cvtsi2ss %D1, %AM',
1233 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm" ] },
1234 emit => '. cvtsi2sd %unop',
1243 comment => "construct: transfer a value from x87 FPU into a SSE register",
1244 cmp_attr => "return 1;",
1250 comment => "construct: transfer a value from SSE register to x87 FPU",
1251 cmp_attr => "return 1;",
1258 state => "exc_pinned",
1259 comment => "store ST0 onto stack",
1260 reg_req => { in => [ "gp", "gp", "none" ] },
1261 emit => '. fstp%XM %AM',
1270 state => "exc_pinned",
1271 comment => "load ST0 from stack",
1272 reg_req => { in => [ "gp", "none" ], out => [ "vf0", "none" ] },
1273 emit => '. fld%M %AM',
1274 outs => [ "res", "M" ],
1284 comment => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
1285 reg_req => { in => [ "edi", "esi", "ecx", "none" ], out => [ "edi", "esi", "ecx", "none" ] },
1286 outs => [ "DST", "SRC", "CNT", "M" ],
1288 modified_flags => [ "DF" ]
1294 comment => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
1295 reg_req => { in => [ "edi", "esi", "none" ], out => [ "edi", "esi", "none" ] },
1296 outs => [ "DST", "SRC", "M" ],
1298 modified_flags => [ "DF" ]
1304 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3", "none" ] },
1305 comment => "construct Conv Int -> Int",
1308 modified_flags => $status_flags
1312 reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => [ "in_r3", "none" ] },
1313 comment => "construct Conv Int -> Int",
1316 modified_flags => $status_flags
1320 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm", "none" ] },
1321 comment => "construct Conv Int -> Floating Point",
1328 reg_req => { in => [ "gp", "gp", "xmm", "none" ], out => [ "gp", "none" ] },
1329 comment => "construct Conv Floating Point -> Int",
1336 reg_req => { in => [ "gp", "gp", "xmm", "none" ], out => [ "xmm", "none" ] },
1337 comment => "construct Conv Floating Point -> Floating Point",
1345 comment => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
1346 reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "in_r4" ] },
1354 comment => "check if Psi condition tree evaluates to true and move result accordingly",
1355 reg_req => { in => [ "gp", "gp", "gp" ], out => [ "in_r3" ] },
1363 comment => "construct Conditional Move: SSE Compare + int CMov ",
1364 reg_req => { in => [ "xmm", "xmm", "gp", "gp" ], out => [ "in_r4" ] },
1372 comment => "construct Conditional Move: x87 Compare + int CMov",
1373 reg_req => { in => [ "vfp", "vfp", "gp", "gp" ], out => [ "in_r4" ] },
1381 comment => "construct Set: Set(sel) == sel ? 1 : 0",
1382 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "eax ebx ecx edx" ] },
1390 comment => "check if Psi condition tree evaluates to true and set result accordingly",
1391 reg_req => { in => [ "gp" ], out => [ "eax ebx ecx edx" ] },
1399 comment => "construct Set: SSE Compare + int Set",
1400 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "eax ebx ecx edx" ] },
1408 comment => "construct Set: x87 Compare + int Set",
1409 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "eax ebx ecx edx" ] },
1417 comment => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
1418 reg_req => { in => [ "vfp", "vfp", "vfp", "vfp" ], out => [ "vfp" ] },
1424 #----------------------------------------------------------#
1426 # (_) | | | | / _| | | | #
1427 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
1428 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
1429 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
1430 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
1432 # _ __ ___ __| | ___ ___ #
1433 # | '_ \ / _ \ / _` |/ _ \/ __| #
1434 # | | | | (_) | (_| | __/\__ \ #
1435 # |_| |_|\___/ \__,_|\___||___/ #
1436 #----------------------------------------------------------#
1440 comment => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
1441 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1449 comment => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1450 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1458 cmp_attr => "return 1;",
1459 comment => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1465 comment => "virtual fp Sub: Sub(a, b) = a - b",
1466 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1473 cmp_attr => "return 1;",
1474 comment => "lowered virtual fp Sub: Sub(a, b) = a - b",
1479 comment => "virtual fp Div: Div(a, b) = a / b",
1480 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1481 outs => [ "res", "M" ],
1487 cmp_attr => "return 1;",
1488 comment => "lowered virtual fp Div: Div(a, b) = a / b",
1489 outs => [ "res", "M" ],
1494 comment => "virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1495 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1502 cmp_attr => "return 1;",
1503 comment => "lowered virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1509 comment => "virtual fp Abs: Abs(a) = |a|",
1510 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1518 comment => "virtual fp Chs: Chs(a) = -a",
1519 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1527 comment => "virtual fp Sin: Sin(a) = sin(a)",
1528 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1536 comment => "virtual fp Cos: Cos(a) = cos(a)",
1537 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1545 comment => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
1546 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1552 # virtual Load and Store
1556 state => "exc_pinned",
1557 comment => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
1558 reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] },
1559 outs => [ "res", "M" ],
1566 state => "exc_pinned",
1567 comment => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
1568 reg_req => { in => [ "gp", "gp", "vfp", "none" ] },
1577 comment => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1578 reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] },
1579 outs => [ "res", "M" ],
1585 cmp_attr => "return 1;",
1586 comment => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1587 outs => [ "res", "M" ],
1592 comment => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1593 reg_req => { in => [ "gp", "gp", "vfp", "fpcw", "none" ] },
1600 cmp_attr => "return 1;",
1601 comment => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1611 comment => "virtual fp Load 0.0: Ld 0.0 -> reg",
1612 reg_req => { out => [ "vfp" ] },
1620 comment => "virtual fp Load 1.0: Ld 1.0 -> reg",
1621 reg_req => { out => [ "vfp" ] },
1629 comment => "virtual fp Load pi: Ld pi -> reg",
1630 reg_req => { out => [ "vfp" ] },
1638 comment => "virtual fp Load ln 2: Ld ln 2 -> reg",
1639 reg_req => { out => [ "vfp" ] },
1647 comment => "virtual fp Load lg 2: Ld lg 2 -> reg",
1648 reg_req => { out => [ "vfp" ] },
1656 comment => "virtual fp Load ld 10: Ld ld 10 -> reg",
1657 reg_req => { out => [ "vfp" ] },
1665 comment => "virtual fp Load ld e: Ld ld e -> reg",
1666 reg_req => { out => [ "vfp" ] },
1675 # init_attr => " set_ia32_ls_mode(res, mode);",
1676 comment => "represents a virtual floating point constant",
1677 reg_req => { out => [ "vfp" ] },
1687 op_flags => "L|X|Y",
1688 comment => "represents a virtual floating point compare",
1689 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "none", "none", "eax" ] },
1690 outs => [ "false", "true", "temp_reg_eax" ],
1695 #------------------------------------------------------------------------#
1696 # ___ _____ __ _ _ _ #
1697 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1698 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1699 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1700 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1701 #------------------------------------------------------------------------#
1703 # Note: gas is strangely buggy: fdivrp and fdivp as well as fsubrp and fsubp
1704 # are swapped, we work this around in the emitter...
1708 rd_constructor => "NONE",
1709 comment => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1711 emit => '. fadd%XM %x87_binop',
1716 rd_constructor => "NONE",
1717 comment => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1719 emit => '. faddp %x87_binop',
1724 rd_constructor => "NONE",
1725 comment => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1727 emit => '. fmul%XM %x87_binop',
1732 rd_constructor => "NONE",
1733 comment => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1735 emit => '. fmulp %x87_binop',,
1740 rd_constructor => "NONE",
1741 comment => "x87 fp Sub: Sub(a, b) = a - b",
1743 emit => '. fsub%XM %x87_binop',
1748 rd_constructor => "NONE",
1749 comment => "x87 fp Sub: Sub(a, b) = a - b",
1751 # see note about gas bugs
1752 emit => '. fsubrp %x87_binop',
1757 rd_constructor => "NONE",
1759 comment => "x87 fp SubR: SubR(a, b) = b - a",
1761 emit => '. fsubr%XM %x87_binop',
1766 rd_constructor => "NONE",
1768 comment => "x87 fp SubR: SubR(a, b) = b - a",
1770 # see note about gas bugs
1771 emit => '. fsubp %x87_binop',
1776 rd_constructor => "NONE",
1777 comment => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1782 # this node is just here, to keep the simulator running
1783 # we can omit this when a fprem simulation function exists
1786 rd_constructor => "NONE",
1787 comment => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1794 rd_constructor => "NONE",
1795 comment => "x87 fp Div: Div(a, b) = a / b",
1797 emit => '. fdiv%XM %x87_binop',
1802 rd_constructor => "NONE",
1803 comment => "x87 fp Div: Div(a, b) = a / b",
1805 # see note about gas bugs
1806 emit => '. fdivrp %x87_binop',
1811 rd_constructor => "NONE",
1812 comment => "x87 fp DivR: DivR(a, b) = b / a",
1814 emit => '. fdivr%XM %x87_binop',
1819 rd_constructor => "NONE",
1820 comment => "x87 fp DivR: DivR(a, b) = b / a",
1822 # see note about gas bugs
1823 emit => '. fdivp %x87_binop',
1828 rd_constructor => "NONE",
1829 comment => "x87 fp Abs: Abs(a) = |a|",
1836 rd_constructor => "NONE",
1837 comment => "x87 fp Chs: Chs(a) = -a",
1844 rd_constructor => "NONE",
1845 comment => "x87 fp Sin: Sin(a) = sin(a)",
1852 rd_constructor => "NONE",
1853 comment => "x87 fp Cos: Cos(a) = cos(a)",
1860 rd_constructor => "NONE",
1861 comment => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1863 emit => '. fsqrt $',
1866 # x87 Load and Store
1869 rd_constructor => "NONE",
1870 op_flags => "R|L|F",
1871 state => "exc_pinned",
1872 comment => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1874 emit => '. fld%XM %AM',
1878 rd_constructor => "NONE",
1879 op_flags => "R|L|F",
1880 state => "exc_pinned",
1881 comment => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1883 emit => '. fst%XM %AM',
1888 rd_constructor => "NONE",
1889 op_flags => "R|L|F",
1890 state => "exc_pinned",
1891 comment => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1893 emit => '. fstp%XM %AM',
1901 rd_constructor => "NONE",
1902 comment => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1904 emit => '. fild%XM %AM',
1909 rd_constructor => "NONE",
1910 comment => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1912 emit => '. fist%M %AM',
1918 rd_constructor => "NONE",
1919 comment => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1921 emit => '. fistp%M %AM',
1930 comment => "x87 fp Load 0.0: Ld 0.0 -> reg",
1938 comment => "x87 fp Load 1.0: Ld 1.0 -> reg",
1946 comment => "x87 fp Load pi: Ld pi -> reg",
1954 comment => "x87 fp Load ln 2: Ld ln 2 -> reg",
1962 comment => "x87 fp Load lg 2: Ld lg 2 -> reg",
1970 comment => "x87 fp Load ld 10: Ld ld 10 -> reg",
1972 emit => '. fldll2t',
1978 comment => "x87 fp Load ld e: Ld ld e -> reg",
1984 # Note that it is NEVER allowed to do CSE on these nodes
1985 # Moreover, note the virtual register requierements!
1989 comment => "x87 stack exchange",
1991 cmp_attr => "return 1;",
1992 emit => '. fxch %X1',
1997 comment => "x87 stack push",
1999 cmp_attr => "return 1;",
2000 emit => '. fld %X1',
2005 comment => "x87 stack push",
2006 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
2007 cmp_attr => "return 1;",
2008 emit => '. fld %X1',
2013 comment => "x87 stack pop",
2015 cmp_attr => "return 1;",
2016 emit => '. fstp %X1',
2022 op_flags => "L|X|Y",
2023 comment => "floating point compare",
2028 op_flags => "L|X|Y",
2029 comment => "floating point compare and pop",
2034 op_flags => "L|X|Y",
2035 comment => "floating point compare and pop twice",
2040 op_flags => "L|X|Y",
2041 comment => "floating point compare reverse",
2046 op_flags => "L|X|Y",
2047 comment => "floating point compare reverse and pop",
2052 op_flags => "L|X|Y",
2053 comment => "floating point compare reverse and pop twice",
2058 # -------------------------------------------------------------------------------- #
2059 # ____ ____ _____ _ _ #
2060 # / ___/ ___|| ____| __ _____ ___| |_ ___ _ __ _ __ ___ __| | ___ ___ #
2061 # \___ \___ \| _| \ \ / / _ \/ __| __/ _ \| '__| | '_ \ / _ \ / _` |/ _ \/ __| #
2062 # ___) |__) | |___ \ V / __/ (__| || (_) | | | | | | (_) | (_| | __/\__ \ #
2063 # |____/____/|_____| \_/ \___|\___|\__\___/|_| |_| |_|\___/ \__,_|\___||___/ #
2065 # -------------------------------------------------------------------------------- #
2068 # Spilling and reloading of SSE registers, hardcoded, not generated #
2072 state => "exc_pinned",
2073 comment => "construct SSE Load: Load(ptr, mem) = LD ptr",
2074 reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none" ] },
2075 emit => '. movdqu %D1, %AM',
2076 outs => [ "res", "M" ],
2082 state => "exc_pinned",
2083 comment => "construct Store: Store(ptr, val, mem) = ST ptr,val",
2084 reg_req => { in => [ "gp", "gp", "xmm", "none" ] },
2085 emit => '. movdqu %binop',
2092 # Include the generated SIMD node specification written by the SIMD optimization
2093 $my_script_name = dirname($myname) . "/../ia32/ia32_simd_spec.pl";
2094 unless ($return = do $my_script_name) {
2095 warn "couldn't parse $my_script_name: $@" if $@;
2096 warn "couldn't do $my_script_name: $!" unless defined $return;
2097 warn "couldn't run $my_script_name" unless $return;