8 #include "firm_types.h"
13 #include "../benode_t.h"
15 #include "ia32_new_nodes.h"
16 #include "bearch_ia32_t.h"
19 #define is_NoMem(irn) (get_irn_op(irn) == op_NoMem)
22 * creates a unique ident by adding a number to a tag
24 * @param tag the tag string, must contain a %d if a number
27 static ident *unique_id(const char *tag)
29 static unsigned id = 0;
32 snprintf(str, sizeof(str), tag, ++id);
33 return new_id_from_str(str);
39 * Transforms a SymConst.
41 * @param mod the debug module
42 * @param block the block the new node should belong to
43 * @param node the ir SymConst node
44 * @param mode mode of the SymConst
45 * @return the created ia32 Const node
47 static ir_node *gen_SymConst(ia32_transform_env_t *env) {
49 dbg_info *dbg = env->dbg;
50 ir_mode *mode = env->mode;
51 ir_graph *irg = env->irg;
52 ir_node *block = env->block;
54 cnst = new_rd_ia32_Const(dbg, irg, block, mode);
55 set_ia32_Const_attr(cnst, env->irn);
60 * Get a primitive type for a mode.
62 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
64 pmap_entry *e = pmap_find(types, mode);
69 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
70 res = new_type_primitive(new_id_from_str(buf), mode);
71 pmap_insert(types, mode, res);
79 * Get an entity that is initialized with a tarval
81 static entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
83 tarval *tv = get_Const_tarval(cnst);
84 pmap_entry *e = pmap_find(cg->tv_ent, tv);
89 ir_mode *mode = get_irn_mode(cnst);
90 ir_type *tp = get_Const_type(cnst);
91 if (tp == firm_unknown_type)
92 tp = get_prim_type(cg->types, mode);
94 res = new_entity(get_glob_type(), unique_id("ia32FloatCnst_%u"), tp);
96 set_entity_ld_ident(res, get_entity_ident(res));
97 set_entity_visibility(res, visibility_local);
98 set_entity_variability(res, variability_constant);
99 set_entity_allocation(res, allocation_static);
101 /* we create a new entity here: It's initialization must resist on the
103 rem = current_ir_graph;
104 current_ir_graph = get_const_code_irg();
105 set_atomic_ent_value(res, new_Const_type(tv, tp));
106 current_ir_graph = rem;
114 * Transforms a Const.
116 * @param mod the debug module
117 * @param block the block the new node should belong to
118 * @param node the ir Const node
119 * @param mode mode of the Const
120 * @return the created ia32 Const node
122 static ir_node *gen_Const(ia32_transform_env_t *env) {
125 ir_graph *irg = env->irg;
126 ir_node *block = env->block;
127 ir_node *node = env->irn;
128 dbg_info *dbg = env->dbg;
129 ir_mode *mode = env->mode;
131 if (mode_is_float(mode)) {
132 sym.entity_p = get_entity_for_tv(env->cg, node);
134 cnst = new_rd_SymConst(dbg, irg, block, sym, symconst_addr_ent);
136 cnst = gen_SymConst(env);
139 cnst = new_rd_ia32_Const(dbg, irg, block, get_irn_mode(node));
140 set_ia32_Const_attr(cnst, node);
148 * Transforms (all) Const's into ia32_Const and places them in the
149 * block where they are used (or in the cfg-pred Block in case of Phi's)
151 void ia32_place_consts(ir_node *irn, void *env) {
152 ia32_code_gen_t *cg = env;
153 ia32_transform_env_t tenv;
155 ir_node *pred, *cnst;
162 mode = get_irn_mode(irn);
164 tenv.arch_env = cg->arch_env;
165 tenv.block = get_nodes_block(irn);
170 /* Loop over all predecessors and check for Sym/Const nodes */
171 for (i = get_irn_arity(irn) - 1; i >= 0; --i) {
172 pred = get_irn_n(irn, i);
174 opc = get_irn_opcode(pred);
176 tenv.mode = get_irn_mode(pred);
177 tenv.dbg = get_irn_dbg_info(pred);
179 /* If it's a Phi, then we need to create the */
180 /* new Const in it's predecessor block */
182 tenv.block = get_Block_cfgpred_block(get_nodes_block(irn), i);
187 cnst = gen_Const(&tenv);
190 cnst = gen_SymConst(&tenv);
196 /* if we found a const, then set it */
198 set_irn_n(irn, i, cnst);
204 /******************************************************************
206 * /\ | | | | | \/ | | |
207 * / \ __| | __| |_ __ ___ ___ ___| \ / | ___ __| | ___
208 * / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \
209 * / ____ \ (_| | (_| | | | __/\__ \__ \ | | | (_) | (_| | __/
210 * /_/ \_\__,_|\__,_|_| \___||___/___/_| |_|\___/ \__,_|\___|
212 ******************************************************************/
214 static int node_is_comm(const ir_node *irn) {
215 if (is_ia32_Add(irn) ||
237 static int ia32_get_irn_n_edges(const ir_node *irn) {
238 const ir_edge_t *edge;
241 foreach_out_edge(irn, edge) {
249 * Returns the first mode_M Proj connected to irn.
251 static ir_node *get_mem_proj(const ir_node *irn) {
252 const ir_edge_t *edge;
255 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
257 foreach_out_edge(irn, edge) {
258 src = get_edge_src_irn(edge);
260 assert(is_Proj(src) && "Proj expected");
262 if (get_irn_mode(src) == mode_M)
270 * Returns the Proj with number 0 connected to irn.
272 static ir_node *get_res_proj(const ir_node *irn) {
273 const ir_edge_t *edge;
276 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
278 foreach_out_edge(irn, edge) {
279 src = get_edge_src_irn(edge);
281 assert(is_Proj(src) && "Proj expected");
283 if (get_Proj_proj(src) == 0)
291 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor.
293 * @param pred The node to be checked
294 * @param is_op_func The check-function
295 * @return 1 if conditions are fulfilled, 0 otherwise
297 static int pred_is_specific_node(const ir_node *pred, int (*is_op_func)(const ir_node *n)) {
298 if (is_Proj(pred) && is_op_func(get_Proj_pred(pred))) {
306 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor
307 * and if the predecessor is in block bl.
309 * @param bl The block
310 * @param pred The node to be checked
311 * @param is_op_func The check-function
312 * @return 1 if conditions are fulfilled, 0 otherwise
314 static int pred_is_specific_nodeblock(const ir_node *bl, const ir_node *pred,
315 int (*is_op_func)(const ir_node *n))
318 pred = get_Proj_pred(pred);
319 if ((bl == get_nodes_block(pred)) && is_op_func(pred)) {
328 * Folds Add or Sub to LEA if possible
330 static ir_node *fold_addr(ir_node *irn, firm_dbg_module_t *mod, ir_node *noreg) {
331 ir_graph *irg = get_irn_irg(irn);
332 ir_mode *mode = get_irn_mode(irn);
333 dbg_info *dbg = get_irn_dbg_info(irn);
334 ir_node *block = get_nodes_block(irn);
337 char *offs_cnst = NULL;
338 char *offs_lea = NULL;
342 ir_node *left, *right, *temp;
343 ir_node *base, *index;
344 ia32_am_flavour_t am_flav;
346 if (is_ia32_Add(irn))
349 left = get_irn_n(irn, 2);
350 right = get_irn_n(irn, 3);
358 /* "normalize" arguments in case of add with two operands */
359 if (isadd && ! be_is_NoReg(right)) {
360 /* put LEA == ia32_am_O as right operand */
361 if (is_ia32_Lea(left) && get_ia32_am_flavour(left) == ia32_am_O) {
362 set_irn_n(irn, 2, right);
363 set_irn_n(irn, 3, left);
369 /* put LEA != ia32_am_O as left operand */
370 if (is_ia32_Lea(right) && get_ia32_am_flavour(right) != ia32_am_O) {
371 set_irn_n(irn, 2, right);
372 set_irn_n(irn, 3, left);
378 /* put SHL as left operand iff left is NOT a LEA */
379 if (! is_ia32_Lea(left) && pred_is_specific_node(right, is_ia32_Shl)) {
380 set_irn_n(irn, 2, right);
381 set_irn_n(irn, 3, left);
388 /* check if operand is either const */
389 if (get_ia32_cnst(irn)) {
390 DBG((mod, LEVEL_1, "\tfound op with imm"));
392 offs_cnst = get_ia32_cnst(irn);
396 /* determine the operand which needs to be checked */
397 if (be_is_NoReg(right)) {
404 /* check if right operand is AMConst (LEA with ia32_am_O) */
405 if (is_ia32_Lea(temp) && get_ia32_am_flavour(temp) == ia32_am_O) {
406 DBG((mod, LEVEL_1, "\tgot op with LEA am_O"));
408 offs_lea = get_ia32_am_offs(temp);
413 /* default for add -> make right operand to index */
417 DBG((mod, LEVEL_1, "\tgot LEA candidate with index %+F\n", index));
419 /* determine the operand which needs to be checked */
421 if (is_ia32_Lea(left)) {
425 /* check for SHL 1,2,3 */
426 if (pred_is_specific_node(temp, is_ia32_Shl)) {
427 temp = get_Proj_pred(temp);
429 if (get_ia32_Immop_tarval(temp)) {
430 scale = get_tarval_long(get_ia32_Immop_tarval(temp));
434 index = get_irn_n(temp, 2);
436 DBG((mod, LEVEL_1, "\tgot scaled index %+F\n", index));
442 if (! be_is_NoReg(index)) {
443 /* if we have index, but left == right -> no base */
447 else if (! is_ia32_Lea(left) && (index != right)) {
448 /* index != right -> we found a good Shl */
449 /* left != LEA -> this Shl was the left operand */
450 /* -> base is right operand */
456 /* Try to assimilate a LEA as left operand */
457 if (is_ia32_Lea(left) && (get_ia32_am_flavour(left) != ia32_am_O)) {
458 am_flav = get_ia32_am_flavour(left);
460 /* If we have an Add with a real right operand (not NoReg) and */
461 /* the LEA contains already an index calculation then we create */
463 if (isadd && !be_is_NoReg(index) && (am_flav & ia32_am_I)) {
464 DBG((mod, LEVEL_1, "\tleave old LEA, creating new one\n"));
467 DBG((mod, LEVEL_1, "\tgot LEA as left operand ... assimilating\n"));
468 offs = get_ia32_am_offs(left);
469 base = get_irn_n(left, 0);
470 index = get_irn_n(left, 1);
471 scale = get_ia32_am_scale(left);
475 /* ok, we can create a new LEA */
477 res = new_rd_ia32_Lea(dbg, irg, block, base, index, mode_Is);
479 /* add the old offset of a previous LEA */
481 add_ia32_am_offs(res, offs);
484 /* add the new offset */
487 add_ia32_am_offs(res, offs_cnst);
490 add_ia32_am_offs(res, offs_lea);
494 /* either lea_O-cnst, -cnst or -lea_O */
497 add_ia32_am_offs(res, offs_lea);
500 sub_ia32_am_offs(res, offs_cnst);
503 sub_ia32_am_offs(res, offs_lea);
508 set_ia32_am_scale(res, scale);
511 /* determine new am flavour */
512 if (offs || offs_cnst || offs_lea) {
515 if (! be_is_NoReg(base)) {
518 if (! be_is_NoReg(index)) {
524 set_ia32_am_flavour(res, am_flav);
526 set_ia32_op_type(res, ia32_AddrModeS);
528 DBG((mod, LEVEL_1, "\tLEA [%+F + %+F * %d + %s]\n", base, index, scale, get_ia32_am_offs(res)));
530 /* get the result Proj of the Add/Sub */
531 irn = get_res_proj(irn);
533 assert(irn && "Couldn't find result proj");
535 /* exchange the old op with the new LEA */
543 * Optimizes a pattern around irn to address mode if possible.
545 void ia32_optimize_am(ir_node *irn, void *env) {
546 ia32_code_gen_t *cg = env;
547 ir_graph *irg = cg->irg;
548 firm_dbg_module_t *mod = cg->mod;
552 ir_node *block, *noreg_gp, *noreg_fp;
553 ir_node *left, *right, *temp;
554 ir_node *store, *load, *mem_proj;
555 ir_node *succ, *addr_b, *addr_i;
556 int check_am_src = 0;
558 if (! is_ia32_irn(irn))
561 dbg = get_irn_dbg_info(irn);
562 mode = get_irn_mode(irn);
563 block = get_nodes_block(irn);
564 noreg_gp = ia32_new_NoReg_gp(cg);
565 noreg_fp = ia32_new_NoReg_fp(cg);
567 DBG((mod, LEVEL_1, "checking for AM\n"));
569 /* 1st part: check for address calculations and transform the into Lea */
571 /* Following cases can occur: */
572 /* - Sub (l, imm) -> LEA [base - offset] */
573 /* - Sub (l, r == LEA with ia32_am_O) -> LEA [base - offset] */
574 /* - Add (l, imm) -> LEA [base + offset] */
575 /* - Add (l, r == LEA with ia32_am_O) -> LEA [base + offset] */
576 /* - Add (l == LEA with ia32_am_O, r) -> LEA [base + offset] */
577 /* - Add (l, r) -> LEA [base + index * scale] */
578 /* with scale > 1 iff l/r == shl (1,2,3) */
580 if (is_ia32_Sub(irn) || is_ia32_Add(irn)) {
581 left = get_irn_n(irn, 2);
582 right = get_irn_n(irn, 3);
584 /* Do not try to create a LEA if one of the operands is a Load. */
585 if (! pred_is_specific_nodeblock(block, left, is_ia32_Load) &&
586 ! pred_is_specific_nodeblock(block, right, is_ia32_Load))
588 res = fold_addr(irn, mod, noreg_gp);
592 /* 2nd part: fold following patterns: */
593 /* - Load -> LEA into Load } TODO: If the LEA is used by more than one Load/Store */
594 /* - Store -> LEA into Store } it might be better to keep the LEA */
595 /* - op -> Load into AMop with am_Source */
597 /* - op is am_Source capable AND */
598 /* - the Load is only used by this op AND */
599 /* - the Load is in the same block */
600 /* - Store -> op -> Load into AMop with am_Dest */
602 /* - op is am_Dest capable AND */
603 /* - the Store uses the same address as the Load AND */
604 /* - the Load is only used by this op AND */
605 /* - the Load and Store are in the same block AND */
606 /* - nobody else uses the result of the op */
608 if ((res == irn) && (get_ia32_am_support(irn) != ia32_am_None) && !is_ia32_Lea(irn)) {
609 /* 1st: check for Load/Store -> LEA */
610 if (is_ia32_Ld(irn) || is_ia32_St(irn)) {
611 left = get_irn_n(irn, 0);
613 if (is_ia32_Lea(left)) {
614 /* get the AM attributes from the LEA */
615 add_ia32_am_offs(irn, get_ia32_am_offs(left));
616 set_ia32_am_scale(irn, get_ia32_am_scale(left));
617 set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
618 set_ia32_op_type(irn, get_ia32_op_type(left));
620 /* set base and index */
621 set_irn_n(irn, 0, get_irn_n(left, 0));
622 set_irn_n(irn, 1, get_irn_n(left, 1));
625 /* check if at least one operand is a Load */
626 else if (pred_is_specific_nodeblock(block, get_irn_n(irn, 2), is_ia32_Ld) ||
627 pred_is_specific_nodeblock(block, get_irn_n(irn, 3), is_ia32_Ld))
629 left = get_irn_n(irn, 2);
630 if (get_irn_arity(irn) == 4) {
631 /* it's an "unary" operation */
635 right = get_irn_n(irn, 3);
638 /* normalize commutative ops */
639 if (node_is_comm(irn)) {
640 /* Assure that right operand is always a Load if there is one */
641 /* because non-commutative ops can only use Dest AM if the right */
642 /* operand is a load, so we only need to check right operand. */
643 if (pred_is_specific_nodeblock(block, left, is_ia32_Ld))
645 set_irn_n(irn, 2, right);
646 set_irn_n(irn, 3, left);
654 /* check for Store -> op -> Load */
656 /* Store -> op -> Load optimization is only possible if supported by op */
657 /* and if right operand is a Load */
658 if ((get_ia32_am_support(irn) & ia32_am_Dest) &&
659 pred_is_specific_nodeblock(block, right, is_ia32_Ld))
662 /* An address mode capable op always has a result Proj. */
663 /* If this Proj is used by more than one other node, we don't need to */
664 /* check further, otherwise we check for Store and remember the address, */
665 /* the Store points to. */
667 succ = get_res_proj(irn);
668 assert(succ && "Couldn't find result proj");
674 /* now check for users and Store */
675 if (ia32_get_irn_n_edges(succ) == 1) {
676 succ = get_edge_src_irn(get_irn_out_edge_first(succ));
678 if (is_ia32_fStore(succ) || is_ia32_Store(succ)) {
680 addr_b = get_irn_n(store, 0);
682 /* Could be that the Store is connected to the address */
683 /* calculating LEA while the Load is already transformed. */
684 if (is_ia32_Lea(addr_b)) {
686 addr_b = get_irn_n(succ, 0);
687 addr_i = get_irn_n(succ, 1);
696 /* we found a Store as single user: Now check for Load */
698 /* Extra check for commutative ops with two Loads */
699 /* -> put the interesting Load right */
700 if (node_is_comm(irn) &&
701 pred_is_specific_nodeblock(block, left, is_ia32_Ld))
703 if ((addr_b == get_irn_n(get_Proj_pred(left), 0)) &&
704 (addr_i == get_irn_n(get_Proj_pred(left), 1)))
706 /* We exchange left and right, so it's easier to kill */
707 /* the correct Load later and to handle unary operations. */
708 set_irn_n(irn, 2, right);
709 set_irn_n(irn, 3, left);
717 /* skip the Proj for easier access */
718 load = get_Proj_pred(right);
720 /* Compare Load and Store address */
721 if ((addr_b == get_irn_n(load, 0)) && (addr_i == get_irn_n(load, 1)))
723 /* Right Load is from same address, so we can */
724 /* disconnect the Load and Store here */
726 /* set new base, index and attributes */
727 set_irn_n(irn, 0, addr_b);
728 set_irn_n(irn, 1, addr_i);
729 add_ia32_am_offs(irn, get_ia32_am_offs(load));
730 set_ia32_am_scale(irn, get_ia32_am_scale(load));
731 set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
732 set_ia32_op_type(irn, ia32_AddrModeD);
734 /* connect to Load memory and disconnect Load */
735 if (get_irn_arity(irn) == 5) {
737 set_irn_n(irn, 4, get_irn_n(load, 2));
738 set_irn_n(irn, 3, noreg_gp);
742 set_irn_n(irn, 3, get_irn_n(load, 2));
743 set_irn_n(irn, 2, noreg_gp);
746 /* connect the memory Proj of the Store to the op */
747 mem_proj = get_mem_proj(store);
748 set_Proj_pred(mem_proj, irn);
749 set_Proj_proj(mem_proj, 1);
752 else if (get_ia32_am_support(irn) & ia32_am_Source) {
753 /* There was no store, check if we still can optimize for source address mode */
756 } /* if (support AM Dest) */
757 else if (get_ia32_am_support(irn) & ia32_am_Source) {
758 /* op doesn't support am AM Dest -> check for AM Source */
762 /* normalize commutative ops */
763 if (node_is_comm(irn)) {
764 /* Assure that left operand is always a Load if there is one */
765 /* because non-commutative ops can only use Source AM if the */
766 /* left operand is a Load, so we only need to check the left */
767 /* operand afterwards. */
768 if (pred_is_specific_nodeblock(block, right, is_ia32_Ld)) {
769 set_irn_n(irn, 2, right);
770 set_irn_n(irn, 3, left);
778 /* optimize op -> Load iff Load is only used by this op */
779 /* and left operand is a Load which only used by this irn */
781 pred_is_specific_nodeblock(block, left, is_ia32_Ld) &&
782 (ia32_get_irn_n_edges(left) == 1))
784 left = get_Proj_pred(left);
786 addr_b = get_irn_n(left, 0);
787 addr_i = get_irn_n(left, 1);
789 /* set new base, index and attributes */
790 set_irn_n(irn, 0, addr_b);
791 set_irn_n(irn, 1, addr_i);
792 add_ia32_am_offs(irn, get_ia32_am_offs(left));
793 set_ia32_am_scale(irn, get_ia32_am_scale(left));
794 set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
795 set_ia32_op_type(irn, ia32_AddrModeS);
797 /* connect to Load memory */
798 if (get_irn_arity(irn) == 5) {
800 set_irn_n(irn, 4, get_irn_n(left, 2));
804 set_irn_n(irn, 3, get_irn_n(left, 2));
807 /* disconnect from Load */
808 set_irn_n(irn, 2, noreg_gp);
810 /* If Load has a memory Proj, connect it to the op */
811 mem_proj = get_mem_proj(left);
813 set_Proj_pred(mem_proj, irn);
814 set_Proj_proj(mem_proj, 1);