2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Matthias Braun, Christian Wuerdig
32 #include "firm_types.h"
44 #include "../benode.h"
45 #include "../besched.h"
46 #include "../bepeephole.h"
48 #include "ia32_new_nodes.h"
49 #include "ia32_optimize.h"
50 #include "bearch_ia32_t.h"
51 #include "gen_ia32_regalloc_if.h"
52 #include "ia32_common_transform.h"
53 #include "ia32_transform.h"
54 #include "ia32_dbg_stat.h"
55 #include "ia32_util.h"
56 #include "ia32_architecture.h"
58 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
60 static ia32_code_gen_t *cg;
62 static void copy_mark(const ir_node *old, ir_node *new)
64 if (is_ia32_is_reload(old))
65 set_ia32_is_reload(new);
66 if (is_ia32_is_spill(old))
67 set_ia32_is_spill(new);
68 if (is_ia32_is_remat(old))
69 set_ia32_is_remat(new);
72 typedef enum produces_flag_t {
79 * Return which usable flag the given node produces
81 * @param node the node to check
82 * @param pn the projection number of the used result
84 static produces_flag_t produces_test_flag(ir_node *node, int pn)
87 const ia32_immediate_attr_t *imm_attr;
89 if (!is_ia32_irn(node))
90 return produces_no_flag;
92 switch (get_ia32_irn_opcode(node)) {
107 assert(n_ia32_ShlD_count == n_ia32_ShrD_count);
108 count = get_irn_n(node, n_ia32_ShlD_count);
109 goto check_shift_amount;
114 assert(n_ia32_Shl_count == n_ia32_Shr_count
115 && n_ia32_Shl_count == n_ia32_Sar_count);
116 count = get_irn_n(node, n_ia32_Shl_count);
118 /* when shift count is zero the flags are not affected, so we can only
119 * do this for constants != 0 */
120 if (!is_ia32_Immediate(count))
121 return produces_no_flag;
123 imm_attr = get_ia32_immediate_attr_const(count);
124 if (imm_attr->symconst != NULL)
125 return produces_no_flag;
126 if ((imm_attr->offset & 0x1f) == 0)
127 return produces_no_flag;
131 return pn == pn_ia32_Mul_res_high ?
132 produces_flag_carry : produces_no_flag;
135 return produces_no_flag;
138 return pn == pn_ia32_res ?
139 produces_flag_zero : produces_no_flag;
143 * Replace Cmp(x, 0) by a Test(x, x)
145 static void peephole_ia32_Cmp(ir_node *const node)
148 ia32_immediate_attr_t const *imm;
154 ia32_attr_t const *attr;
158 arch_register_t const *reg;
159 ir_edge_t const *edge;
160 ir_edge_t const *tmp;
162 if (get_ia32_op_type(node) != ia32_Normal)
165 right = get_irn_n(node, n_ia32_Cmp_right);
166 if (!is_ia32_Immediate(right))
169 imm = get_ia32_immediate_attr_const(right);
170 if (imm->symconst != NULL || imm->offset != 0)
173 dbgi = get_irn_dbg_info(node);
174 block = get_nodes_block(node);
175 noreg = ia32_new_NoReg_gp(cg);
176 nomem = get_irg_no_mem(current_ir_graph);
177 op = get_irn_n(node, n_ia32_Cmp_left);
178 attr = get_irn_generic_attr(node);
179 ins_permuted = attr->data.ins_permuted;
180 cmp_unsigned = attr->data.cmp_unsigned;
182 if (is_ia32_Cmp(node)) {
183 test = new_bd_ia32_Test(dbgi, block, noreg, noreg, nomem,
184 op, op, ins_permuted, cmp_unsigned);
186 test = new_bd_ia32_Test8Bit(dbgi, block, noreg, noreg, nomem,
187 op, op, ins_permuted, cmp_unsigned);
189 set_ia32_ls_mode(test, get_ia32_ls_mode(node));
191 reg = arch_irn_get_register(node, pn_ia32_Cmp_eflags);
192 arch_irn_set_register(test, pn_ia32_Test_eflags, reg);
194 foreach_out_edge_safe(node, edge, tmp) {
195 ir_node *const user = get_edge_src_irn(edge);
198 exchange(user, test);
201 sched_add_before(node, test);
202 copy_mark(node, test);
203 be_peephole_exchange(node, test);
207 * Peephole optimization for Test instructions.
208 * - Remove the Test, if an appropriate flag was produced which is still live
209 * - Change a Test(x, c) to 8Bit, if 0 <= c < 256 (3 byte shorter opcode)
211 static void peephole_ia32_Test(ir_node *node)
213 ir_node *left = get_irn_n(node, n_ia32_Test_left);
214 ir_node *right = get_irn_n(node, n_ia32_Test_right);
216 assert(n_ia32_Test_left == n_ia32_Test8Bit_left
217 && n_ia32_Test_right == n_ia32_Test8Bit_right);
219 if (left == right) { /* we need a test for 0 */
220 ir_node *block = get_nodes_block(node);
221 int pn = pn_ia32_res;
225 const ir_edge_t *edge;
227 if (get_nodes_block(left) != block)
231 pn = get_Proj_proj(left);
232 left = get_Proj_pred(left);
235 /* walk schedule up and abort when we find left or some other node
236 * destroys the flags */
239 schedpoint = sched_prev(schedpoint);
240 if (schedpoint == left)
242 if (arch_irn_is(schedpoint, modify_flags))
244 if (schedpoint == block)
245 panic("couldn't find left");
248 /* make sure only Lg/Eq tests are used */
249 foreach_out_edge(node, edge) {
250 ir_node *user = get_edge_src_irn(edge);
251 int pnc = get_ia32_condcode(user);
253 if (pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) {
258 switch (produces_test_flag(left, pn)) {
259 case produces_flag_zero:
262 case produces_flag_carry:
263 foreach_out_edge(node, edge) {
264 ir_node *user = get_edge_src_irn(edge);
265 int pnc = get_ia32_condcode(user);
268 case pn_Cmp_Eq: pnc = pn_Cmp_Ge | ia32_pn_Cmp_unsigned; break;
269 case pn_Cmp_Lg: pnc = pn_Cmp_Lt | ia32_pn_Cmp_unsigned; break;
270 default: panic("unexpected pn");
272 set_ia32_condcode(user, pnc);
280 if (get_irn_mode(left) != mode_T) {
281 set_irn_mode(left, mode_T);
283 /* If there are other users, reroute them to result proj */
284 if (get_irn_n_edges(left) != 2) {
285 ir_node *res = new_r_Proj(left, mode_Iu, pn_ia32_res);
287 edges_reroute(left, res, current_ir_graph);
288 /* Reattach the result proj to left */
289 set_Proj_pred(res, left);
293 flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
294 flags_proj = new_r_Proj(left, flags_mode, pn_ia32_flags);
295 arch_set_irn_register(flags_proj, &ia32_flags_regs[REG_EFLAGS]);
297 assert(get_irn_mode(node) != mode_T);
299 be_peephole_exchange(node, flags_proj);
300 } else if (is_ia32_Immediate(right)) {
301 ia32_immediate_attr_t const *const imm = get_ia32_immediate_attr_const(right);
304 /* A test with a symconst is rather strange, but better safe than sorry */
305 if (imm->symconst != NULL)
308 offset = imm->offset;
309 if (get_ia32_op_type(node) == ia32_AddrModeS) {
310 ia32_attr_t *const attr = get_irn_generic_attr(node);
312 if ((offset & 0xFFFFFF00) == 0) {
313 /* attr->am_offs += 0; */
314 } else if ((offset & 0xFFFF00FF) == 0) {
315 ir_node *imm = ia32_create_Immediate(NULL, 0, offset >> 8);
316 set_irn_n(node, n_ia32_Test_right, imm);
318 } else if ((offset & 0xFF00FFFF) == 0) {
319 ir_node *imm = ia32_create_Immediate(NULL, 0, offset >> 16);
320 set_irn_n(node, n_ia32_Test_right, imm);
322 } else if ((offset & 0x00FFFFFF) == 0) {
323 ir_node *imm = ia32_create_Immediate(NULL, 0, offset >> 24);
324 set_irn_n(node, n_ia32_Test_right, imm);
329 } else if (offset < 256) {
330 arch_register_t const* const reg = arch_get_irn_register(left);
332 if (reg != &ia32_gp_regs[REG_EAX] &&
333 reg != &ia32_gp_regs[REG_EBX] &&
334 reg != &ia32_gp_regs[REG_ECX] &&
335 reg != &ia32_gp_regs[REG_EDX]) {
342 /* Technically we should build a Test8Bit because of the register
343 * constraints, but nobody changes registers at this point anymore. */
344 set_ia32_ls_mode(node, mode_Bu);
349 * AMD Athlon works faster when RET is not destination of
350 * conditional jump or directly preceded by other jump instruction.
351 * Can be avoided by placing a Rep prefix before the return.
353 static void peephole_ia32_Return(ir_node *node)
355 ir_node *block, *irn;
357 if (!ia32_cg_config.use_pad_return)
360 block = get_nodes_block(node);
362 /* check if this return is the first on the block */
363 sched_foreach_reverse_from(node, irn) {
364 switch (get_irn_opcode(irn)) {
366 /* the return node itself, ignore */
371 /* ignore no code generated */
374 /* arg, IncSP 0 nodes might occur, ignore these */
375 if (be_get_IncSP_offset(irn) == 0)
385 /* ensure, that the 3 byte return is generated */
386 be_Return_set_emit_pop(node, 1);
389 /* only optimize up to 48 stores behind IncSPs */
390 #define MAXPUSH_OPTIMIZE 48
393 * Tries to create Push's from IncSP, Store combinations.
394 * The Stores are replaced by Push's, the IncSP is modified
395 * (possibly into IncSP 0, but not removed).
397 static void peephole_IncSP_Store_to_push(ir_node *irn)
403 ir_node *stores[MAXPUSH_OPTIMIZE];
408 ir_node *first_push = NULL;
409 ir_edge_t const *edge;
410 ir_edge_t const *next;
412 memset(stores, 0, sizeof(stores));
414 assert(be_is_IncSP(irn));
416 inc_ofs = be_get_IncSP_offset(irn);
421 * We first walk the schedule after the IncSP node as long as we find
422 * suitable Stores that could be transformed to a Push.
423 * We save them into the stores array which is sorted by the frame offset/4
424 * attached to the node
427 for (node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
432 /* it has to be a Store */
433 if (!is_ia32_Store(node))
436 /* it has to use our sp value */
437 if (get_irn_n(node, n_ia32_base) != irn)
439 /* Store has to be attached to NoMem */
440 mem = get_irn_n(node, n_ia32_mem);
444 /* unfortunately we can't support the full AMs possible for push at the
445 * moment. TODO: fix this */
446 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
449 offset = get_ia32_am_offs_int(node);
450 /* we should NEVER access uninitialized stack BELOW the current SP */
453 /* storing at half-slots is bad */
454 if ((offset & 3) != 0)
457 if (inc_ofs - 4 < offset || offset >= MAXPUSH_OPTIMIZE * 4)
459 storeslot = offset >> 2;
461 /* storing into the same slot twice is bad (and shouldn't happen...) */
462 if (stores[storeslot] != NULL)
465 stores[storeslot] = node;
466 if (storeslot > maxslot)
472 for (i = -1; i < maxslot; ++i) {
473 if (stores[i + 1] == NULL)
477 /* walk through the Stores and create Pushs for them */
478 block = get_nodes_block(irn);
479 spmode = get_irn_mode(irn);
481 for (; i >= 0; --i) {
482 const arch_register_t *spreg;
484 ir_node *val, *mem, *mem_proj;
485 ir_node *store = stores[i];
486 ir_node *noreg = ia32_new_NoReg_gp(cg);
488 val = get_irn_n(store, n_ia32_unary_op);
489 mem = get_irn_n(store, n_ia32_mem);
490 spreg = arch_get_irn_register(curr_sp);
492 push = new_bd_ia32_Push(get_irn_dbg_info(store), block, noreg, noreg, mem, val, curr_sp);
493 copy_mark(store, push);
495 if (first_push == NULL)
498 sched_add_after(skip_Proj(curr_sp), push);
500 /* create stackpointer Proj */
501 curr_sp = new_r_Proj(push, spmode, pn_ia32_Push_stack);
502 arch_set_irn_register(curr_sp, spreg);
504 /* create memory Proj */
505 mem_proj = new_r_Proj(push, mode_M, pn_ia32_Push_M);
507 /* use the memproj now */
508 be_peephole_exchange(store, mem_proj);
513 foreach_out_edge_safe(irn, edge, next) {
514 ir_node *const src = get_edge_src_irn(edge);
515 int const pos = get_edge_src_pos(edge);
517 if (src == first_push)
520 set_irn_n(src, pos, curr_sp);
523 be_set_IncSP_offset(irn, inc_ofs);
527 static void peephole_store_incsp(ir_node *store)
538 ir_node *am_base = get_irn_n(store, n_ia32_Store_base);
539 if (!be_is_IncSP(am_base)
540 || get_nodes_block(am_base) != get_nodes_block(store))
542 mem = get_irn_n(store, n_ia32_Store_mem);
543 if (!is_ia32_NoReg_GP(get_irn_n(store, n_ia32_Store_index))
547 int incsp_offset = be_get_IncSP_offset(am_base);
548 if (incsp_offset <= 0)
551 /* we have to be at offset 0 */
552 int my_offset = get_ia32_am_offs_int(store);
553 if (my_offset != 0) {
554 /* TODO here: find out wether there is a store with offset 0 before
555 * us and wether we can move it down to our place */
558 ir_mode *ls_mode = get_ia32_ls_mode(store);
559 int my_store_size = get_mode_size_bytes(ls_mode);
561 if (my_offset + my_store_size > incsp_offset)
564 /* correctness checking:
565 - noone else must write to that stackslot
566 (because after translation incsp won't allocate it anymore)
568 sched_foreach_reverse_from(store, node) {
574 /* make sure noone else can use the space on the stack */
575 arity = get_irn_arity(node);
576 for (i = 0; i < arity; ++i) {
577 ir_node *pred = get_irn_n(node, i);
581 if (i == n_ia32_base &&
582 (get_ia32_op_type(node) == ia32_AddrModeS
583 || get_ia32_op_type(node) == ia32_AddrModeD)) {
584 int node_offset = get_ia32_am_offs_int(node);
585 ir_mode *node_ls_mode = get_ia32_ls_mode(node);
586 int node_size = get_mode_size_bytes(node_ls_mode);
587 /* overlapping with our position? abort */
588 if (node_offset < my_offset + my_store_size
589 && node_offset + node_size >= my_offset)
591 /* otherwise it's fine */
595 /* strange use of esp: abort */
600 /* all ok, change to push */
601 dbgi = get_irn_dbg_info(store);
602 block = get_nodes_block(store);
603 noreg = ia32_new_NoReg_gp(cg);
604 val = get_irn_n(store, n_ia32_Store_val);
606 push = new_bd_ia32_Push(dbgi, block, noreg, noreg, mem,
608 create_push(dbgi, current_ir_graph, block, am_base, store);
613 * Return true if a mode can be stored in the GP register set
615 static inline int mode_needs_gp_reg(ir_mode *mode)
617 if (mode == mode_fpcw)
619 if (get_mode_size_bits(mode) > 32)
621 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
625 * Tries to create Pops from Load, IncSP combinations.
626 * The Loads are replaced by Pops, the IncSP is modified
627 * (possibly into IncSP 0, but not removed).
629 static void peephole_Load_IncSP_to_pop(ir_node *irn)
631 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
632 int i, maxslot, inc_ofs, ofs;
633 ir_node *node, *pred_sp, *block;
634 ir_node *loads[MAXPUSH_OPTIMIZE];
636 unsigned regmask = 0;
637 unsigned copymask = ~0;
639 memset(loads, 0, sizeof(loads));
640 assert(be_is_IncSP(irn));
642 inc_ofs = -be_get_IncSP_offset(irn);
647 * We first walk the schedule before the IncSP node as long as we find
648 * suitable Loads that could be transformed to a Pop.
649 * We save them into the stores array which is sorted by the frame offset/4
650 * attached to the node
653 pred_sp = be_get_IncSP_pred(irn);
654 for (node = sched_prev(irn); !sched_is_end(node); node = sched_prev(node)) {
657 const arch_register_t *sreg, *dreg;
659 /* it has to be a Load */
660 if (!is_ia32_Load(node)) {
661 if (be_is_Copy(node)) {
662 if (!mode_needs_gp_reg(get_irn_mode(node))) {
663 /* not a GP copy, ignore */
666 dreg = arch_get_irn_register(node);
667 sreg = arch_get_irn_register(be_get_Copy_op(node));
668 if (regmask & copymask & (1 << sreg->index)) {
671 if (regmask & copymask & (1 << dreg->index)) {
674 /* we CAN skip Copies if neither the destination nor the source
675 * is not in our regmask, ie none of our future Pop will overwrite it */
676 regmask |= (1 << dreg->index) | (1 << sreg->index);
677 copymask &= ~((1 << dreg->index) | (1 << sreg->index));
683 /* we can handle only GP loads */
684 if (!mode_needs_gp_reg(get_ia32_ls_mode(node)))
687 /* it has to use our predecessor sp value */
688 if (get_irn_n(node, n_ia32_base) != pred_sp) {
689 /* it would be ok if this load does not use a Pop result,
690 * but we do not check this */
694 /* should have NO index */
695 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
698 offset = get_ia32_am_offs_int(node);
699 /* we should NEVER access uninitialized stack BELOW the current SP */
702 /* storing at half-slots is bad */
703 if ((offset & 3) != 0)
706 if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
708 /* ignore those outside the possible windows */
709 if (offset > inc_ofs - 4)
711 loadslot = offset >> 2;
713 /* loading from the same slot twice is bad (and shouldn't happen...) */
714 if (loads[loadslot] != NULL)
717 dreg = arch_irn_get_register(node, pn_ia32_Load_res);
718 if (regmask & (1 << dreg->index)) {
719 /* this register is already used */
722 regmask |= 1 << dreg->index;
724 loads[loadslot] = node;
725 if (loadslot > maxslot)
732 /* find the first slot */
733 for (i = maxslot; i >= 0; --i) {
734 ir_node *load = loads[i];
740 ofs = inc_ofs - (maxslot + 1) * 4;
743 /* create a new IncSP if needed */
744 block = get_nodes_block(irn);
747 pred_sp = be_new_IncSP(esp, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
748 sched_add_before(irn, pred_sp);
751 /* walk through the Loads and create Pops for them */
752 for (++i; i <= maxslot; ++i) {
753 ir_node *load = loads[i];
755 const ir_edge_t *edge, *tmp;
756 const arch_register_t *reg;
758 mem = get_irn_n(load, n_ia32_mem);
759 reg = arch_irn_get_register(load, pn_ia32_Load_res);
761 pop = new_bd_ia32_Pop(get_irn_dbg_info(load), block, mem, pred_sp);
762 arch_irn_set_register(pop, pn_ia32_Load_res, reg);
764 copy_mark(load, pop);
766 /* create stackpointer Proj */
767 pred_sp = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack);
768 arch_set_irn_register(pred_sp, esp);
770 sched_add_before(irn, pop);
773 foreach_out_edge_safe(load, edge, tmp) {
774 ir_node *proj = get_edge_src_irn(edge);
776 set_Proj_pred(proj, pop);
779 /* we can remove the Load now */
784 be_set_IncSP_offset(irn, -ofs);
785 be_set_IncSP_pred(irn, pred_sp);
790 * Find a free GP register if possible, else return NULL.
792 static const arch_register_t *get_free_gp_reg(void)
796 for (i = 0; i < N_ia32_gp_REGS; ++i) {
797 const arch_register_t *reg = &ia32_gp_regs[i];
798 if (arch_register_type_is(reg, ignore))
801 if (be_peephole_get_value(CLASS_ia32_gp, i) == NULL)
802 return &ia32_gp_regs[i];
809 * Creates a Pop instruction before the given schedule point.
811 * @param dbgi debug info
812 * @param block the block
813 * @param stack the previous stack value
814 * @param schedpoint the new node is added before this node
815 * @param reg the register to pop
817 * @return the new stack value
819 static ir_node *create_pop(dbg_info *dbgi, ir_node *block,
820 ir_node *stack, ir_node *schedpoint,
821 const arch_register_t *reg)
823 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
829 pop = new_bd_ia32_Pop(dbgi, block, new_NoMem(), stack);
831 stack = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack);
832 arch_set_irn_register(stack, esp);
833 val = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_res);
834 arch_set_irn_register(val, reg);
836 sched_add_before(schedpoint, pop);
839 keep = be_new_Keep(block, 1, in);
840 sched_add_before(schedpoint, keep);
846 * Creates a Push instruction before the given schedule point.
848 * @param dbgi debug info
849 * @param block the block
850 * @param stack the previous stack value
851 * @param schedpoint the new node is added before this node
852 * @param reg the register to pop
854 * @return the new stack value
856 static ir_node *create_push(dbg_info *dbgi, ir_node *block,
857 ir_node *stack, ir_node *schedpoint)
859 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
861 ir_node *val = ia32_new_NoReg_gp(cg);
862 ir_node *noreg = ia32_new_NoReg_gp(cg);
863 ir_node *nomem = new_NoMem();
864 ir_node *push = new_bd_ia32_Push(dbgi, block, noreg, noreg, nomem, val, stack);
865 sched_add_before(schedpoint, push);
867 stack = new_r_Proj(push, mode_Iu, pn_ia32_Push_stack);
868 arch_set_irn_register(stack, esp);
874 * Optimize an IncSp by replacing it with Push/Pop.
876 static void peephole_be_IncSP(ir_node *node)
878 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
879 const arch_register_t *reg;
885 /* first optimize incsp->incsp combinations */
886 node = be_peephole_IncSP_IncSP(node);
888 /* transform IncSP->Store combinations to Push where possible */
889 peephole_IncSP_Store_to_push(node);
891 /* transform Load->IncSP combinations to Pop where possible */
892 peephole_Load_IncSP_to_pop(node);
894 if (arch_get_irn_register(node) != esp)
897 /* replace IncSP -4 by Pop freereg when possible */
898 offset = be_get_IncSP_offset(node);
899 if ((offset != -8 || ia32_cg_config.use_add_esp_8) &&
900 (offset != -4 || ia32_cg_config.use_add_esp_4) &&
901 (offset != +4 || ia32_cg_config.use_sub_esp_4) &&
902 (offset != +8 || ia32_cg_config.use_sub_esp_8))
906 /* we need a free register for pop */
907 reg = get_free_gp_reg();
911 dbgi = get_irn_dbg_info(node);
912 block = get_nodes_block(node);
913 stack = be_get_IncSP_pred(node);
915 stack = create_pop(dbgi, block, stack, node, reg);
918 stack = create_pop(dbgi, block, stack, node, reg);
921 dbgi = get_irn_dbg_info(node);
922 block = get_nodes_block(node);
923 stack = be_get_IncSP_pred(node);
924 stack = create_push(dbgi, block, stack, node);
927 stack = create_push(dbgi, block, stack, node);
931 be_peephole_exchange(node, stack);
935 * Peephole optimisation for ia32_Const's
937 static void peephole_ia32_Const(ir_node *node)
939 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
940 const arch_register_t *reg;
945 /* try to transform a mov 0, reg to xor reg reg */
946 if (attr->offset != 0 || attr->symconst != NULL)
948 if (ia32_cg_config.use_mov_0)
950 /* xor destroys the flags, so no-one must be using them */
951 if (be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
954 reg = arch_get_irn_register(node);
955 assert(be_peephole_get_reg_value(reg) == NULL);
957 /* create xor(produceval, produceval) */
958 block = get_nodes_block(node);
959 dbgi = get_irn_dbg_info(node);
960 xor = new_bd_ia32_Xor0(dbgi, block);
961 arch_set_irn_register(xor, reg);
963 sched_add_before(node, xor);
965 copy_mark(node, xor);
966 be_peephole_exchange(node, xor);
969 static inline int is_noreg(ia32_code_gen_t *cg, const ir_node *node)
971 return node == cg->noreg_gp;
974 ir_node *ia32_immediate_from_long(long val)
976 ir_graph *irg = current_ir_graph;
977 ir_node *start_block = get_irg_start_block(irg);
979 = new_bd_ia32_Immediate(NULL, start_block, NULL, 0, 0, val);
980 arch_set_irn_register(immediate, &ia32_gp_regs[REG_GP_NOREG]);
985 static ir_node *create_immediate_from_am(const ir_node *node)
987 ir_node *block = get_nodes_block(node);
988 int offset = get_ia32_am_offs_int(node);
989 int sc_sign = is_ia32_am_sc_sign(node);
990 const ia32_attr_t *attr = get_ia32_attr_const(node);
991 int sc_no_pic_adjust = attr->data.am_sc_no_pic_adjust;
992 ir_entity *entity = get_ia32_am_sc(node);
995 res = new_bd_ia32_Immediate(NULL, block, entity, sc_sign, sc_no_pic_adjust,
997 arch_set_irn_register(res, &ia32_gp_regs[REG_GP_NOREG]);
1001 static int is_am_one(const ir_node *node)
1003 int offset = get_ia32_am_offs_int(node);
1004 ir_entity *entity = get_ia32_am_sc(node);
1006 return offset == 1 && entity == NULL;
1009 static int is_am_minus_one(const ir_node *node)
1011 int offset = get_ia32_am_offs_int(node);
1012 ir_entity *entity = get_ia32_am_sc(node);
1014 return offset == -1 && entity == NULL;
1018 * Transforms a LEA into an Add or SHL if possible.
1020 static void peephole_ia32_Lea(ir_node *node)
1024 const arch_register_t *base_reg;
1025 const arch_register_t *index_reg;
1026 const arch_register_t *out_reg;
1037 assert(is_ia32_Lea(node));
1039 /* we can only do this if it is allowed to clobber the flags */
1040 if (be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
1043 base = get_irn_n(node, n_ia32_Lea_base);
1044 index = get_irn_n(node, n_ia32_Lea_index);
1046 if (is_noreg(cg, base)) {
1050 base_reg = arch_get_irn_register(base);
1052 if (is_noreg(cg, index)) {
1056 index_reg = arch_get_irn_register(index);
1059 if (base == NULL && index == NULL) {
1060 /* we shouldn't construct these in the first place... */
1061 #ifdef DEBUG_libfirm
1062 ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
1067 out_reg = arch_get_irn_register(node);
1068 scale = get_ia32_am_scale(node);
1069 assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
1070 /* check if we have immediates values (frame entities should already be
1071 * expressed in the offsets) */
1072 if (get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
1078 /* we can transform leas where the out register is the same as either the
1079 * base or index register back to an Add or Shl */
1080 if (out_reg == base_reg) {
1081 if (index == NULL) {
1082 #ifdef DEBUG_libfirm
1083 if (!has_immediates) {
1084 ir_fprintf(stderr, "Optimisation warning: found lea which is "
1089 goto make_add_immediate;
1091 if (scale == 0 && !has_immediates) {
1096 /* can't create an add */
1098 } else if (out_reg == index_reg) {
1100 if (has_immediates && scale == 0) {
1102 goto make_add_immediate;
1103 } else if (!has_immediates && scale > 0) {
1105 op2 = ia32_immediate_from_long(scale);
1107 } else if (!has_immediates) {
1108 #ifdef DEBUG_libfirm
1109 ir_fprintf(stderr, "Optimisation warning: found lea which is "
1113 } else if (scale == 0 && !has_immediates) {
1118 /* can't create an add */
1121 /* can't create an add */
1126 if (ia32_cg_config.use_incdec) {
1127 if (is_am_one(node)) {
1128 dbgi = get_irn_dbg_info(node);
1129 block = get_nodes_block(node);
1130 res = new_bd_ia32_Inc(dbgi, block, op1);
1131 arch_set_irn_register(res, out_reg);
1134 if (is_am_minus_one(node)) {
1135 dbgi = get_irn_dbg_info(node);
1136 block = get_nodes_block(node);
1137 res = new_bd_ia32_Dec(dbgi, block, op1);
1138 arch_set_irn_register(res, out_reg);
1142 op2 = create_immediate_from_am(node);
1145 dbgi = get_irn_dbg_info(node);
1146 block = get_nodes_block(node);
1147 noreg = ia32_new_NoReg_gp(cg);
1148 nomem = new_NoMem();
1149 res = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, op1, op2);
1150 arch_set_irn_register(res, out_reg);
1151 set_ia32_commutative(res);
1155 dbgi = get_irn_dbg_info(node);
1156 block = get_nodes_block(node);
1157 noreg = ia32_new_NoReg_gp(cg);
1158 nomem = new_NoMem();
1159 res = new_bd_ia32_Shl(dbgi, block, op1, op2);
1160 arch_set_irn_register(res, out_reg);
1164 SET_IA32_ORIG_NODE(res, node);
1166 /* add new ADD/SHL to schedule */
1167 DBG_OPT_LEA2ADD(node, res);
1169 /* exchange the Add and the LEA */
1170 sched_add_before(node, res);
1171 copy_mark(node, res);
1172 be_peephole_exchange(node, res);
1176 * Split a Imul mem, imm into a Load mem and Imul reg, imm if possible.
1178 static void peephole_ia32_Imul_split(ir_node *imul)
1180 const ir_node *right = get_irn_n(imul, n_ia32_IMul_right);
1181 const arch_register_t *reg;
1184 if (!is_ia32_Immediate(right) || get_ia32_op_type(imul) != ia32_AddrModeS) {
1185 /* no memory, imm form ignore */
1188 /* we need a free register */
1189 reg = get_free_gp_reg();
1193 /* fine, we can rebuild it */
1194 res = turn_back_am(imul);
1195 arch_set_irn_register(res, reg);
1199 * Replace xorps r,r and xorpd r,r by pxor r,r
1201 static void peephole_ia32_xZero(ir_node *xor)
1203 set_irn_op(xor, op_ia32_xPzero);
1207 * Replace 16bit sign extension from ax to eax by shorter cwtl
1209 static void peephole_ia32_Conv_I2I(ir_node *node)
1211 const arch_register_t *eax = &ia32_gp_regs[REG_EAX];
1212 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1213 ir_node *val = get_irn_n(node, n_ia32_Conv_I2I_val);
1218 if (get_mode_size_bits(smaller_mode) != 16 ||
1219 !mode_is_signed(smaller_mode) ||
1220 eax != arch_get_irn_register(val) ||
1221 eax != arch_irn_get_register(node, pn_ia32_Conv_I2I_res))
1224 dbgi = get_irn_dbg_info(node);
1225 block = get_nodes_block(node);
1226 cwtl = new_bd_ia32_Cwtl(dbgi, block, val);
1227 arch_set_irn_register(cwtl, eax);
1228 sched_add_before(node, cwtl);
1229 be_peephole_exchange(node, cwtl);
1233 * Register a peephole optimisation function.
1235 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func)
1237 assert(op->ops.generic == NULL);
1238 op->ops.generic = (op_func)func;
1241 /* Perform peephole-optimizations. */
1242 void ia32_peephole_optimization(ia32_code_gen_t *new_cg)
1246 /* register peephole optimisations */
1247 clear_irp_opcodes_generic_func();
1248 register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
1249 register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
1250 register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
1251 register_peephole_optimisation(op_ia32_Cmp, peephole_ia32_Cmp);
1252 register_peephole_optimisation(op_ia32_Cmp8Bit, peephole_ia32_Cmp);
1253 register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
1254 register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test);
1255 register_peephole_optimisation(op_be_Return, peephole_ia32_Return);
1256 if (! ia32_cg_config.use_imul_mem_imm32)
1257 register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split);
1258 if (ia32_cg_config.use_pxor)
1259 register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero);
1260 if (ia32_cg_config.use_short_sex_eax)
1261 register_peephole_optimisation(op_ia32_Conv_I2I, peephole_ia32_Conv_I2I);
1263 be_peephole_opt(cg->birg);
1267 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
1268 * all it's Projs are removed as well.
1269 * @param irn The irn to be removed from schedule
1271 static inline void try_kill(ir_node *node)
1273 if (get_irn_mode(node) == mode_T) {
1274 const ir_edge_t *edge, *next;
1275 foreach_out_edge_safe(node, edge, next) {
1276 ir_node *proj = get_edge_src_irn(edge);
1281 if (get_irn_n_edges(node) != 0)
1284 if (sched_is_scheduled(node)) {
1291 static void optimize_conv_store(ir_node *node)
1296 ir_mode *store_mode;
1298 if (!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
1301 assert(n_ia32_Store_val == n_ia32_Store8Bit_val);
1302 pred_proj = get_irn_n(node, n_ia32_Store_val);
1303 if (is_Proj(pred_proj)) {
1304 pred = get_Proj_pred(pred_proj);
1308 if (!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1310 if (get_ia32_op_type(pred) != ia32_Normal)
1313 /* the store only stores the lower bits, so we only need the conv
1314 * it it shrinks the mode */
1315 conv_mode = get_ia32_ls_mode(pred);
1316 store_mode = get_ia32_ls_mode(node);
1317 if (get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
1320 set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val));
1321 if (get_irn_n_edges(pred_proj) == 0) {
1322 kill_node(pred_proj);
1323 if (pred != pred_proj)
1328 static void optimize_load_conv(ir_node *node)
1330 ir_node *pred, *predpred;
1334 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1337 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1338 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
1342 predpred = get_Proj_pred(pred);
1343 if (!is_ia32_Load(predpred))
1346 /* the load is sign extending the upper bits, so we only need the conv
1347 * if it shrinks the mode */
1348 load_mode = get_ia32_ls_mode(predpred);
1349 conv_mode = get_ia32_ls_mode(node);
1350 if (get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
1353 if (get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
1354 /* change the load if it has only 1 user */
1355 if (get_irn_n_edges(pred) == 1) {
1357 if (get_mode_sign(conv_mode)) {
1358 newmode = find_signed_mode(load_mode);
1360 newmode = find_unsigned_mode(load_mode);
1362 assert(newmode != NULL);
1363 set_ia32_ls_mode(predpred, newmode);
1365 /* otherwise we have to keep the conv */
1371 exchange(node, pred);
1374 static void optimize_conv_conv(ir_node *node)
1376 ir_node *pred_proj, *pred, *result_conv;
1377 ir_mode *pred_mode, *conv_mode;
1381 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1384 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1385 pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
1386 if (is_Proj(pred_proj))
1387 pred = get_Proj_pred(pred_proj);
1391 if (!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1394 /* we know that after a conv, the upper bits are sign extended
1395 * so we only need the 2nd conv if it shrinks the mode */
1396 conv_mode = get_ia32_ls_mode(node);
1397 conv_mode_bits = get_mode_size_bits(conv_mode);
1398 pred_mode = get_ia32_ls_mode(pred);
1399 pred_mode_bits = get_mode_size_bits(pred_mode);
1401 if (conv_mode_bits == pred_mode_bits
1402 && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1403 result_conv = pred_proj;
1404 } else if (conv_mode_bits <= pred_mode_bits) {
1405 /* if 2nd conv is smaller then first conv, then we can always take the
1407 if (get_irn_n_edges(pred_proj) == 1) {
1408 result_conv = pred_proj;
1409 set_ia32_ls_mode(pred, conv_mode);
1411 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1412 if (get_mode_size_bits(conv_mode) == 8) {
1413 set_irn_op(pred, op_ia32_Conv_I2I8Bit);
1414 set_ia32_in_req_all(pred, get_ia32_in_req_all(node));
1417 /* we don't want to end up with 2 loads, so we better do nothing */
1418 if (get_irn_mode(pred) == mode_T) {
1422 result_conv = exact_copy(pred);
1423 set_ia32_ls_mode(result_conv, conv_mode);
1425 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1426 if (get_mode_size_bits(conv_mode) == 8) {
1427 set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
1428 set_ia32_in_req_all(result_conv, get_ia32_in_req_all(node));
1432 /* if both convs have the same sign, then we can take the smaller one */
1433 if (get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1434 result_conv = pred_proj;
1436 /* no optimisation possible if smaller conv is sign-extend */
1437 if (mode_is_signed(pred_mode)) {
1440 /* we can take the smaller conv if it is unsigned */
1441 result_conv = pred_proj;
1445 /* Some user (like Phis) won't be happy if we change the mode. */
1446 set_irn_mode(result_conv, get_irn_mode(node));
1449 exchange(node, result_conv);
1451 if (get_irn_n_edges(pred_proj) == 0) {
1452 kill_node(pred_proj);
1453 if (pred != pred_proj)
1456 optimize_conv_conv(result_conv);
1459 static void optimize_node(ir_node *node, void *env)
1463 optimize_load_conv(node);
1464 optimize_conv_store(node);
1465 optimize_conv_conv(node);
1469 * Performs conv and address mode optimization.
1471 void ia32_optimize_graph(ia32_code_gen_t *cg)
1473 irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg);
1476 be_dump(cg->irg, "-opt", dump_ir_block_graph_sched);
1479 void ia32_init_optimize(void)
1481 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");