8 #include "firm_types.h"
15 #include "../benode_t.h"
16 #include "../besched_t.h"
18 #include "ia32_new_nodes.h"
19 #include "bearch_ia32_t.h"
20 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
23 #define is_NoMem(irn) (get_irn_op(irn) == op_NoMem)
25 static int be_is_NoReg(be_abi_irg_t *babi, const ir_node *irn) {
26 if (be_abi_get_callee_save_irn(babi, &ia32_gp_regs[REG_XXX]) == irn ||
27 be_abi_get_callee_save_irn(babi, &ia32_fp_regs[REG_XXXX]) == irn)
36 * creates a unique ident by adding a number to a tag
38 * @param tag the tag string, must contain a %d if a number
41 static ident *unique_id(const char *tag)
43 static unsigned id = 0;
46 snprintf(str, sizeof(str), tag, ++id);
47 return new_id_from_str(str);
53 * Transforms a SymConst.
55 * @param mod the debug module
56 * @param block the block the new node should belong to
57 * @param node the ir SymConst node
58 * @param mode mode of the SymConst
59 * @return the created ia32 Const node
61 static ir_node *gen_SymConst(ia32_transform_env_t *env) {
63 dbg_info *dbg = env->dbg;
64 ir_mode *mode = env->mode;
65 ir_graph *irg = env->irg;
66 ir_node *block = env->block;
68 cnst = new_rd_ia32_Const(dbg, irg, block, mode);
69 set_ia32_Const_attr(cnst, env->irn);
74 * Get a primitive type for a mode.
76 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
78 pmap_entry *e = pmap_find(types, mode);
83 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
84 res = new_type_primitive(new_id_from_str(buf), mode);
85 pmap_insert(types, mode, res);
93 * Get an entity that is initialized with a tarval
95 static entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
97 tarval *tv = get_Const_tarval(cnst);
98 pmap_entry *e = pmap_find(cg->tv_ent, tv);
103 ir_mode *mode = get_irn_mode(cnst);
104 ir_type *tp = get_Const_type(cnst);
105 if (tp == firm_unknown_type)
106 tp = get_prim_type(cg->types, mode);
108 res = new_entity(get_glob_type(), unique_id("ia32FloatCnst_%u"), tp);
110 set_entity_ld_ident(res, get_entity_ident(res));
111 set_entity_visibility(res, visibility_local);
112 set_entity_variability(res, variability_constant);
113 set_entity_allocation(res, allocation_static);
115 /* we create a new entity here: It's initialization must resist on the
117 rem = current_ir_graph;
118 current_ir_graph = get_const_code_irg();
119 set_atomic_ent_value(res, new_Const_type(tv, tp));
120 current_ir_graph = rem;
128 * Transforms a Const.
130 * @param mod the debug module
131 * @param block the block the new node should belong to
132 * @param node the ir Const node
133 * @param mode mode of the Const
134 * @return the created ia32 Const node
136 static ir_node *gen_Const(ia32_transform_env_t *env) {
139 ir_graph *irg = env->irg;
140 ir_node *block = env->block;
141 ir_node *node = env->irn;
142 dbg_info *dbg = env->dbg;
143 ir_mode *mode = env->mode;
145 if (mode_is_float(mode)) {
146 sym.entity_p = get_entity_for_tv(env->cg, node);
148 cnst = new_rd_SymConst(dbg, irg, block, sym, symconst_addr_ent);
150 cnst = gen_SymConst(env);
153 cnst = new_rd_ia32_Const(dbg, irg, block, get_irn_mode(node));
154 set_ia32_Const_attr(cnst, node);
162 * Transforms (all) Const's into ia32_Const and places them in the
163 * block where they are used (or in the cfg-pred Block in case of Phi's).
164 * Additionally all mode_P nodes are changed into mode_Is nodes.
166 void ia32_place_consts_set_modes(ir_node *irn, void *env) {
167 ia32_code_gen_t *cg = env;
168 ia32_transform_env_t tenv;
170 ir_node *pred, *cnst;
177 mode = get_irn_mode(irn);
179 /* transform all mode_P nodes into mode_Is nodes */
180 if (mode == mode_P) {
181 set_irn_mode(irn, mode_Is);
185 tenv.block = get_nodes_block(irn);
190 /* Loop over all predecessors and check for Sym/Const nodes */
191 for (i = get_irn_arity(irn) - 1; i >= 0; --i) {
192 pred = get_irn_n(irn, i);
194 opc = get_irn_opcode(pred);
196 tenv.mode = get_irn_mode(pred);
197 tenv.dbg = get_irn_dbg_info(pred);
199 /* If it's a Phi, then we need to create the */
200 /* new Const in it's predecessor block */
202 tenv.block = get_Block_cfgpred_block(get_nodes_block(irn), i);
205 /* put the const into the block where the original const was */
206 if (! cg->opt.placecnst) {
207 tenv.block = get_nodes_block(pred);
212 cnst = gen_Const(&tenv);
215 cnst = gen_SymConst(&tenv);
221 /* if we found a const, then set it */
223 set_irn_n(irn, i, cnst);
229 /******************************************************************
231 * /\ | | | | | \/ | | |
232 * / \ __| | __| |_ __ ___ ___ ___| \ / | ___ __| | ___
233 * / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \
234 * / ____ \ (_| | (_| | | | __/\__ \__ \ | | | (_) | (_| | __/
235 * /_/ \_\__,_|\__,_|_| \___||___/___/_| |_|\___/ \__,_|\___|
237 ******************************************************************/
239 static int node_is_comm(const ir_node *irn) {
240 return is_ia32_irn(irn) ? is_ia32_commutative(irn) : 0;
243 static int ia32_get_irn_n_edges(const ir_node *irn) {
244 const ir_edge_t *edge;
247 foreach_out_edge(irn, edge) {
255 * Returns the first mode_M Proj connected to irn.
257 static ir_node *get_mem_proj(const ir_node *irn) {
258 const ir_edge_t *edge;
261 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
263 foreach_out_edge(irn, edge) {
264 src = get_edge_src_irn(edge);
266 assert(is_Proj(src) && "Proj expected");
268 if (get_irn_mode(src) == mode_M)
276 * Returns the first Proj with mode != mode_M connected to irn.
278 static ir_node *get_res_proj(const ir_node *irn) {
279 const ir_edge_t *edge;
282 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
284 foreach_out_edge(irn, edge) {
285 src = get_edge_src_irn(edge);
287 assert(is_Proj(src) && "Proj expected");
289 if (get_irn_mode(src) != mode_M)
297 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor.
299 * @param pred The node to be checked
300 * @param is_op_func The check-function
301 * @return 1 if conditions are fulfilled, 0 otherwise
303 static int pred_is_specific_node(const ir_node *pred, int (*is_op_func)(const ir_node *n)) {
304 if (is_Proj(pred) && is_op_func(get_Proj_pred(pred))) {
312 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor
313 * and if the predecessor is in block bl.
315 * @param bl The block
316 * @param pred The node to be checked
317 * @param is_op_func The check-function
318 * @return 1 if conditions are fulfilled, 0 otherwise
320 static int pred_is_specific_nodeblock(const ir_node *bl, const ir_node *pred,
321 int (*is_op_func)(const ir_node *n))
324 pred = get_Proj_pred(pred);
325 if ((bl == get_nodes_block(pred)) && is_op_func(pred)) {
336 * Checks if irn is a candidate for address calculation or address mode.
338 * address calculation (AC):
339 * - none of the operand must be a Load within the same block OR
340 * - all Loads must have more than one user OR
341 * - the irn has a frame entity (it's a former FrameAddr)
344 * - at least one operand has to be a Load within the same block AND
345 * - the load must not have other users than the irn AND
346 * - the irn must not have a frame entity set
348 * @param block The block the Loads must/not be in
349 * @param irn The irn to check
350 * @param check_addr 1 if to check for address calculation, 0 otherwise
351 * return 1 if irn is a candidate for AC or AM, 0 otherwise
353 static int is_candidate(const ir_node *block, const ir_node *irn, int check_addr) {
355 int n, is_cand = check_addr;
357 in = get_irn_n(irn, 2);
359 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
360 n = ia32_get_irn_n_edges(in);
361 is_cand = check_addr ? (n == 1 ? 0 : is_cand) : (n == 1 ? 1 : is_cand);
364 in = get_irn_n(irn, 3);
366 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
367 n = ia32_get_irn_n_edges(in);
368 is_cand = check_addr ? (n == 1 ? 0 : is_cand) : (n == 1 ? 1 : is_cand);
371 is_cand = get_ia32_frame_ent(irn) ? (check_addr ? 1 : 0) : is_cand;
377 * Compares the base and index addr and the load/store entities
378 * and returns 1 if they are equal.
380 static int load_store_addr_is_equal(const ir_node *load, const ir_node *store,
381 const ir_node *addr_b, const ir_node *addr_i)
383 int is_equal = (addr_b == get_irn_n(load, 0)) && (addr_i == get_irn_n(load, 1));
384 entity *lent = get_ia32_frame_ent(load);
385 entity *sent = get_ia32_frame_ent(store);
387 /* are both entities set and equal? */
388 is_equal = lent && sent && (lent == sent);
390 /* are the load and the store of the same mode? */
391 is_equal = get_ia32_ls_mode(load) == get_ia32_ls_mode(store);
399 * Folds Add or Sub to LEA if possible
401 static ir_node *fold_addr(be_abi_irg_t *babi, ir_node *irn, firm_dbg_module_t *mod, ir_node *noreg) {
402 ir_graph *irg = get_irn_irg(irn);
403 dbg_info *dbg = get_irn_dbg_info(irn);
404 ir_node *block = get_nodes_block(irn);
407 char *offs_cnst = NULL;
408 char *offs_lea = NULL;
412 ir_node *left, *right, *temp;
413 ir_node *base, *index;
414 ia32_am_flavour_t am_flav;
416 if (is_ia32_Add(irn))
419 left = get_irn_n(irn, 2);
420 right = get_irn_n(irn, 3);
422 /* "normalize" arguments in case of add with two operands */
423 if (isadd && ! be_is_NoReg(babi, right)) {
424 /* put LEA == ia32_am_O as right operand */
425 if (is_ia32_Lea(left) && get_ia32_am_flavour(left) == ia32_am_O) {
426 set_irn_n(irn, 2, right);
427 set_irn_n(irn, 3, left);
433 /* put LEA != ia32_am_O as left operand */
434 if (is_ia32_Lea(right) && get_ia32_am_flavour(right) != ia32_am_O) {
435 set_irn_n(irn, 2, right);
436 set_irn_n(irn, 3, left);
442 /* put SHL as left operand iff left is NOT a LEA */
443 if (! is_ia32_Lea(left) && pred_is_specific_node(right, is_ia32_Shl)) {
444 set_irn_n(irn, 2, right);
445 set_irn_n(irn, 3, left);
458 /* check if operand is either const */
459 if (get_ia32_cnst(irn)) {
460 DBG((mod, LEVEL_1, "\tfound op with imm"));
462 offs_cnst = get_ia32_cnst(irn);
466 /* determine the operand which needs to be checked */
467 if (be_is_NoReg(babi, right)) {
474 /* check if right operand is AMConst (LEA with ia32_am_O) */
475 if (is_ia32_Lea(temp) && get_ia32_am_flavour(temp) == ia32_am_O) {
476 DBG((mod, LEVEL_1, "\tgot op with LEA am_O"));
478 offs_lea = get_ia32_am_offs(temp);
483 /* default for add -> make right operand to index */
487 DBG((mod, LEVEL_1, "\tgot LEA candidate with index %+F\n", index));
489 /* determine the operand which needs to be checked */
491 if (is_ia32_Lea(left)) {
495 /* check for SHL 1,2,3 */
496 if (pred_is_specific_node(temp, is_ia32_Shl)) {
497 temp = get_Proj_pred(temp);
499 if (get_ia32_Immop_tarval(temp)) {
500 scale = get_tarval_long(get_ia32_Immop_tarval(temp));
503 index = get_irn_n(temp, 2);
505 DBG((mod, LEVEL_1, "\tgot scaled index %+F\n", index));
511 if (! be_is_NoReg(babi, index)) {
512 /* if we have index, but left == right -> no base */
516 else if (! is_ia32_Lea(left) && (index != right)) {
517 /* index != right -> we found a good Shl */
518 /* left != LEA -> this Shl was the left operand */
519 /* -> base is right operand */
525 /* Try to assimilate a LEA as left operand */
526 if (is_ia32_Lea(left) && (get_ia32_am_flavour(left) != ia32_am_O)) {
527 am_flav = get_ia32_am_flavour(left);
529 /* If we have an Add with a real right operand (not NoReg) and */
530 /* the LEA contains already an index calculation then we create */
532 /* If the LEA contains already a frame_entity then we also */
533 /* create a new one otherwise we would loose it. */
534 if ((isadd && ((!be_is_NoReg(babi, index) && (am_flav & ia32_am_I))) || get_ia32_frame_ent(left))) {
535 DBG((mod, LEVEL_1, "\tleave old LEA, creating new one\n"));
538 DBG((mod, LEVEL_1, "\tgot LEA as left operand ... assimilating\n"));
539 offs = get_ia32_am_offs(left);
540 base = get_irn_n(left, 0);
541 index = get_irn_n(left, 1);
542 scale = get_ia32_am_scale(left);
546 /* ok, we can create a new LEA */
548 res = new_rd_ia32_Lea(dbg, irg, block, base, index, mode_Is);
550 /* add the old offset of a previous LEA */
552 add_ia32_am_offs(res, offs);
555 /* add the new offset */
558 add_ia32_am_offs(res, offs_cnst);
561 add_ia32_am_offs(res, offs_lea);
565 /* either lea_O-cnst, -cnst or -lea_O */
568 add_ia32_am_offs(res, offs_lea);
571 sub_ia32_am_offs(res, offs_cnst);
574 sub_ia32_am_offs(res, offs_lea);
578 /* copy the frame entity (could be set in case of Add */
579 /* which was a FrameAddr) */
580 set_ia32_frame_ent(res, get_ia32_frame_ent(irn));
582 if (is_ia32_use_frame(irn))
583 set_ia32_use_frame(res);
586 set_ia32_am_scale(res, scale);
589 /* determine new am flavour */
590 if (offs || offs_cnst || offs_lea) {
593 if (! be_is_NoReg(babi, base)) {
596 if (! be_is_NoReg(babi, index)) {
602 set_ia32_am_flavour(res, am_flav);
604 set_ia32_op_type(res, ia32_AddrModeS);
606 DBG((mod, LEVEL_1, "\tLEA [%+F + %+F * %d + %s]\n", base, index, scale, get_ia32_am_offs(res)));
608 /* get the result Proj of the Add/Sub */
609 irn = get_res_proj(irn);
611 assert(irn && "Couldn't find result proj");
613 /* exchange the old op with the new LEA */
621 * Optimizes a pattern around irn to address mode if possible.
623 void ia32_optimize_am(ir_node *irn, void *env) {
624 ia32_code_gen_t *cg = env;
625 firm_dbg_module_t *mod = cg->mod;
627 be_abi_irg_t *babi = cg->birg->abi;
630 ir_node *block, *noreg_gp, *noreg_fp;
631 ir_node *left, *right, *temp;
632 ir_node *store, *load, *mem_proj;
633 ir_node *succ, *addr_b, *addr_i;
634 int check_am_src = 0;
636 if (! is_ia32_irn(irn))
639 dbg = get_irn_dbg_info(irn);
640 mode = get_irn_mode(irn);
641 block = get_nodes_block(irn);
642 noreg_gp = ia32_new_NoReg_gp(cg);
643 noreg_fp = ia32_new_NoReg_fp(cg);
645 DBG((mod, LEVEL_1, "checking for AM\n"));
647 /* 1st part: check for address calculations and transform the into Lea */
649 /* Following cases can occur: */
650 /* - Sub (l, imm) -> LEA [base - offset] */
651 /* - Sub (l, r == LEA with ia32_am_O) -> LEA [base - offset] */
652 /* - Add (l, imm) -> LEA [base + offset] */
653 /* - Add (l, r == LEA with ia32_am_O) -> LEA [base + offset] */
654 /* - Add (l == LEA with ia32_am_O, r) -> LEA [base + offset] */
655 /* - Add (l, r) -> LEA [base + index * scale] */
656 /* with scale > 1 iff l/r == shl (1,2,3) */
658 if (is_ia32_Sub(irn) || is_ia32_Add(irn)) {
659 left = get_irn_n(irn, 2);
660 right = get_irn_n(irn, 3);
662 /* Do not try to create a LEA if one of the operands is a Load. */
663 /* check is irn is a candidate for address calculation */
664 if (is_candidate(block, irn, 1)) {
665 DBG((mod, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn));
666 res = fold_addr(babi, irn, mod, noreg_gp);
669 DB((mod, LEVEL_1, "transformed into %+F\n", res));
671 DB((mod, LEVEL_1, "not transformed\n"));
675 /* 2nd part: fold following patterns: */
676 /* - Load -> LEA into Load } TODO: If the LEA is used by more than one Load/Store */
677 /* - Store -> LEA into Store } it might be better to keep the LEA */
678 /* - op -> Load into AMop with am_Source */
680 /* - op is am_Source capable AND */
681 /* - the Load is only used by this op AND */
682 /* - the Load is in the same block */
683 /* - Store -> op -> Load into AMop with am_Dest */
685 /* - op is am_Dest capable AND */
686 /* - the Store uses the same address as the Load AND */
687 /* - the Load is only used by this op AND */
688 /* - the Load and Store are in the same block AND */
689 /* - nobody else uses the result of the op */
691 if ((res == irn) && (get_ia32_am_support(irn) != ia32_am_None) && !is_ia32_Lea(irn)) {
692 /* 1st: check for Load/Store -> LEA */
693 if (is_ia32_Ld(irn) || is_ia32_St(irn)) {
694 left = get_irn_n(irn, 0);
696 if (is_ia32_Lea(left)) {
697 DBG((mod, LEVEL_1, "\nmerging %+F into %+F\n", left, irn));
699 /* get the AM attributes from the LEA */
700 add_ia32_am_offs(irn, get_ia32_am_offs(left));
701 set_ia32_am_scale(irn, get_ia32_am_scale(left));
702 set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
704 set_ia32_op_type(irn, is_ia32_St(irn) ? ia32_AddrModeD : ia32_AddrModeS);
706 /* set base and index */
707 set_irn_n(irn, 0, get_irn_n(left, 0));
708 set_irn_n(irn, 1, get_irn_n(left, 1));
711 /* check if the node is an address mode candidate */
712 else if (is_candidate(block, irn, 0)) {
713 DBG((mod, LEVEL_1, "\tfound address mode candidate %+F ... ", irn));
715 left = get_irn_n(irn, 2);
716 if (get_irn_arity(irn) == 4) {
717 /* it's an "unary" operation */
721 right = get_irn_n(irn, 3);
724 /* normalize commutative ops */
725 if (node_is_comm(irn)) {
726 /* Assure that right operand is always a Load if there is one */
727 /* because non-commutative ops can only use Dest AM if the right */
728 /* operand is a load, so we only need to check right operand. */
729 if (pred_is_specific_nodeblock(block, left, is_ia32_Ld))
731 set_irn_n(irn, 2, right);
732 set_irn_n(irn, 3, left);
740 /* check for Store -> op -> Load */
742 /* Store -> op -> Load optimization is only possible if supported by op */
743 /* and if right operand is a Load */
744 if ((get_ia32_am_support(irn) & ia32_am_Dest) &&
745 pred_is_specific_nodeblock(block, right, is_ia32_Ld))
748 /* An address mode capable op always has a result Proj. */
749 /* If this Proj is used by more than one other node, we don't need to */
750 /* check further, otherwise we check for Store and remember the address, */
751 /* the Store points to. */
753 succ = get_res_proj(irn);
754 assert(succ && "Couldn't find result proj");
760 /* now check for users and Store */
761 if (ia32_get_irn_n_edges(succ) == 1) {
762 succ = get_edge_src_irn(get_irn_out_edge_first(succ));
764 if (is_ia32_fStore(succ) || is_ia32_Store(succ)) {
766 addr_b = get_irn_n(store, 0);
768 /* Could be that the Store is connected to the address */
769 /* calculating LEA while the Load is already transformed. */
770 if (is_ia32_Lea(addr_b)) {
772 addr_b = get_irn_n(succ, 0);
773 addr_i = get_irn_n(succ, 1);
782 /* we found a Store as single user: Now check for Load */
784 /* Extra check for commutative ops with two Loads */
785 /* -> put the interesting Load right */
786 if (node_is_comm(irn) &&
787 pred_is_specific_nodeblock(block, left, is_ia32_Ld))
789 if ((addr_b == get_irn_n(get_Proj_pred(left), 0)) &&
790 (addr_i == get_irn_n(get_Proj_pred(left), 1)))
792 /* We exchange left and right, so it's easier to kill */
793 /* the correct Load later and to handle unary operations. */
794 set_irn_n(irn, 2, right);
795 set_irn_n(irn, 3, left);
803 /* skip the Proj for easier access */
804 load = get_Proj_pred(right);
806 /* Compare Load and Store address */
807 if (load_store_addr_is_equal(load, store, addr_b, addr_i)) {
808 /* Right Load is from same address, so we can */
809 /* disconnect the Load and Store here */
811 /* set new base, index and attributes */
812 set_irn_n(irn, 0, addr_b);
813 set_irn_n(irn, 1, addr_i);
814 add_ia32_am_offs(irn, get_ia32_am_offs(load));
815 set_ia32_am_scale(irn, get_ia32_am_scale(load));
816 set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
817 set_ia32_op_type(irn, ia32_AddrModeD);
818 set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
819 set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
821 if (is_ia32_use_frame(load))
822 set_ia32_use_frame(irn);
824 /* connect to Load memory and disconnect Load */
825 if (get_irn_arity(irn) == 5) {
827 set_irn_n(irn, 4, get_irn_n(load, 2));
828 set_irn_n(irn, 3, noreg_gp);
832 set_irn_n(irn, 3, get_irn_n(load, 2));
833 set_irn_n(irn, 2, noreg_gp);
836 /* connect the memory Proj of the Store to the op */
837 mem_proj = get_mem_proj(store);
838 set_Proj_pred(mem_proj, irn);
839 set_Proj_proj(mem_proj, 1);
841 DB((mod, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
844 else if (get_ia32_am_support(irn) & ia32_am_Source) {
845 /* There was no store, check if we still can optimize for source address mode */
848 } /* if (support AM Dest) */
849 else if (get_ia32_am_support(irn) & ia32_am_Source) {
850 /* op doesn't support am AM Dest -> check for AM Source */
854 /* normalize commutative ops */
855 if (node_is_comm(irn)) {
856 /* Assure that left operand is always a Load if there is one */
857 /* because non-commutative ops can only use Source AM if the */
858 /* left operand is a Load, so we only need to check the left */
859 /* operand afterwards. */
860 if (pred_is_specific_nodeblock(block, right, is_ia32_Ld)) {
861 set_irn_n(irn, 2, right);
862 set_irn_n(irn, 3, left);
870 /* optimize op -> Load iff Load is only used by this op */
871 /* and left operand is a Load which only used by this irn */
873 pred_is_specific_nodeblock(block, left, is_ia32_Ld) &&
874 (ia32_get_irn_n_edges(left) == 1))
876 left = get_Proj_pred(left);
878 addr_b = get_irn_n(left, 0);
879 addr_i = get_irn_n(left, 1);
881 /* set new base, index and attributes */
882 set_irn_n(irn, 0, addr_b);
883 set_irn_n(irn, 1, addr_i);
884 add_ia32_am_offs(irn, get_ia32_am_offs(left));
885 set_ia32_am_scale(irn, get_ia32_am_scale(left));
886 set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
887 set_ia32_op_type(irn, ia32_AddrModeS);
888 set_ia32_frame_ent(irn, get_ia32_frame_ent(left));
889 set_ia32_ls_mode(irn, get_ia32_ls_mode(left));
891 if (is_ia32_use_frame(left))
892 set_ia32_use_frame(irn);
894 /* connect to Load memory */
895 if (get_irn_arity(irn) == 5) {
897 set_irn_n(irn, 4, get_irn_n(left, 2));
901 set_irn_n(irn, 3, get_irn_n(left, 2));
904 /* disconnect from Load */
905 set_irn_n(irn, 2, noreg_gp);
907 /* If Load has a memory Proj, connect it to the op */
908 mem_proj = get_mem_proj(left);
910 set_Proj_pred(mem_proj, irn);
911 set_Proj_proj(mem_proj, 1);
914 DB((mod, LEVEL_1, "merged with %+F into source AM\n", left));