8 #include "firm_types.h"
16 #include "ia32_new_nodes.h"
17 #include "bearch_ia32_t.h"
18 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
21 #define is_NoMem(irn) (get_irn_op(irn) == op_NoMem)
23 static int be_is_NoReg(be_abi_irg_t *babi, const ir_node *irn) {
24 if (be_abi_get_callee_save_irn(babi, &ia32_gp_regs[REG_XXX]) == irn ||
25 be_abi_get_callee_save_irn(babi, &ia32_fp_regs[REG_XXXX]) == irn)
34 * creates a unique ident by adding a number to a tag
36 * @param tag the tag string, must contain a %d if a number
39 static ident *unique_id(const char *tag)
41 static unsigned id = 0;
44 snprintf(str, sizeof(str), tag, ++id);
45 return new_id_from_str(str);
51 * Transforms a SymConst.
53 * @param mod the debug module
54 * @param block the block the new node should belong to
55 * @param node the ir SymConst node
56 * @param mode mode of the SymConst
57 * @return the created ia32 Const node
59 static ir_node *gen_SymConst(ia32_transform_env_t *env) {
61 dbg_info *dbg = env->dbg;
62 ir_mode *mode = env->mode;
63 ir_graph *irg = env->irg;
64 ir_node *block = env->block;
66 cnst = new_rd_ia32_Const(dbg, irg, block, mode);
67 set_ia32_Const_attr(cnst, env->irn);
72 * Get a primitive type for a mode.
74 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
76 pmap_entry *e = pmap_find(types, mode);
81 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
82 res = new_type_primitive(new_id_from_str(buf), mode);
83 pmap_insert(types, mode, res);
91 * Get an entity that is initialized with a tarval
93 static entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
95 tarval *tv = get_Const_tarval(cnst);
96 pmap_entry *e = pmap_find(cg->tv_ent, tv);
101 ir_mode *mode = get_irn_mode(cnst);
102 ir_type *tp = get_Const_type(cnst);
103 if (tp == firm_unknown_type)
104 tp = get_prim_type(cg->types, mode);
106 res = new_entity(get_glob_type(), unique_id("ia32FloatCnst_%u"), tp);
108 set_entity_ld_ident(res, get_entity_ident(res));
109 set_entity_visibility(res, visibility_local);
110 set_entity_variability(res, variability_constant);
111 set_entity_allocation(res, allocation_static);
113 /* we create a new entity here: It's initialization must resist on the
115 rem = current_ir_graph;
116 current_ir_graph = get_const_code_irg();
117 set_atomic_ent_value(res, new_Const_type(tv, tp));
118 current_ir_graph = rem;
126 * Transforms a Const.
128 * @param mod the debug module
129 * @param block the block the new node should belong to
130 * @param node the ir Const node
131 * @param mode mode of the Const
132 * @return the created ia32 Const node
134 static ir_node *gen_Const(ia32_transform_env_t *env) {
137 ir_graph *irg = env->irg;
138 ir_node *block = env->block;
139 ir_node *node = env->irn;
140 dbg_info *dbg = env->dbg;
141 ir_mode *mode = env->mode;
143 if (mode_is_float(mode)) {
144 sym.entity_p = get_entity_for_tv(env->cg, node);
146 cnst = new_rd_SymConst(dbg, irg, block, sym, symconst_addr_ent);
148 cnst = gen_SymConst(env);
151 cnst = new_rd_ia32_Const(dbg, irg, block, get_irn_mode(node));
152 set_ia32_Const_attr(cnst, node);
160 * Transforms (all) Const's into ia32_Const and places them in the
161 * block where they are used (or in the cfg-pred Block in case of Phi's)
163 void ia32_place_consts(ir_node *irn, void *env) {
164 ia32_code_gen_t *cg = env;
165 ia32_transform_env_t tenv;
167 ir_node *pred, *cnst;
174 mode = get_irn_mode(irn);
176 tenv.block = get_nodes_block(irn);
181 /* Loop over all predecessors and check for Sym/Const nodes */
182 for (i = get_irn_arity(irn) - 1; i >= 0; --i) {
183 pred = get_irn_n(irn, i);
185 opc = get_irn_opcode(pred);
187 tenv.mode = get_irn_mode(pred);
188 tenv.dbg = get_irn_dbg_info(pred);
190 /* If it's a Phi, then we need to create the */
191 /* new Const in it's predecessor block */
193 tenv.block = get_Block_cfgpred_block(get_nodes_block(irn), i);
196 /* put the const into the block where the original const was */
197 if (! cg->opt.placecnst) {
198 tenv.block = get_nodes_block(pred);
203 cnst = gen_Const(&tenv);
206 cnst = gen_SymConst(&tenv);
212 /* if we found a const, then set it */
214 set_irn_n(irn, i, cnst);
220 /******************************************************************
222 * /\ | | | | | \/ | | |
223 * / \ __| | __| |_ __ ___ ___ ___| \ / | ___ __| | ___
224 * / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \
225 * / ____ \ (_| | (_| | | | __/\__ \__ \ | | | (_) | (_| | __/
226 * /_/ \_\__,_|\__,_|_| \___||___/___/_| |_|\___/ \__,_|\___|
228 ******************************************************************/
230 static int node_is_comm(const ir_node *irn) {
231 return is_ia32_irn(irn) ? is_ia32_commutative(irn) : 0;
234 static int ia32_get_irn_n_edges(const ir_node *irn) {
235 const ir_edge_t *edge;
238 foreach_out_edge(irn, edge) {
246 * Returns the first mode_M Proj connected to irn.
248 static ir_node *get_mem_proj(const ir_node *irn) {
249 const ir_edge_t *edge;
252 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
254 foreach_out_edge(irn, edge) {
255 src = get_edge_src_irn(edge);
257 assert(is_Proj(src) && "Proj expected");
259 if (get_irn_mode(src) == mode_M)
267 * Returns the Proj with number 0 connected to irn.
269 static ir_node *get_res_proj(const ir_node *irn) {
270 const ir_edge_t *edge;
273 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
275 foreach_out_edge(irn, edge) {
276 src = get_edge_src_irn(edge);
278 assert(is_Proj(src) && "Proj expected");
280 if (get_Proj_proj(src) == 0)
288 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor.
290 * @param pred The node to be checked
291 * @param is_op_func The check-function
292 * @return 1 if conditions are fulfilled, 0 otherwise
294 static int pred_is_specific_node(const ir_node *pred, int (*is_op_func)(const ir_node *n)) {
295 if (is_Proj(pred) && is_op_func(get_Proj_pred(pred))) {
303 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor
304 * and if the predecessor is in block bl.
306 * @param bl The block
307 * @param pred The node to be checked
308 * @param is_op_func The check-function
309 * @return 1 if conditions are fulfilled, 0 otherwise
311 static int pred_is_specific_nodeblock(const ir_node *bl, const ir_node *pred,
312 int (*is_op_func)(const ir_node *n))
315 pred = get_Proj_pred(pred);
316 if ((bl == get_nodes_block(pred)) && is_op_func(pred)) {
325 * Checks if irn is a candidate for address calculation or address mode.
327 * address calculation (AC):
328 * - none of the operand must be a Load within the same block OR
329 * - all Loads must have more than one user OR
330 * - the irn has a frame entity (it's a former FrameAddr)
333 * - at least one operand has to be a Load within the same block AND
334 * - the load must not have other users than the irn AND
335 * - the irn must not have a frame entity set
337 * @param block The block the Loads must/not be in
338 * @param irn The irn to check
339 * @param check_addr 1 if to check for address calculation, 0 otherwise
340 * return 1 if irn is a candidate for AC or AM, 0 otherwise
342 static int is_candidate(const ir_node *block, const ir_node *irn, int check_addr) {
344 int n, is_cand = check_addr;
346 if (pred_is_specific_nodeblock(block, get_irn_n(irn, 2), is_ia32_Load)) {
347 load_proj = get_irn_n(irn, 2);
348 n = ia32_get_irn_n_edges(load_proj);
349 is_cand = check_addr ? (n == 1 ? 0 : is_cand) : (n == 1 ? 1 : is_cand);
352 if (pred_is_specific_nodeblock(block, get_irn_n(irn, 3), is_ia32_Load)) {
353 load_proj = get_irn_n(irn, 3);
354 n = ia32_get_irn_n_edges(load_proj);
355 is_cand = check_addr ? (n == 1 ? 0 : is_cand) : (n == 1 ? 1 : is_cand);
358 is_cand = get_ia32_frame_ent(irn) ? (check_addr ? 1 : 0) : (check_addr ? 0 : 1);
364 * Compares the base and index addr and the load/store entities
365 * and returns 1 if they are equal.
367 static int load_store_addr_is_equal(const ir_node *load, const ir_node *store,
368 const ir_node *addr_b, const ir_node *addr_i)
370 int is_equal = (addr_b == get_irn_n(load, 0)) && (addr_i == get_irn_n(load, 1));
371 entity *lent = get_ia32_frame_ent(load);
372 entity *sent = get_ia32_frame_ent(store);
374 /* are both entities set and equal? */
375 is_equal = (lent && sent && (lent == sent)) ? 1 : is_equal;
381 * Folds Add or Sub to LEA if possible
383 static ir_node *fold_addr(be_abi_irg_t *babi, ir_node *irn, firm_dbg_module_t *mod, ir_node *noreg) {
384 ir_graph *irg = get_irn_irg(irn);
385 dbg_info *dbg = get_irn_dbg_info(irn);
386 ir_node *block = get_nodes_block(irn);
389 char *offs_cnst = NULL;
390 char *offs_lea = NULL;
394 ir_node *left, *right, *temp;
395 ir_node *base, *index;
396 ia32_am_flavour_t am_flav;
398 if (is_ia32_Add(irn))
401 left = get_irn_n(irn, 2);
402 right = get_irn_n(irn, 3);
410 /* "normalize" arguments in case of add with two operands */
411 if (isadd && ! be_is_NoReg(babi, right)) {
412 /* put LEA == ia32_am_O as right operand */
413 if (is_ia32_Lea(left) && get_ia32_am_flavour(left) == ia32_am_O) {
414 set_irn_n(irn, 2, right);
415 set_irn_n(irn, 3, left);
421 /* put LEA != ia32_am_O as left operand */
422 if (is_ia32_Lea(right) && get_ia32_am_flavour(right) != ia32_am_O) {
423 set_irn_n(irn, 2, right);
424 set_irn_n(irn, 3, left);
430 /* put SHL as left operand iff left is NOT a LEA */
431 if (! is_ia32_Lea(left) && pred_is_specific_node(right, is_ia32_Shl)) {
432 set_irn_n(irn, 2, right);
433 set_irn_n(irn, 3, left);
440 /* check if operand is either const */
441 if (get_ia32_cnst(irn)) {
442 DBG((mod, LEVEL_1, "\tfound op with imm"));
444 offs_cnst = get_ia32_cnst(irn);
448 /* determine the operand which needs to be checked */
449 if (be_is_NoReg(babi, right)) {
456 /* check if right operand is AMConst (LEA with ia32_am_O) */
457 if (is_ia32_Lea(temp) && get_ia32_am_flavour(temp) == ia32_am_O) {
458 DBG((mod, LEVEL_1, "\tgot op with LEA am_O"));
460 offs_lea = get_ia32_am_offs(temp);
465 /* default for add -> make right operand to index */
469 DBG((mod, LEVEL_1, "\tgot LEA candidate with index %+F\n", index));
471 /* determine the operand which needs to be checked */
473 if (is_ia32_Lea(left)) {
477 /* check for SHL 1,2,3 */
478 if (pred_is_specific_node(temp, is_ia32_Shl)) {
479 temp = get_Proj_pred(temp);
481 if (get_ia32_Immop_tarval(temp)) {
482 scale = get_tarval_long(get_ia32_Immop_tarval(temp));
485 index = get_irn_n(temp, 2);
487 DBG((mod, LEVEL_1, "\tgot scaled index %+F\n", index));
493 if (! be_is_NoReg(babi, index)) {
494 /* if we have index, but left == right -> no base */
498 else if (! is_ia32_Lea(left) && (index != right)) {
499 /* index != right -> we found a good Shl */
500 /* left != LEA -> this Shl was the left operand */
501 /* -> base is right operand */
507 /* Try to assimilate a LEA as left operand */
508 if (is_ia32_Lea(left) && (get_ia32_am_flavour(left) != ia32_am_O)) {
509 am_flav = get_ia32_am_flavour(left);
511 /* If we have an Add with a real right operand (not NoReg) and */
512 /* the LEA contains already an index calculation then we create */
514 /* If the LEA contains already a frame_entity then we also */
515 /* create a new one otherwise we would loose it. */
516 if (isadd && ((!be_is_NoReg(babi, index) && (am_flav & ia32_am_I)) || get_ia32_frame_ent(left))) {
517 DBG((mod, LEVEL_1, "\tleave old LEA, creating new one\n"));
520 DBG((mod, LEVEL_1, "\tgot LEA as left operand ... assimilating\n"));
521 offs = get_ia32_am_offs(left);
522 base = get_irn_n(left, 0);
523 index = get_irn_n(left, 1);
524 scale = get_ia32_am_scale(left);
528 /* ok, we can create a new LEA */
530 res = new_rd_ia32_Lea(dbg, irg, block, base, index, mode_Is);
532 /* add the old offset of a previous LEA */
534 add_ia32_am_offs(res, offs);
537 /* add the new offset */
540 add_ia32_am_offs(res, offs_cnst);
543 add_ia32_am_offs(res, offs_lea);
547 /* either lea_O-cnst, -cnst or -lea_O */
550 add_ia32_am_offs(res, offs_lea);
553 sub_ia32_am_offs(res, offs_cnst);
556 sub_ia32_am_offs(res, offs_lea);
560 /* copy the frame entity (could be set in case of Add */
561 /* which was a FrameAddr) */
562 set_ia32_frame_ent(res, get_ia32_frame_ent(irn));
564 if (is_ia32_use_frame(irn))
565 set_ia32_use_frame(res);
568 set_ia32_am_scale(res, scale);
571 /* determine new am flavour */
572 if (offs || offs_cnst || offs_lea) {
575 if (! be_is_NoReg(babi, base)) {
578 if (! be_is_NoReg(babi, index)) {
584 set_ia32_am_flavour(res, am_flav);
586 set_ia32_op_type(res, ia32_AddrModeS);
588 DBG((mod, LEVEL_1, "\tLEA [%+F + %+F * %d + %s]\n", base, index, scale, get_ia32_am_offs(res)));
590 /* get the result Proj of the Add/Sub */
591 irn = get_res_proj(irn);
593 assert(irn && "Couldn't find result proj");
595 /* exchange the old op with the new LEA */
603 * Optimizes a pattern around irn to address mode if possible.
605 void ia32_optimize_am(ir_node *irn, void *env) {
606 ia32_code_gen_t *cg = env;
607 firm_dbg_module_t *mod = cg->mod;
609 be_abi_irg_t *babi = cg->birg->abi;
612 ir_node *block, *noreg_gp, *noreg_fp;
613 ir_node *left, *right, *temp;
614 ir_node *store, *load, *mem_proj;
615 ir_node *succ, *addr_b, *addr_i;
616 int check_am_src = 0;
618 if (! is_ia32_irn(irn))
621 dbg = get_irn_dbg_info(irn);
622 mode = get_irn_mode(irn);
623 block = get_nodes_block(irn);
624 noreg_gp = ia32_new_NoReg_gp(cg);
625 noreg_fp = ia32_new_NoReg_fp(cg);
627 DBG((mod, LEVEL_1, "checking for AM\n"));
629 /* 1st part: check for address calculations and transform the into Lea */
631 /* Following cases can occur: */
632 /* - Sub (l, imm) -> LEA [base - offset] */
633 /* - Sub (l, r == LEA with ia32_am_O) -> LEA [base - offset] */
634 /* - Add (l, imm) -> LEA [base + offset] */
635 /* - Add (l, r == LEA with ia32_am_O) -> LEA [base + offset] */
636 /* - Add (l == LEA with ia32_am_O, r) -> LEA [base + offset] */
637 /* - Add (l, r) -> LEA [base + index * scale] */
638 /* with scale > 1 iff l/r == shl (1,2,3) */
640 if (is_ia32_Sub(irn) || is_ia32_Add(irn)) {
641 left = get_irn_n(irn, 2);
642 right = get_irn_n(irn, 3);
644 /* Do not try to create a LEA if one of the operands is a Load. */
645 /* check is irn is a candidate for address calculation */
646 if (is_candidate(block, irn, 1)) {
647 DBG((mod, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn));
648 res = fold_addr(babi, irn, mod, noreg_gp);
651 DB((mod, LEVEL_1, "transformed into %+F\n", res));
653 DB((mod, LEVEL_1, "not transformed\n"));
657 /* 2nd part: fold following patterns: */
658 /* - Load -> LEA into Load } TODO: If the LEA is used by more than one Load/Store */
659 /* - Store -> LEA into Store } it might be better to keep the LEA */
660 /* - op -> Load into AMop with am_Source */
662 /* - op is am_Source capable AND */
663 /* - the Load is only used by this op AND */
664 /* - the Load is in the same block */
665 /* - Store -> op -> Load into AMop with am_Dest */
667 /* - op is am_Dest capable AND */
668 /* - the Store uses the same address as the Load AND */
669 /* - the Load is only used by this op AND */
670 /* - the Load and Store are in the same block AND */
671 /* - nobody else uses the result of the op */
673 if ((res == irn) && (get_ia32_am_support(irn) != ia32_am_None) && !is_ia32_Lea(irn)) {
674 /* 1st: check for Load/Store -> LEA */
675 if (is_ia32_Ld(irn) || is_ia32_St(irn)) {
676 left = get_irn_n(irn, 0);
678 if (is_ia32_Lea(left)) {
679 DBG((mod, LEVEL_1, "\nmerging %+F into %+F\n", left, irn));
681 /* get the AM attributes from the LEA */
682 add_ia32_am_offs(irn, get_ia32_am_offs(left));
683 set_ia32_am_scale(irn, get_ia32_am_scale(left));
684 set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
686 set_ia32_op_type(irn, is_ia32_St(irn) ? ia32_AddrModeD : ia32_AddrModeS);
688 /* set base and index */
689 set_irn_n(irn, 0, get_irn_n(left, 0));
690 set_irn_n(irn, 1, get_irn_n(left, 1));
693 /* check if the node is an address mode candidate */
694 else if (is_candidate(block, irn, 0)) {
695 DBG((mod, LEVEL_1, "\tfound address mode candidate %+F ... ", irn));
697 left = get_irn_n(irn, 2);
698 if (get_irn_arity(irn) == 4) {
699 /* it's an "unary" operation */
703 right = get_irn_n(irn, 3);
706 /* normalize commutative ops */
707 if (node_is_comm(irn)) {
708 /* Assure that right operand is always a Load if there is one */
709 /* because non-commutative ops can only use Dest AM if the right */
710 /* operand is a load, so we only need to check right operand. */
711 if (pred_is_specific_nodeblock(block, left, is_ia32_Ld))
713 set_irn_n(irn, 2, right);
714 set_irn_n(irn, 3, left);
722 /* check for Store -> op -> Load */
724 /* Store -> op -> Load optimization is only possible if supported by op */
725 /* and if right operand is a Load */
726 if ((get_ia32_am_support(irn) & ia32_am_Dest) &&
727 pred_is_specific_nodeblock(block, right, is_ia32_Ld))
730 /* An address mode capable op always has a result Proj. */
731 /* If this Proj is used by more than one other node, we don't need to */
732 /* check further, otherwise we check for Store and remember the address, */
733 /* the Store points to. */
735 succ = get_res_proj(irn);
736 assert(succ && "Couldn't find result proj");
742 /* now check for users and Store */
743 if (ia32_get_irn_n_edges(succ) == 1) {
744 succ = get_edge_src_irn(get_irn_out_edge_first(succ));
746 if (is_ia32_fStore(succ) || is_ia32_Store(succ)) {
748 addr_b = get_irn_n(store, 0);
750 /* Could be that the Store is connected to the address */
751 /* calculating LEA while the Load is already transformed. */
752 if (is_ia32_Lea(addr_b)) {
754 addr_b = get_irn_n(succ, 0);
755 addr_i = get_irn_n(succ, 1);
764 /* we found a Store as single user: Now check for Load */
766 /* Extra check for commutative ops with two Loads */
767 /* -> put the interesting Load right */
768 if (node_is_comm(irn) &&
769 pred_is_specific_nodeblock(block, left, is_ia32_Ld))
771 if ((addr_b == get_irn_n(get_Proj_pred(left), 0)) &&
772 (addr_i == get_irn_n(get_Proj_pred(left), 1)))
774 /* We exchange left and right, so it's easier to kill */
775 /* the correct Load later and to handle unary operations. */
776 set_irn_n(irn, 2, right);
777 set_irn_n(irn, 3, left);
785 /* skip the Proj for easier access */
786 load = get_Proj_pred(right);
788 /* Compare Load and Store address */
789 if (load_store_addr_is_equal(load, store, addr_b, addr_i)) {
790 /* Right Load is from same address, so we can */
791 /* disconnect the Load and Store here */
793 /* set new base, index and attributes */
794 set_irn_n(irn, 0, addr_b);
795 set_irn_n(irn, 1, addr_i);
796 add_ia32_am_offs(irn, get_ia32_am_offs(load));
797 set_ia32_am_scale(irn, get_ia32_am_scale(load));
798 set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
799 set_ia32_op_type(irn, ia32_AddrModeD);
800 set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
801 set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
803 if (is_ia32_use_frame(load))
804 set_ia32_use_frame(irn);
806 /* connect to Load memory and disconnect Load */
807 if (get_irn_arity(irn) == 5) {
809 set_irn_n(irn, 4, get_irn_n(load, 2));
810 set_irn_n(irn, 3, noreg_gp);
814 set_irn_n(irn, 3, get_irn_n(load, 2));
815 set_irn_n(irn, 2, noreg_gp);
818 /* connect the memory Proj of the Store to the op */
819 mem_proj = get_mem_proj(store);
820 set_Proj_pred(mem_proj, irn);
821 set_Proj_proj(mem_proj, 1);
823 DB((mod, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
826 else if (get_ia32_am_support(irn) & ia32_am_Source) {
827 /* There was no store, check if we still can optimize for source address mode */
830 } /* if (support AM Dest) */
831 else if (get_ia32_am_support(irn) & ia32_am_Source) {
832 /* op doesn't support am AM Dest -> check for AM Source */
836 /* normalize commutative ops */
837 if (node_is_comm(irn)) {
838 /* Assure that left operand is always a Load if there is one */
839 /* because non-commutative ops can only use Source AM if the */
840 /* left operand is a Load, so we only need to check the left */
841 /* operand afterwards. */
842 if (pred_is_specific_nodeblock(block, right, is_ia32_Ld)) {
843 set_irn_n(irn, 2, right);
844 set_irn_n(irn, 3, left);
852 /* optimize op -> Load iff Load is only used by this op */
853 /* and left operand is a Load which only used by this irn */
855 pred_is_specific_nodeblock(block, left, is_ia32_Ld) &&
856 (ia32_get_irn_n_edges(left) == 1))
858 left = get_Proj_pred(left);
860 addr_b = get_irn_n(left, 0);
861 addr_i = get_irn_n(left, 1);
863 /* set new base, index and attributes */
864 set_irn_n(irn, 0, addr_b);
865 set_irn_n(irn, 1, addr_i);
866 add_ia32_am_offs(irn, get_ia32_am_offs(left));
867 set_ia32_am_scale(irn, get_ia32_am_scale(left));
868 set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
869 set_ia32_op_type(irn, ia32_AddrModeS);
870 set_ia32_frame_ent(irn, get_ia32_frame_ent(left));
871 set_ia32_ls_mode(irn, get_ia32_ls_mode(left));
873 if (is_ia32_use_frame(left))
874 set_ia32_use_frame(irn);
876 /* connect to Load memory */
877 if (get_irn_arity(irn) == 5) {
879 set_irn_n(irn, 4, get_irn_n(left, 2));
883 set_irn_n(irn, 3, get_irn_n(left, 2));
886 /* disconnect from Load */
887 set_irn_n(irn, 2, noreg_gp);
889 /* If Load has a memory Proj, connect it to the op */
890 mem_proj = get_mem_proj(left);
892 set_Proj_pred(mem_proj, irn);
893 set_Proj_proj(mem_proj, 1);
896 DB((mod, LEVEL_1, "merged with %+F into source AM\n", left));