8 #include "firm_types.h"
15 #include "../benode_t.h"
16 #include "../besched_t.h"
18 #include "ia32_new_nodes.h"
19 #include "bearch_ia32_t.h"
20 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
21 #include "ia32_transform.h"
26 #include "dbginfo_t.h"
30 * Merge the debug info due to a LEA creation.
32 * @param oldn the node
33 * @param n the new constant holding the value
35 #define DBG_OPT_LEA(oldn, n) \
37 hook_merge_nodes(&n, 1, &oldn, 1, FS_BE_IA32_LEA); \
38 __dbg_info_merge_pair(n, oldn, dbg_backend); \
43 #define is_NoMem(irn) (get_irn_op(irn) == op_NoMem)
45 typedef int is_op_func_t(const ir_node *n);
48 * checks if a node represents the NOREG value
50 static int be_is_NoReg(ia32_code_gen_t *cg, const ir_node *irn) {
51 be_abi_irg_t *babi = cg->birg->abi;
52 const arch_register_t *fp_noreg = USE_SSE2(cg) ?
53 &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG];
55 return (be_abi_get_callee_save_irn(babi, &ia32_gp_regs[REG_GP_NOREG]) == irn) ||
56 (be_abi_get_callee_save_irn(babi, fp_noreg) == irn);
61 /*************************************************
64 * | | ___ _ __ ___| |_ __ _ _ __ | |_ ___
65 * | | / _ \| '_ \/ __| __/ _` | '_ \| __/ __|
66 * | |___| (_) | | | \__ \ || (_| | | | | |_\__ \
67 * \_____\___/|_| |_|___/\__\__,_|_| |_|\__|___/
69 *************************************************/
72 * creates a unique ident by adding a number to a tag
74 * @param tag the tag string, must contain a %d if a number
77 static ident *unique_id(const char *tag)
79 static unsigned id = 0;
82 snprintf(str, sizeof(str), tag, ++id);
83 return new_id_from_str(str);
89 * Transforms a SymConst.
91 * @param mod the debug module
92 * @param block the block the new node should belong to
93 * @param node the ir SymConst node
94 * @param mode mode of the SymConst
95 * @return the created ia32 Const node
97 static ir_node *gen_SymConst(ia32_transform_env_t *env) {
99 dbg_info *dbg = env->dbg;
100 ir_mode *mode = env->mode;
101 ir_graph *irg = env->irg;
102 ir_node *block = env->block;
104 if (mode_is_float(mode)) {
105 if (USE_SSE2(env->cg))
106 cnst = new_rd_ia32_fConst(dbg, irg, block, mode);
108 cnst = new_rd_ia32_vfConst(dbg, irg, block, mode);
111 cnst = new_rd_ia32_Const(dbg, irg, block, mode);
113 set_ia32_Const_attr(cnst, env->irn);
118 * Get a primitive type for a mode.
120 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
122 pmap_entry *e = pmap_find(types, mode);
127 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
128 res = new_type_primitive(new_id_from_str(buf), mode);
129 pmap_insert(types, mode, res);
137 * Get an entity that is initialized with a tarval
139 static entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
141 tarval *tv = get_Const_tarval(cnst);
142 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
147 ir_mode *mode = get_irn_mode(cnst);
148 ir_type *tp = get_Const_type(cnst);
149 if (tp == firm_unknown_type)
150 tp = get_prim_type(cg->isa->types, mode);
152 res = new_entity(get_glob_type(), unique_id("ia32FloatCnst_%u"), tp);
154 set_entity_ld_ident(res, get_entity_ident(res));
155 set_entity_visibility(res, visibility_local);
156 set_entity_variability(res, variability_constant);
157 set_entity_allocation(res, allocation_static);
159 /* we create a new entity here: It's initialization must resist on the
161 rem = current_ir_graph;
162 current_ir_graph = get_const_code_irg();
163 set_atomic_ent_value(res, new_Const_type(tv, tp));
164 current_ir_graph = rem;
166 pmap_insert(cg->isa->tv_ent, tv, res);
174 * Transforms a Const.
176 * @param mod the debug module
177 * @param block the block the new node should belong to
178 * @param node the ir Const node
179 * @param mode mode of the Const
180 * @return the created ia32 Const node
182 static ir_node *gen_Const(ia32_transform_env_t *env) {
185 ir_graph *irg = env->irg;
186 ir_node *block = env->block;
187 ir_node *node = env->irn;
188 dbg_info *dbg = env->dbg;
189 ir_mode *mode = env->mode;
191 if (mode_is_float(mode)) {
193 if (! USE_SSE2(env->cg)) {
194 cnst_classify_t clss = classify_Const(node);
196 if (clss == CNST_NULL)
197 return new_rd_ia32_vfldz(dbg, irg, block, mode);
198 else if (clss == CNST_ONE)
199 return new_rd_ia32_vfld1(dbg, irg, block, mode);
201 sym.entity_p = get_entity_for_tv(env->cg, node);
203 cnst = new_rd_SymConst(dbg, irg, block, sym, symconst_addr_ent);
205 cnst = gen_SymConst(env);
208 cnst = new_rd_ia32_Const(dbg, irg, block, get_irn_mode(node));
209 set_ia32_Const_attr(cnst, node);
217 * Transforms (all) Const's into ia32_Const and places them in the
218 * block where they are used (or in the cfg-pred Block in case of Phi's).
219 * Additionally all reference nodes are changed into mode_Is nodes.
221 void ia32_place_consts_set_modes(ir_node *irn, void *env) {
222 ia32_code_gen_t *cg = env;
223 ia32_transform_env_t tenv;
225 ir_node *pred, *cnst;
232 mode = get_irn_mode(irn);
234 /* transform all reference nodes into mode_Is nodes */
235 if (mode_is_reference(mode)) {
237 set_irn_mode(irn, mode);
240 tenv.block = get_nodes_block(irn);
243 DEBUG_ONLY(tenv.mod = cg->mod;)
245 /* Loop over all predecessors and check for Sym/Const nodes */
246 for (i = get_irn_arity(irn) - 1; i >= 0; --i) {
247 pred = get_irn_n(irn, i);
249 opc = get_irn_opcode(pred);
251 tenv.mode = get_irn_mode(pred);
252 tenv.dbg = get_irn_dbg_info(pred);
254 /* If it's a Phi, then we need to create the */
255 /* new Const in it's predecessor block */
257 tenv.block = get_Block_cfgpred_block(get_nodes_block(irn), i);
260 /* put the const into the block where the original const was */
261 if (! cg->opt.placecnst) {
262 tenv.block = get_nodes_block(pred);
267 cnst = gen_Const(&tenv);
270 cnst = gen_SymConst(&tenv);
276 /* if we found a const, then set it */
278 set_irn_n(irn, i, cnst);
285 /********************************************************************************************************
286 * _____ _ _ ____ _ _ _ _ _
287 * | __ \ | | | | / __ \ | | (_) (_) | | (_)
288 * | |__) |__ ___ _ __ | |__ ___ | | ___ | | | |_ __ | |_ _ _ __ ___ _ ______ _| |_ _ ___ _ __
289 * | ___/ _ \/ _ \ '_ \| '_ \ / _ \| |/ _ \ | | | | '_ \| __| | '_ ` _ \| |_ / _` | __| |/ _ \| '_ \
290 * | | | __/ __/ |_) | | | | (_) | | __/ | |__| | |_) | |_| | | | | | | |/ / (_| | |_| | (_) | | | |
291 * |_| \___|\___| .__/|_| |_|\___/|_|\___| \____/| .__/ \__|_|_| |_| |_|_/___\__,_|\__|_|\___/|_| |_|
294 ********************************************************************************************************/
297 * NOTE: THESE PEEPHOLE OPTIMIZATIONS MUST BE CALLED AFTER SCHEDULING AND REGISTER ALLOCATION.
300 static int ia32_cnst_compare(ir_node *n1, ir_node *n2) {
301 return get_ia32_id_cnst(n1) == get_ia32_id_cnst(n2);
305 * Checks for potential CJmp/CJmpAM optimization candidates.
307 static ir_node *ia32_determine_cjmp_cand(ir_node *irn, is_op_func_t *is_op_func) {
308 ir_node *cand = NULL;
309 ir_node *prev = sched_prev(irn);
311 if (is_Block(prev)) {
312 if (get_Block_n_cfgpreds(prev) == 1)
313 prev = get_Block_cfgpred(prev, 0);
318 /* The predecessor must be a ProjX. */
319 if (prev && is_Proj(prev) && get_irn_mode(prev) == mode_X) {
320 prev = get_Proj_pred(prev);
322 if (is_op_func(prev))
329 static int is_TestJmp_cand(const ir_node *irn) {
330 return is_ia32_TestJmp(irn) || is_ia32_And(irn);
334 * Checks if two consecutive arguments of cand matches
335 * the two arguments of irn (TestJmp).
337 static int is_TestJmp_replacement(ir_node *cand, ir_node *irn) {
338 ir_node *in1 = get_irn_n(irn, 0);
339 ir_node *in2 = get_irn_n(irn, 1);
340 int i, n = get_irn_arity(cand);
343 for (i = 0; i < n - 1; i++) {
344 if (get_irn_n(cand, i) == in1 &&
345 get_irn_n(cand, i + 1) == in2)
353 return ia32_cnst_compare(cand, irn);
359 * Tries to replace a TestJmp by a CJmp or CJmpAM (in case of And)
361 static void ia32_optimize_TestJmp(ir_node *irn, ia32_code_gen_t *cg) {
362 ir_node *cand = ia32_determine_cjmp_cand(irn, is_TestJmp_cand);
365 /* we found a possible candidate */
366 replace = cand ? is_TestJmp_replacement(cand, irn) : 0;
369 DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
371 if (is_ia32_And(cand))
372 set_irn_op(irn, op_ia32_CJmpAM);
374 set_irn_op(irn, op_ia32_CJmp);
376 DB((cg->mod, LEVEL_1, "%+F\n", irn));
380 static int is_CondJmp_cand(const ir_node *irn) {
381 return is_ia32_CondJmp(irn) || is_ia32_Sub(irn);
385 * Checks if the arguments of cand are the same of irn.
387 static int is_CondJmp_replacement(ir_node *cand, ir_node *irn) {
388 int i, n = get_irn_arity(cand);
391 for (i = 0; i < n; i++) {
392 if (get_irn_n(cand, i) == get_irn_n(irn, i)) {
399 return ia32_cnst_compare(cand, irn);
405 * Tries to replace a CondJmp by a CJmpAM
407 static void ia32_optimize_CondJmp(ir_node *irn, ia32_code_gen_t *cg) {
408 ir_node *cand = ia32_determine_cjmp_cand(irn, is_CondJmp_cand);
411 /* we found a possible candidate */
412 replace = cand ? is_CondJmp_replacement(cand, irn) : 0;
415 DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
417 set_irn_op(irn, op_ia32_CJmp);
419 DB((cg->mod, LEVEL_1, "%+F\n", irn));
424 * Tries to optimize two following IncSP.
426 static void ia32_optimize_IncSP(ir_node *irn, ia32_code_gen_t *cg) {
427 ir_node *prev = be_get_IncSP_pred(irn);
428 int real_uses = get_irn_n_edges(prev);
430 if (be_is_IncSP(prev) && real_uses == 1) {
431 /* first IncSP has only one IncSP user, kill the first one */
432 unsigned prev_offs = be_get_IncSP_offset(prev);
433 be_stack_dir_t prev_dir = be_get_IncSP_direction(prev);
434 unsigned curr_offs = be_get_IncSP_offset(irn);
435 be_stack_dir_t curr_dir = be_get_IncSP_direction(irn);
437 int new_ofs = prev_offs * (prev_dir == be_stack_dir_expand ? -1 : +1) +
438 curr_offs * (curr_dir == be_stack_dir_expand ? -1 : +1);
442 curr_dir = be_stack_dir_expand;
445 curr_dir = be_stack_dir_shrink;
446 be_set_IncSP_offset(prev, 0);
447 be_set_IncSP_offset(irn, (unsigned)new_ofs);
448 be_set_IncSP_direction(irn, curr_dir);
453 * Performs Peephole Optimizations.
455 void ia32_peephole_optimization(ir_node *irn, void *env) {
456 ia32_code_gen_t *cg = env;
458 if (is_ia32_TestJmp(irn))
459 ia32_optimize_TestJmp(irn, cg);
460 else if (is_ia32_CondJmp(irn))
461 ia32_optimize_CondJmp(irn, cg);
462 else if (be_is_IncSP(irn))
463 ia32_optimize_IncSP(irn, cg);
468 /******************************************************************
470 * /\ | | | | | \/ | | |
471 * / \ __| | __| |_ __ ___ ___ ___| \ / | ___ __| | ___
472 * / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \
473 * / ____ \ (_| | (_| | | | __/\__ \__ \ | | | (_) | (_| | __/
474 * /_/ \_\__,_|\__,_|_| \___||___/___/_| |_|\___/ \__,_|\___|
476 ******************************************************************/
478 static int node_is_ia32_comm(const ir_node *irn) {
479 return is_ia32_irn(irn) ? is_ia32_commutative(irn) : 0;
482 static int ia32_get_irn_n_edges(const ir_node *irn) {
483 const ir_edge_t *edge;
486 foreach_out_edge(irn, edge) {
494 * Returns the first mode_M Proj connected to irn.
496 static ir_node *get_mem_proj(const ir_node *irn) {
497 const ir_edge_t *edge;
500 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
502 foreach_out_edge(irn, edge) {
503 src = get_edge_src_irn(edge);
505 assert(is_Proj(src) && "Proj expected");
507 if (get_irn_mode(src) == mode_M)
515 * Returns the first Proj with mode != mode_M connected to irn.
517 static ir_node *get_res_proj(const ir_node *irn) {
518 const ir_edge_t *edge;
521 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
523 foreach_out_edge(irn, edge) {
524 src = get_edge_src_irn(edge);
526 assert(is_Proj(src) && "Proj expected");
528 if (get_irn_mode(src) != mode_M)
536 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor.
538 * @param pred The node to be checked
539 * @param is_op_func The check-function
540 * @return 1 if conditions are fulfilled, 0 otherwise
542 static int pred_is_specific_node(const ir_node *pred, is_op_func_t *is_op_func) {
543 if (is_Proj(pred) && is_op_func(get_Proj_pred(pred))) {
551 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor
552 * and if the predecessor is in block bl.
554 * @param bl The block
555 * @param pred The node to be checked
556 * @param is_op_func The check-function
557 * @return 1 if conditions are fulfilled, 0 otherwise
559 static int pred_is_specific_nodeblock(const ir_node *bl, const ir_node *pred,
560 int (*is_op_func)(const ir_node *n))
563 pred = get_Proj_pred(pred);
564 if ((bl == get_nodes_block(pred)) && is_op_func(pred)) {
575 * Checks if irn is a candidate for address calculation or address mode.
577 * address calculation (AC):
578 * - none of the operand must be a Load within the same block OR
579 * - all Loads must have more than one user OR
580 * - the irn has a frame entity (it's a former FrameAddr)
583 * - at least one operand has to be a Load within the same block AND
584 * - the load must not have other users than the irn AND
585 * - the irn must not have a frame entity set
587 * @param block The block the Loads must/not be in
588 * @param irn The irn to check
589 * @param check_addr 1 if to check for address calculation, 0 otherwise
590 * return 1 if irn is a candidate for AC or AM, 0 otherwise
592 static int is_candidate(const ir_node *block, const ir_node *irn, int check_addr) {
594 int n, is_cand = check_addr;
596 in = get_irn_n(irn, 2);
598 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
599 n = ia32_get_irn_n_edges(in);
600 is_cand = check_addr ? (n == 1 ? 0 : is_cand) : (n == 1 ? 1 : is_cand);
603 in = get_irn_n(irn, 3);
605 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
606 n = ia32_get_irn_n_edges(in);
607 is_cand = check_addr ? (n == 1 ? 0 : is_cand) : (n == 1 ? 1 : is_cand);
610 is_cand = get_ia32_frame_ent(irn) ? (check_addr ? 1 : 0) : is_cand;
616 * Compares the base and index addr and the load/store entities
617 * and returns 1 if they are equal.
619 static int load_store_addr_is_equal(const ir_node *load, const ir_node *store,
620 const ir_node *addr_b, const ir_node *addr_i)
622 int is_equal = (addr_b == get_irn_n(load, 0)) && (addr_i == get_irn_n(load, 1));
623 entity *lent = get_ia32_frame_ent(load);
624 entity *sent = get_ia32_frame_ent(store);
625 ident *lid = get_ia32_am_sc(load);
626 ident *sid = get_ia32_am_sc(store);
627 char *loffs = get_ia32_am_offs(load);
628 char *soffs = get_ia32_am_offs(store);
630 /* are both entities set and equal? */
631 if (is_equal && (lent || sent))
632 is_equal = lent && sent && (lent == sent);
634 /* are address mode idents set and equal? */
635 if (is_equal && (lid || sid))
636 is_equal = lid && sid && (lid == sid);
638 /* are offsets set and equal */
639 if (is_equal && (loffs || soffs))
640 is_equal = loffs && soffs && strcmp(loffs, soffs) == 0;
642 /* are the load and the store of the same mode? */
643 is_equal = is_equal ? get_ia32_ls_mode(load) == get_ia32_ls_mode(store) : 0;
651 * Folds Add or Sub to LEA if possible
653 static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn, ir_node *noreg) {
654 ir_graph *irg = get_irn_irg(irn);
655 dbg_info *dbg = get_irn_dbg_info(irn);
656 ir_node *block = get_nodes_block(irn);
659 const char *offs_cnst = NULL;
660 char *offs_lea = NULL;
667 ir_node *left, *right, *temp;
668 ir_node *base, *index;
669 ia32_am_flavour_t am_flav;
670 DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
672 if (is_ia32_Add(irn))
675 left = get_irn_n(irn, 2);
676 right = get_irn_n(irn, 3);
678 /* "normalize" arguments in case of add with two operands */
679 if (isadd && ! be_is_NoReg(cg, right)) {
680 /* put LEA == ia32_am_O as right operand */
681 if (is_ia32_Lea(left) && get_ia32_am_flavour(left) == ia32_am_O) {
682 set_irn_n(irn, 2, right);
683 set_irn_n(irn, 3, left);
689 /* put LEA != ia32_am_O as left operand */
690 if (is_ia32_Lea(right) && get_ia32_am_flavour(right) != ia32_am_O) {
691 set_irn_n(irn, 2, right);
692 set_irn_n(irn, 3, left);
698 /* put SHL as left operand iff left is NOT a LEA */
699 if (! is_ia32_Lea(left) && pred_is_specific_node(right, is_ia32_Shl)) {
700 set_irn_n(irn, 2, right);
701 set_irn_n(irn, 3, left);
714 /* check for operation with immediate */
715 if (is_ia32_ImmConst(irn)) {
716 DBG((mod, LEVEL_1, "\tfound op with imm const"));
718 offs_cnst = get_ia32_cnst(irn);
721 else if (is_ia32_ImmSymConst(irn)) {
722 DBG((mod, LEVEL_1, "\tfound op with imm symconst"));
726 am_sc = get_ia32_id_cnst(irn);
727 am_sc_sign = is_ia32_am_sc_sign(irn);
730 /* determine the operand which needs to be checked */
731 if (be_is_NoReg(cg, right)) {
738 /* check if right operand is AMConst (LEA with ia32_am_O) */
739 /* but we can only eat it up if there is no other symconst */
740 /* because the linker won't accept two symconsts */
741 if (! have_am_sc && is_ia32_Lea(temp) && get_ia32_am_flavour(temp) == ia32_am_O) {
742 DBG((mod, LEVEL_1, "\tgot op with LEA am_O"));
744 offs_lea = get_ia32_am_offs(temp);
745 am_sc = get_ia32_am_sc(temp);
746 am_sc_sign = is_ia32_am_sc_sign(temp);
752 /* default for add -> make right operand to index */
756 DBG((mod, LEVEL_1, "\tgot LEA candidate with index %+F\n", index));
758 /* determine the operand which needs to be checked */
760 if (is_ia32_Lea(left)) {
764 /* check for SHL 1,2,3 */
765 if (pred_is_specific_node(temp, is_ia32_Shl)) {
766 temp = get_Proj_pred(temp);
768 if (get_ia32_Immop_tarval(temp)) {
769 scale = get_tarval_long(get_ia32_Immop_tarval(temp));
772 index = get_irn_n(temp, 2);
774 DBG((mod, LEVEL_1, "\tgot scaled index %+F\n", index));
780 if (! be_is_NoReg(cg, index)) {
781 /* if we have index, but left == right -> no base */
785 else if (! is_ia32_Lea(left) && (index != right)) {
786 /* index != right -> we found a good Shl */
787 /* left != LEA -> this Shl was the left operand */
788 /* -> base is right operand */
794 /* Try to assimilate a LEA as left operand */
795 if (is_ia32_Lea(left) && (get_ia32_am_flavour(left) != ia32_am_O)) {
796 ir_node *assim_lea_idx, *assim_lea_base;
798 am_flav = get_ia32_am_flavour(left);
799 assim_lea_base = get_irn_n(left, 0);
800 assim_lea_idx = get_irn_n(left, 1);
803 /* If we have an Add with a real right operand (not NoReg) and */
804 /* the LEA contains already an index calculation then we create */
806 /* If the LEA contains already a frame_entity then we also */
807 /* create a new one otherwise we would loose it. */
808 if ((isadd && ! be_is_NoReg(cg, index) && (am_flav & ia32_I)) || /* no new LEA if index already set */
809 get_ia32_frame_ent(left) || /* no new LEA if stack access */
810 (have_am_sc && get_ia32_am_sc(left)) || /* no new LEA if AM symconst already present */
811 /* at least on of the LEA operands must be NOREG */
812 (!be_is_NoReg(cg, assim_lea_base) && !be_is_NoReg(cg, assim_lea_idx)))
814 DBG((mod, LEVEL_1, "\tleave old LEA, creating new one\n"));
817 DBG((mod, LEVEL_1, "\tgot LEA as left operand ... assimilating\n"));
818 offs = get_ia32_am_offs(left);
819 am_sc = have_am_sc ? am_sc : get_ia32_am_sc(left);
820 have_am_sc = am_sc ? 1 : 0;
821 am_sc_sign = is_ia32_am_sc_sign(left);
822 scale = get_ia32_am_scale(left);
824 if (be_is_NoReg(cg, assim_lea_base) && ! be_is_NoReg(cg, assim_lea_idx)) {
825 /* assimilate index */
826 assert(be_is_NoReg(cg, index) && ! be_is_NoReg(cg, base) && "operand mismatch for LEA assimilation");
827 index = assim_lea_idx;
829 else if (! be_is_NoReg(cg, assim_lea_base) && be_is_NoReg(cg, assim_lea_idx)) {
830 /* assimilate base */
831 assert(! be_is_NoReg(cg, index) && (base == left) && "operand mismatch for LEA assimilation");
832 base = assim_lea_base;
837 /* ok, we can create a new LEA */
839 res = new_rd_ia32_Lea(dbg, irg, block, base, index, mode_Is);
841 /* add the old offset of a previous LEA */
843 add_ia32_am_offs(res, offs);
846 /* add the new offset */
849 add_ia32_am_offs(res, offs_cnst);
852 add_ia32_am_offs(res, offs_lea);
856 /* either lea_O-cnst, -cnst or -lea_O */
859 add_ia32_am_offs(res, offs_lea);
862 sub_ia32_am_offs(res, offs_cnst);
865 sub_ia32_am_offs(res, offs_lea);
869 /* set the address mode symconst */
871 set_ia32_am_sc(res, am_sc);
873 set_ia32_am_sc_sign(res);
876 /* copy the frame entity (could be set in case of Add */
877 /* which was a FrameAddr) */
878 set_ia32_frame_ent(res, get_ia32_frame_ent(irn));
880 if (is_ia32_use_frame(irn))
881 set_ia32_use_frame(res);
884 set_ia32_am_scale(res, scale);
887 /* determine new am flavour */
888 if (offs || offs_cnst || offs_lea) {
891 if (! be_is_NoReg(cg, base)) {
894 if (! be_is_NoReg(cg, index)) {
900 set_ia32_am_flavour(res, am_flav);
902 set_ia32_op_type(res, ia32_AddrModeS);
904 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
906 DBG((mod, LEVEL_1, "\tLEA [%+F + %+F * %d + %s]\n", base, index, scale, get_ia32_am_offs(res)));
908 /* we will exchange it, report here before the Proj is created */
909 DBG_OPT_LEA(irn, res);
911 /* get the result Proj of the Add/Sub */
912 irn = get_res_proj(irn);
914 assert(irn && "Couldn't find result proj");
916 /* exchange the old op with the new LEA */
924 * Optimizes a pattern around irn to address mode if possible.
926 void ia32_optimize_am(ir_node *irn, void *env) {
927 ia32_code_gen_t *cg = env;
931 ir_node *block, *noreg_gp, *noreg_fp;
932 ir_node *left, *right, *temp;
933 ir_node *store, *load, *mem_proj;
934 ir_node *succ, *addr_b, *addr_i;
935 int check_am_src = 0;
936 DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
938 if (! is_ia32_irn(irn))
941 dbg = get_irn_dbg_info(irn);
942 mode = get_irn_mode(irn);
943 block = get_nodes_block(irn);
944 noreg_gp = ia32_new_NoReg_gp(cg);
945 noreg_fp = ia32_new_NoReg_fp(cg);
947 DBG((mod, LEVEL_1, "checking for AM\n"));
949 /* 1st part: check for address calculations and transform the into Lea */
951 /* Following cases can occur: */
952 /* - Sub (l, imm) -> LEA [base - offset] */
953 /* - Sub (l, r == LEA with ia32_am_O) -> LEA [base - offset] */
954 /* - Add (l, imm) -> LEA [base + offset] */
955 /* - Add (l, r == LEA with ia32_am_O) -> LEA [base + offset] */
956 /* - Add (l == LEA with ia32_am_O, r) -> LEA [base + offset] */
957 /* - Add (l, r) -> LEA [base + index * scale] */
958 /* with scale > 1 iff l/r == shl (1,2,3) */
960 if (is_ia32_Sub(irn) || is_ia32_Add(irn)) {
961 left = get_irn_n(irn, 2);
962 right = get_irn_n(irn, 3);
964 /* Do not try to create a LEA if one of the operands is a Load. */
965 /* check is irn is a candidate for address calculation */
966 if (is_candidate(block, irn, 1)) {
967 DBG((mod, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn));
968 res = fold_addr(cg, irn, noreg_gp);
971 DB((mod, LEVEL_1, "transformed into %+F\n", res));
973 DB((mod, LEVEL_1, "not transformed\n"));
977 /* 2nd part: fold following patterns: */
978 /* - Load -> LEA into Load } TODO: If the LEA is used by more than one Load/Store */
979 /* - Store -> LEA into Store } it might be better to keep the LEA */
980 /* - op -> Load into AMop with am_Source */
982 /* - op is am_Source capable AND */
983 /* - the Load is only used by this op AND */
984 /* - the Load is in the same block */
985 /* - Store -> op -> Load into AMop with am_Dest */
987 /* - op is am_Dest capable AND */
988 /* - the Store uses the same address as the Load AND */
989 /* - the Load is only used by this op AND */
990 /* - the Load and Store are in the same block AND */
991 /* - nobody else uses the result of the op */
993 if ((res == irn) && (get_ia32_am_support(irn) != ia32_am_None) && !is_ia32_Lea(irn)) {
994 /* 1st: check for Load/Store -> LEA */
995 if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn)) {
996 left = get_irn_n(irn, 0);
998 if (is_ia32_Lea(left)) {
999 DBG((mod, LEVEL_1, "\nmerging %+F into %+F\n", left, irn));
1001 /* get the AM attributes from the LEA */
1002 add_ia32_am_offs(irn, get_ia32_am_offs(left));
1003 set_ia32_am_scale(irn, get_ia32_am_scale(left));
1004 set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
1006 set_ia32_am_sc(irn, get_ia32_am_sc(left));
1007 if (is_ia32_am_sc_sign(left))
1008 set_ia32_am_sc_sign(irn);
1010 set_ia32_op_type(irn, is_ia32_Ld(irn) ? ia32_AddrModeS : ia32_AddrModeD);
1012 /* set base and index */
1013 set_irn_n(irn, 0, get_irn_n(left, 0));
1014 set_irn_n(irn, 1, get_irn_n(left, 1));
1016 /* clear remat flag */
1017 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1020 /* check if the node is an address mode candidate */
1021 else if (is_candidate(block, irn, 0)) {
1022 DBG((mod, LEVEL_1, "\tfound address mode candidate %+F ... ", irn));
1024 left = get_irn_n(irn, 2);
1025 if (get_irn_arity(irn) == 4) {
1026 /* it's an "unary" operation */
1030 right = get_irn_n(irn, 3);
1033 /* normalize commutative ops */
1034 if (node_is_ia32_comm(irn)) {
1035 /* Assure that right operand is always a Load if there is one */
1036 /* because non-commutative ops can only use Dest AM if the right */
1037 /* operand is a load, so we only need to check right operand. */
1038 if (pred_is_specific_nodeblock(block, left, is_ia32_Ld))
1040 set_irn_n(irn, 2, right);
1041 set_irn_n(irn, 3, left);
1049 /* check for Store -> op -> Load */
1051 /* Store -> op -> Load optimization is only possible if supported by op */
1052 /* and if right operand is a Load */
1053 if ((get_ia32_am_support(irn) & ia32_am_Dest) &&
1054 pred_is_specific_nodeblock(block, right, is_ia32_Ld))
1057 /* An address mode capable op always has a result Proj. */
1058 /* If this Proj is used by more than one other node, we don't need to */
1059 /* check further, otherwise we check for Store and remember the address, */
1060 /* the Store points to. */
1062 succ = get_res_proj(irn);
1063 assert(succ && "Couldn't find result proj");
1069 /* now check for users and Store */
1070 if (ia32_get_irn_n_edges(succ) == 1) {
1071 succ = get_edge_src_irn(get_irn_out_edge_first(succ));
1073 if (is_ia32_fStore(succ) || is_ia32_Store(succ)) {
1075 addr_b = get_irn_n(store, 0);
1077 /* Could be that the Store is connected to the address */
1078 /* calculating LEA while the Load is already transformed. */
1079 if (is_ia32_Lea(addr_b)) {
1081 addr_b = get_irn_n(succ, 0);
1082 addr_i = get_irn_n(succ, 1);
1091 /* we found a Store as single user: Now check for Load */
1093 /* Extra check for commutative ops with two Loads */
1094 /* -> put the interesting Load right */
1095 if (node_is_ia32_comm(irn) &&
1096 pred_is_specific_nodeblock(block, left, is_ia32_Ld))
1098 if ((addr_b == get_irn_n(get_Proj_pred(left), 0)) &&
1099 (addr_i == get_irn_n(get_Proj_pred(left), 1)))
1101 /* We exchange left and right, so it's easier to kill */
1102 /* the correct Load later and to handle unary operations. */
1103 set_irn_n(irn, 2, right);
1104 set_irn_n(irn, 3, left);
1112 /* skip the Proj for easier access */
1113 load = get_Proj_pred(right);
1115 /* Compare Load and Store address */
1116 if (load_store_addr_is_equal(load, store, addr_b, addr_i)) {
1117 /* Right Load is from same address, so we can */
1118 /* disconnect the Load and Store here */
1120 /* set new base, index and attributes */
1121 set_irn_n(irn, 0, addr_b);
1122 set_irn_n(irn, 1, addr_i);
1123 add_ia32_am_offs(irn, get_ia32_am_offs(load));
1124 set_ia32_am_scale(irn, get_ia32_am_scale(load));
1125 set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
1126 set_ia32_op_type(irn, ia32_AddrModeD);
1127 set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
1128 set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
1130 set_ia32_am_sc(irn, get_ia32_am_sc(load));
1131 if (is_ia32_am_sc_sign(load))
1132 set_ia32_am_sc_sign(irn);
1134 if (is_ia32_use_frame(load))
1135 set_ia32_use_frame(irn);
1137 /* connect to Load memory and disconnect Load */
1138 if (get_irn_arity(irn) == 5) {
1140 set_irn_n(irn, 4, get_irn_n(load, 2));
1141 set_irn_n(irn, 3, noreg_gp);
1145 set_irn_n(irn, 3, get_irn_n(load, 2));
1146 set_irn_n(irn, 2, noreg_gp);
1149 /* connect the memory Proj of the Store to the op */
1150 mem_proj = get_mem_proj(store);
1151 set_Proj_pred(mem_proj, irn);
1152 set_Proj_proj(mem_proj, 1);
1154 /* clear remat flag */
1155 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1157 DB((mod, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
1160 else if (get_ia32_am_support(irn) & ia32_am_Source) {
1161 /* There was no store, check if we still can optimize for source address mode */
1164 } /* if (support AM Dest) */
1165 else if (get_ia32_am_support(irn) & ia32_am_Source) {
1166 /* op doesn't support am AM Dest -> check for AM Source */
1170 /* normalize commutative ops */
1171 if (node_is_ia32_comm(irn)) {
1172 /* Assure that left operand is always a Load if there is one */
1173 /* because non-commutative ops can only use Source AM if the */
1174 /* left operand is a Load, so we only need to check the left */
1175 /* operand afterwards. */
1176 if (pred_is_specific_nodeblock(block, right, is_ia32_Ld)) {
1177 set_irn_n(irn, 2, right);
1178 set_irn_n(irn, 3, left);
1186 /* optimize op -> Load iff Load is only used by this op */
1187 /* and left operand is a Load which only used by this irn */
1189 pred_is_specific_nodeblock(block, left, is_ia32_Ld) &&
1190 (ia32_get_irn_n_edges(left) == 1))
1192 left = get_Proj_pred(left);
1194 addr_b = get_irn_n(left, 0);
1195 addr_i = get_irn_n(left, 1);
1197 /* set new base, index and attributes */
1198 set_irn_n(irn, 0, addr_b);
1199 set_irn_n(irn, 1, addr_i);
1200 add_ia32_am_offs(irn, get_ia32_am_offs(left));
1201 set_ia32_am_scale(irn, get_ia32_am_scale(left));
1202 set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
1203 set_ia32_op_type(irn, ia32_AddrModeS);
1204 set_ia32_frame_ent(irn, get_ia32_frame_ent(left));
1205 set_ia32_ls_mode(irn, get_ia32_ls_mode(left));
1207 set_ia32_am_sc(irn, get_ia32_am_sc(left));
1208 if (is_ia32_am_sc_sign(left))
1209 set_ia32_am_sc_sign(irn);
1211 /* clear remat flag */
1212 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1214 if (is_ia32_use_frame(left))
1215 set_ia32_use_frame(irn);
1217 /* connect to Load memory */
1218 if (get_irn_arity(irn) == 5) {
1220 set_irn_n(irn, 4, get_irn_n(left, 2));
1224 set_irn_n(irn, 3, get_irn_n(left, 2));
1227 /* disconnect from Load */
1228 set_irn_n(irn, 2, noreg_gp);
1230 /* If Load has a memory Proj, connect it to the op */
1231 mem_proj = get_mem_proj(left);
1233 set_Proj_pred(mem_proj, irn);
1234 set_Proj_proj(mem_proj, 1);
1237 DB((mod, LEVEL_1, "merged with %+F into source AM\n", left));