8 #include "firm_types.h"
16 #include "../benode_t.h"
17 #include "../besched_t.h"
19 #include "ia32_new_nodes.h"
20 #include "bearch_ia32_t.h"
21 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
22 #include "ia32_transform.h"
23 #include "ia32_dbg_stat.h"
26 #define is_NoMem(irn) (get_irn_op(irn) == op_NoMem)
28 typedef int is_op_func_t(const ir_node *n);
31 * checks if a node represents the NOREG value
33 static int be_is_NoReg(ia32_code_gen_t *cg, const ir_node *irn) {
34 be_abi_irg_t *babi = cg->birg->abi;
35 const arch_register_t *fp_noreg = USE_SSE2(cg) ?
36 &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG];
38 return (be_abi_get_callee_save_irn(babi, &ia32_gp_regs[REG_GP_NOREG]) == irn) ||
39 (be_abi_get_callee_save_irn(babi, fp_noreg) == irn);
44 /*************************************************
47 * | | ___ _ __ ___| |_ __ _ _ __ | |_ ___
48 * | | / _ \| '_ \/ __| __/ _` | '_ \| __/ __|
49 * | |___| (_) | | | \__ \ || (_| | | | | |_\__ \
50 * \_____\___/|_| |_|___/\__\__,_|_| |_|\__|___/
52 *************************************************/
55 * creates a unique ident by adding a number to a tag
57 * @param tag the tag string, must contain a %d if a number
60 static ident *unique_id(const char *tag)
62 static unsigned id = 0;
65 snprintf(str, sizeof(str), tag, ++id);
66 return new_id_from_str(str);
72 * Transforms a SymConst.
74 * @param mod the debug module
75 * @param block the block the new node should belong to
76 * @param node the ir SymConst node
77 * @param mode mode of the SymConst
78 * @return the created ia32 Const node
80 static ir_node *gen_SymConst(ia32_transform_env_t *env) {
82 dbg_info *dbg = env->dbg;
83 ir_mode *mode = env->mode;
84 ir_graph *irg = env->irg;
85 ir_node *block = env->block;
87 if (mode_is_float(mode)) {
89 if (USE_SSE2(env->cg))
90 cnst = new_rd_ia32_xConst(dbg, irg, block, get_irg_no_mem(irg), mode);
92 cnst = new_rd_ia32_vfConst(dbg, irg, block, get_irg_no_mem(irg), mode);
95 cnst = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode);
97 set_ia32_Const_attr(cnst, env->irn);
103 * Get a primitive type for a mode.
105 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
107 pmap_entry *e = pmap_find(types, mode);
112 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
113 res = new_type_primitive(new_id_from_str(buf), mode);
114 pmap_insert(types, mode, res);
122 * Get an entity that is initialized with a tarval
124 static entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
126 tarval *tv = get_Const_tarval(cnst);
127 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
132 ir_mode *mode = get_irn_mode(cnst);
133 ir_type *tp = get_Const_type(cnst);
134 if (tp == firm_unknown_type)
135 tp = get_prim_type(cg->isa->types, mode);
137 res = new_entity(get_glob_type(), unique_id("ia32FloatCnst_%u"), tp);
139 set_entity_ld_ident(res, get_entity_ident(res));
140 set_entity_visibility(res, visibility_local);
141 set_entity_variability(res, variability_constant);
142 set_entity_allocation(res, allocation_static);
144 /* we create a new entity here: It's initialization must resist on the
146 rem = current_ir_graph;
147 current_ir_graph = get_const_code_irg();
148 set_atomic_ent_value(res, new_Const_type(tv, tp));
149 current_ir_graph = rem;
151 pmap_insert(cg->isa->tv_ent, tv, res);
159 * Transforms a Const.
161 * @param mod the debug module
162 * @param block the block the new node should belong to
163 * @param node the ir Const node
164 * @param mode mode of the Const
165 * @return the created ia32 Const node
167 static ir_node *gen_Const(ia32_transform_env_t *env) {
170 ir_graph *irg = env->irg;
171 ir_node *block = env->block;
172 ir_node *node = env->irn;
173 dbg_info *dbg = env->dbg;
174 ir_mode *mode = env->mode;
176 if (mode_is_float(mode)) {
178 if (! USE_SSE2(env->cg)) {
179 cnst_classify_t clss = classify_Const(node);
181 if (clss == CNST_NULL)
182 return new_rd_ia32_vfldz(dbg, irg, block, mode);
183 else if (clss == CNST_ONE)
184 return new_rd_ia32_vfld1(dbg, irg, block, mode);
186 sym.entity_p = get_entity_for_tv(env->cg, node);
188 cnst = new_rd_SymConst(dbg, irg, block, sym, symconst_addr_ent);
190 cnst = gen_SymConst(env);
193 cnst = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), get_irn_mode(node));
194 set_ia32_Const_attr(cnst, node);
202 * Transforms (all) Const's into ia32_Const and places them in the
203 * block where they are used (or in the cfg-pred Block in case of Phi's).
204 * Additionally all reference nodes are changed into mode_Is nodes.
206 void ia32_place_consts_set_modes(ir_node *irn, void *env) {
207 ia32_code_gen_t *cg = env;
208 ia32_transform_env_t tenv;
210 ir_node *pred, *cnst;
217 mode = get_irn_mode(irn);
219 /* transform all reference nodes into mode_Is nodes */
220 if (mode_is_reference(mode)) {
222 set_irn_mode(irn, mode);
225 tenv.block = get_nodes_block(irn);
228 DEBUG_ONLY(tenv.mod = cg->mod;)
230 /* Loop over all predecessors and check for Sym/Const nodes */
231 for (i = get_irn_arity(irn) - 1; i >= 0; --i) {
232 pred = get_irn_n(irn, i);
234 opc = get_irn_opcode(pred);
236 tenv.mode = get_irn_mode(pred);
237 tenv.dbg = get_irn_dbg_info(pred);
239 /* If it's a Phi, then we need to create the */
240 /* new Const in it's predecessor block */
242 tenv.block = get_Block_cfgpred_block(get_nodes_block(irn), i);
245 /* put the const into the block where the original const was */
246 if (! (cg->opt & IA32_OPT_PLACECNST)) {
247 tenv.block = get_nodes_block(pred);
252 cnst = gen_Const(&tenv);
255 cnst = gen_SymConst(&tenv);
261 /* if we found a const, then set it */
263 set_irn_n(irn, i, cnst);
270 /********************************************************************************************************
271 * _____ _ _ ____ _ _ _ _ _
272 * | __ \ | | | | / __ \ | | (_) (_) | | (_)
273 * | |__) |__ ___ _ __ | |__ ___ | | ___ | | | |_ __ | |_ _ _ __ ___ _ ______ _| |_ _ ___ _ __
274 * | ___/ _ \/ _ \ '_ \| '_ \ / _ \| |/ _ \ | | | | '_ \| __| | '_ ` _ \| |_ / _` | __| |/ _ \| '_ \
275 * | | | __/ __/ |_) | | | | (_) | | __/ | |__| | |_) | |_| | | | | | | |/ / (_| | |_| | (_) | | | |
276 * |_| \___|\___| .__/|_| |_|\___/|_|\___| \____/| .__/ \__|_|_| |_| |_|_/___\__,_|\__|_|\___/|_| |_|
279 ********************************************************************************************************/
282 * NOTE: THESE PEEPHOLE OPTIMIZATIONS MUST BE CALLED AFTER SCHEDULING AND REGISTER ALLOCATION.
285 static int ia32_cnst_compare(ir_node *n1, ir_node *n2) {
286 return get_ia32_id_cnst(n1) == get_ia32_id_cnst(n2);
290 * Checks for potential CJmp/CJmpAM optimization candidates.
292 static ir_node *ia32_determine_cjmp_cand(ir_node *irn, is_op_func_t *is_op_func) {
293 ir_node *cand = NULL;
294 ir_node *prev = sched_prev(irn);
296 if (is_Block(prev)) {
297 if (get_Block_n_cfgpreds(prev) == 1)
298 prev = get_Block_cfgpred(prev, 0);
303 /* The predecessor must be a ProjX. */
304 if (prev && is_Proj(prev) && get_irn_mode(prev) == mode_X) {
305 prev = get_Proj_pred(prev);
307 if (is_op_func(prev))
314 static int is_TestJmp_cand(const ir_node *irn) {
315 return is_ia32_TestJmp(irn) || is_ia32_And(irn);
319 * Checks if two consecutive arguments of cand matches
320 * the two arguments of irn (TestJmp).
322 static int is_TestJmp_replacement(ir_node *cand, ir_node *irn) {
323 ir_node *in1 = get_irn_n(irn, 0);
324 ir_node *in2 = get_irn_n(irn, 1);
325 int i, n = get_irn_arity(cand);
328 for (i = 0; i < n - 1; i++) {
329 if (get_irn_n(cand, i) == in1 &&
330 get_irn_n(cand, i + 1) == in2)
338 return ia32_cnst_compare(cand, irn);
344 * Tries to replace a TestJmp by a CJmp or CJmpAM (in case of And)
346 static void ia32_optimize_TestJmp(ir_node *irn, ia32_code_gen_t *cg) {
347 ir_node *cand = ia32_determine_cjmp_cand(irn, is_TestJmp_cand);
350 /* we found a possible candidate */
351 replace = cand ? is_TestJmp_replacement(cand, irn) : 0;
354 DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
356 if (is_ia32_And(cand))
357 set_irn_op(irn, op_ia32_CJmpAM);
359 set_irn_op(irn, op_ia32_CJmp);
361 DB((cg->mod, LEVEL_1, "%+F\n", irn));
365 static int is_CondJmp_cand(const ir_node *irn) {
366 return is_ia32_CondJmp(irn) || is_ia32_Sub(irn);
370 * Checks if the arguments of cand are the same of irn.
372 static int is_CondJmp_replacement(ir_node *cand, ir_node *irn) {
373 int i, n = get_irn_arity(cand);
376 for (i = 0; i < n; i++) {
377 if (get_irn_n(cand, i) != get_irn_n(irn, i)) {
384 return ia32_cnst_compare(cand, irn);
390 * Tries to replace a CondJmp by a CJmpAM
392 static void ia32_optimize_CondJmp(ir_node *irn, ia32_code_gen_t *cg) {
393 ir_node *cand = ia32_determine_cjmp_cand(irn, is_CondJmp_cand);
396 /* we found a possible candidate */
397 replace = cand ? is_CondJmp_replacement(cand, irn) : 0;
400 DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
403 set_irn_op(irn, op_ia32_CJmpAM);
405 DB((cg->mod, LEVEL_1, "%+F\n", irn));
410 * Creates a Push from Store(IncSP(gp_reg_size))
412 static void ia32_create_Push(ir_node *irn, ia32_code_gen_t *cg) {
413 ir_node *sp = get_irn_n(irn, 0);
414 ir_node *val, *next, *push, *bl, *proj_M, *proj_res, *old_proj_M;
415 const ir_edge_t *edge;
417 if (get_ia32_am_offs(irn) || !be_is_IncSP(sp))
420 if (arch_get_irn_register(cg->arch_env, get_irn_n(irn, 1)) !=
421 &ia32_gp_regs[REG_GP_NOREG])
424 val = get_irn_n(irn, 2);
425 if (mode_is_float(get_irn_mode(val)))
428 if (be_get_IncSP_direction(sp) != be_stack_dir_expand ||
429 be_get_IncSP_offset(sp) != get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode))
432 /* ok, translate into Push */
433 edge = get_irn_out_edge_first(irn);
434 old_proj_M = get_edge_src_irn(edge);
436 next = sched_next(irn);
440 bl = get_nodes_block(irn);
441 push = new_rd_ia32_Push(NULL, current_ir_graph, bl,
442 be_get_IncSP_pred(sp), val, be_get_IncSP_mem(sp));
443 proj_res = new_r_Proj(current_ir_graph, bl, push, get_irn_mode(sp), pn_ia32_Push_stack);
444 proj_M = new_r_Proj(current_ir_graph, bl, push, mode_M, pn_ia32_Push_M);
446 /* copy a possible constant from the store */
447 set_ia32_id_cnst(push, get_ia32_id_cnst(irn));
448 set_ia32_immop_type(push, get_ia32_immop_type(irn));
450 /* the push must have SP out register */
451 arch_set_irn_register(cg->arch_env, push, arch_get_irn_register(cg->arch_env, sp));
453 exchange(old_proj_M, proj_M);
454 exchange(sp, proj_res);
455 sched_add_before(next, push);
456 sched_add_after(push, proj_res);
460 * Creates a Pop from IncSP(Load(sp))
462 static void ia32_create_Pop(ir_node *irn, ia32_code_gen_t *cg) {
463 ir_node *old_proj_M = be_get_IncSP_mem(irn);
464 ir_node *load = skip_Proj(old_proj_M);
465 ir_node *old_proj_res = NULL;
466 ir_node *bl, *pop, *next, *proj_res, *proj_sp, *proj_M;
467 const ir_edge_t *edge;
468 const arch_register_t *reg, *sp;
470 if (! is_ia32_Load(load) || get_ia32_am_offs(load))
473 if (arch_get_irn_register(cg->arch_env, get_irn_n(load, 1)) !=
474 &ia32_gp_regs[REG_GP_NOREG])
476 if (arch_get_irn_register(cg->arch_env, get_irn_n(load, 0)) != cg->isa->arch_isa.sp)
479 /* ok, translate into pop */
480 foreach_out_edge(load, edge) {
481 ir_node *succ = get_edge_src_irn(edge);
482 if (succ != old_proj_M) {
487 if (! old_proj_res) {
489 return; /* should not happen */
492 bl = get_nodes_block(load);
494 /* IncSP is typically scheduled after the load, so remove it first */
496 next = sched_next(old_proj_res);
497 sched_remove(old_proj_res);
500 reg = arch_get_irn_register(cg->arch_env, load);
501 sp = arch_get_irn_register(cg->arch_env, irn);
503 pop = new_rd_ia32_Pop(NULL, current_ir_graph, bl, get_irn_n(irn, 0), get_irn_n(load, 2));
504 proj_res = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(old_proj_res), pn_ia32_Pop_res);
505 proj_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(irn), pn_ia32_Pop_stack);
506 proj_M = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
508 exchange(old_proj_M, proj_M);
509 exchange(old_proj_res, proj_res);
510 exchange(irn, proj_sp);
512 arch_set_irn_register(cg->arch_env, proj_res, reg);
513 arch_set_irn_register(cg->arch_env, proj_sp, sp);
515 sched_add_before(next, proj_sp);
516 sched_add_before(proj_sp, proj_res);
517 sched_add_before(proj_res,pop);
521 * Tries to optimize two following IncSP.
523 static void ia32_optimize_IncSP(ir_node *irn, ia32_code_gen_t *cg) {
524 ir_node *prev = be_get_IncSP_pred(irn);
525 int real_uses = get_irn_n_edges(prev);
527 if (be_is_IncSP(prev) && real_uses == 1) {
528 /* first IncSP has only one IncSP user, kill the first one */
529 unsigned prev_offs = be_get_IncSP_offset(prev);
530 be_stack_dir_t prev_dir = be_get_IncSP_direction(prev);
531 unsigned curr_offs = be_get_IncSP_offset(irn);
532 be_stack_dir_t curr_dir = be_get_IncSP_direction(irn);
534 int new_ofs = prev_offs * (prev_dir == be_stack_dir_expand ? -1 : +1) +
535 curr_offs * (curr_dir == be_stack_dir_expand ? -1 : +1);
539 curr_dir = be_stack_dir_expand;
542 curr_dir = be_stack_dir_shrink;
543 be_set_IncSP_offset(prev, 0);
544 be_set_IncSP_offset(irn, (unsigned)new_ofs);
545 be_set_IncSP_direction(irn, curr_dir);
547 /* Omit the optimized IncSP */
548 be_set_IncSP_pred(irn, be_get_IncSP_pred(prev));
553 * Performs Peephole Optimizations.
555 void ia32_peephole_optimization(ir_node *irn, void *env) {
556 ia32_code_gen_t *cg = env;
558 if (is_ia32_TestJmp(irn))
559 ia32_optimize_TestJmp(irn, cg);
560 else if (is_ia32_CondJmp(irn))
561 ia32_optimize_CondJmp(irn, cg);
562 /* seems to be buggy when using Pushes */
563 // else if (be_is_IncSP(irn))
564 // ia32_optimize_IncSP(irn, cg);
565 else if (is_ia32_Store(irn))
566 ia32_create_Push(irn, cg);
571 /******************************************************************
573 * /\ | | | | | \/ | | |
574 * / \ __| | __| |_ __ ___ ___ ___| \ / | ___ __| | ___
575 * / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \
576 * / ____ \ (_| | (_| | | | __/\__ \__ \ | | | (_) | (_| | __/
577 * /_/ \_\__,_|\__,_|_| \___||___/___/_| |_|\___/ \__,_|\___|
579 ******************************************************************/
581 static int node_is_ia32_comm(const ir_node *irn) {
582 return is_ia32_irn(irn) ? is_ia32_commutative(irn) : 0;
585 static int ia32_get_irn_n_edges(const ir_node *irn) {
586 const ir_edge_t *edge;
589 foreach_out_edge(irn, edge) {
597 * Returns the first mode_M Proj connected to irn.
599 static ir_node *get_mem_proj(const ir_node *irn) {
600 const ir_edge_t *edge;
603 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
605 foreach_out_edge(irn, edge) {
606 src = get_edge_src_irn(edge);
608 assert(is_Proj(src) && "Proj expected");
610 if (get_irn_mode(src) == mode_M)
618 * Returns the first Proj with mode != mode_M connected to irn.
620 static ir_node *get_res_proj(const ir_node *irn) {
621 const ir_edge_t *edge;
624 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
626 foreach_out_edge(irn, edge) {
627 src = get_edge_src_irn(edge);
629 assert(is_Proj(src) && "Proj expected");
631 if (get_irn_mode(src) != mode_M)
639 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor.
641 * @param pred The node to be checked
642 * @param is_op_func The check-function
643 * @return 1 if conditions are fulfilled, 0 otherwise
645 static int pred_is_specific_node(const ir_node *pred, is_op_func_t *is_op_func) {
646 if (is_Proj(pred) && is_op_func(get_Proj_pred(pred))) {
654 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor
655 * and if the predecessor is in block bl.
657 * @param bl The block
658 * @param pred The node to be checked
659 * @param is_op_func The check-function
660 * @return 1 if conditions are fulfilled, 0 otherwise
662 static int pred_is_specific_nodeblock(const ir_node *bl, const ir_node *pred,
663 int (*is_op_func)(const ir_node *n))
666 pred = get_Proj_pred(pred);
667 if ((bl == get_nodes_block(pred)) && is_op_func(pred)) {
678 * Checks if irn is a candidate for address calculation or address mode.
680 * address calculation (AC):
681 * - none of the operand must be a Load within the same block OR
682 * - all Loads must have more than one user OR
683 * - the irn has a frame entity (it's a former FrameAddr)
686 * - at least one operand has to be a Load within the same block AND
687 * - the load must not have other users than the irn AND
688 * - the irn must not have a frame entity set
690 * @param block The block the Loads must/not be in
691 * @param irn The irn to check
692 * @param check_addr 1 if to check for address calculation, 0 otherwise
693 * return 1 if irn is a candidate for AC or AM, 0 otherwise
695 static int is_candidate(const ir_node *block, const ir_node *irn, int check_addr) {
697 int n, is_cand = check_addr;
699 in = get_irn_n(irn, 2);
701 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
702 n = ia32_get_irn_n_edges(in);
703 is_cand = check_addr ? (n == 1 ? 0 : is_cand) : (n == 1 ? 1 : is_cand);
706 in = get_irn_n(irn, 3);
708 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
709 n = ia32_get_irn_n_edges(in);
710 is_cand = check_addr ? (n == 1 ? 0 : is_cand) : (n == 1 ? 1 : is_cand);
713 is_cand = get_ia32_frame_ent(irn) ? (check_addr ? 1 : 0) : is_cand;
719 * Compares the base and index addr and the load/store entities
720 * and returns 1 if they are equal.
722 static int load_store_addr_is_equal(const ir_node *load, const ir_node *store,
723 const ir_node *addr_b, const ir_node *addr_i)
725 int is_equal = (addr_b == get_irn_n(load, 0)) && (addr_i == get_irn_n(load, 1));
726 entity *lent = get_ia32_frame_ent(load);
727 entity *sent = get_ia32_frame_ent(store);
728 ident *lid = get_ia32_am_sc(load);
729 ident *sid = get_ia32_am_sc(store);
730 char *loffs = get_ia32_am_offs(load);
731 char *soffs = get_ia32_am_offs(store);
733 /* are both entities set and equal? */
734 if (is_equal && (lent || sent))
735 is_equal = lent && sent && (lent == sent);
737 /* are address mode idents set and equal? */
738 if (is_equal && (lid || sid))
739 is_equal = lid && sid && (lid == sid);
741 /* are offsets set and equal */
742 if (is_equal && (loffs || soffs))
743 is_equal = loffs && soffs && strcmp(loffs, soffs) == 0;
745 /* are the load and the store of the same mode? */
746 is_equal = is_equal ? get_ia32_ls_mode(load) == get_ia32_ls_mode(store) : 0;
751 typedef enum _ia32_take_lea_attr {
752 IA32_LEA_ATTR_NONE = 0,
753 IA32_LEA_ATTR_BASE = (1 << 0),
754 IA32_LEA_ATTR_INDEX = (1 << 1),
755 IA32_LEA_ATTR_OFFS = (1 << 2),
756 IA32_LEA_ATTR_SCALE = (1 << 3),
757 IA32_LEA_ATTR_AMSC = (1 << 4),
758 IA32_LEA_ATTR_FENT = (1 << 5)
759 } ia32_take_lea_attr;
762 * Decides if we have to keep the LEA operand or if we can assimilate it.
764 static int do_new_lea(ir_node *irn, ir_node *base, ir_node *index, ir_node *lea,
765 int have_am_sc, ia32_code_gen_t *cg)
767 ir_node *lea_base = get_irn_n(lea, 0);
768 ir_node *lea_idx = get_irn_n(lea, 1);
769 entity *irn_ent = get_ia32_frame_ent(irn);
770 entity *lea_ent = get_ia32_frame_ent(lea);
772 int is_noreg_base = be_is_NoReg(cg, base);
773 int is_noreg_index = be_is_NoReg(cg, index);
774 ia32_am_flavour_t am_flav = get_ia32_am_flavour(lea);
776 /* If the Add and the LEA both have a different frame entity set: keep */
777 if (irn_ent && lea_ent && (irn_ent != lea_ent))
778 return IA32_LEA_ATTR_NONE;
779 else if (! irn_ent && lea_ent)
780 ret_val |= IA32_LEA_ATTR_FENT;
782 /* If the Add and the LEA both have already an address mode symconst: keep */
783 if (have_am_sc && get_ia32_am_sc(lea))
784 return IA32_LEA_ATTR_NONE;
785 else if (get_ia32_am_sc(lea))
786 ret_val |= IA32_LEA_ATTR_AMSC;
788 /* Check the different base-index combinations */
790 if (! is_noreg_base && ! is_noreg_index) {
791 /* Assimilate if base is the lea and the LEA is just a Base + Offset calculation */
792 if ((base == lea) && ! (am_flav & ia32_I ? 1 : 0)) {
793 if (am_flav & ia32_O)
794 ret_val |= IA32_LEA_ATTR_OFFS;
796 ret_val |= IA32_LEA_ATTR_BASE;
799 return IA32_LEA_ATTR_NONE;
801 else if (! is_noreg_base && is_noreg_index) {
802 /* Base is set but index not */
804 /* Base points to LEA: assimilate everything */
805 if (am_flav & ia32_O)
806 ret_val |= IA32_LEA_ATTR_OFFS;
807 if (am_flav & ia32_S)
808 ret_val |= IA32_LEA_ATTR_SCALE;
809 if (am_flav & ia32_I)
810 ret_val |= IA32_LEA_ATTR_INDEX;
812 ret_val |= IA32_LEA_ATTR_BASE;
814 else if (am_flav & ia32_B ? 0 : 1) {
815 /* Base is not the LEA but the LEA is an index only calculation: assimilate */
816 if (am_flav & ia32_O)
817 ret_val |= IA32_LEA_ATTR_OFFS;
818 if (am_flav & ia32_S)
819 ret_val |= IA32_LEA_ATTR_SCALE;
821 ret_val |= IA32_LEA_ATTR_INDEX;
824 return IA32_LEA_ATTR_NONE;
826 else if (is_noreg_base && ! is_noreg_index) {
827 /* Index is set but not base */
829 /* Index points to LEA: assimilate everything */
830 if (am_flav & ia32_O)
831 ret_val |= IA32_LEA_ATTR_OFFS;
832 if (am_flav & ia32_S)
833 ret_val |= IA32_LEA_ATTR_SCALE;
834 if (am_flav & ia32_B)
835 ret_val |= IA32_LEA_ATTR_BASE;
837 ret_val |= IA32_LEA_ATTR_INDEX;
839 else if (am_flav & ia32_I ? 0 : 1) {
840 /* Index is not the LEA but the LEA is a base only calculation: assimilate */
841 if (am_flav & ia32_O)
842 ret_val |= IA32_LEA_ATTR_OFFS;
843 if (am_flav & ia32_S)
844 ret_val |= IA32_LEA_ATTR_SCALE;
846 ret_val |= IA32_LEA_ATTR_BASE;
849 return IA32_LEA_ATTR_NONE;
852 assert(0 && "There must have been set base or index");
860 * Folds Add or Sub to LEA if possible
862 static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn, ir_node *noreg) {
863 ir_graph *irg = get_irn_irg(irn);
864 dbg_info *dbg = get_irn_dbg_info(irn);
865 ir_node *block = get_nodes_block(irn);
867 ir_node *shift = NULL;
868 ir_node *lea_o = NULL;
871 const char *offs_cnst = NULL;
872 char *offs_lea = NULL;
879 entity *lea_ent = NULL;
880 ir_node *left, *right, *temp;
881 ir_node *base, *index;
882 ia32_am_flavour_t am_flav;
883 DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
885 if (is_ia32_Add(irn))
888 left = get_irn_n(irn, 2);
889 right = get_irn_n(irn, 3);
891 /* "normalize" arguments in case of add with two operands */
892 if (isadd && ! be_is_NoReg(cg, right)) {
893 /* put LEA == ia32_am_O as right operand */
894 if (is_ia32_Lea(left) && get_ia32_am_flavour(left) == ia32_am_O) {
895 set_irn_n(irn, 2, right);
896 set_irn_n(irn, 3, left);
902 /* put LEA != ia32_am_O as left operand */
903 if (is_ia32_Lea(right) && get_ia32_am_flavour(right) != ia32_am_O) {
904 set_irn_n(irn, 2, right);
905 set_irn_n(irn, 3, left);
911 /* put SHL as left operand iff left is NOT a LEA */
912 if (! is_ia32_Lea(left) && pred_is_specific_node(right, is_ia32_Shl)) {
913 set_irn_n(irn, 2, right);
914 set_irn_n(irn, 3, left);
927 /* check for operation with immediate */
928 if (is_ia32_ImmConst(irn)) {
929 DBG((mod, LEVEL_1, "\tfound op with imm const"));
931 offs_cnst = get_ia32_cnst(irn);
934 else if (is_ia32_ImmSymConst(irn)) {
935 DBG((mod, LEVEL_1, "\tfound op with imm symconst"));
939 am_sc = get_ia32_id_cnst(irn);
940 am_sc_sign = is_ia32_am_sc_sign(irn);
943 /* determine the operand which needs to be checked */
944 if (be_is_NoReg(cg, right)) {
951 /* check if right operand is AMConst (LEA with ia32_am_O) */
952 /* but we can only eat it up if there is no other symconst */
953 /* because the linker won't accept two symconsts */
954 if (! have_am_sc && is_ia32_Lea(temp) && get_ia32_am_flavour(temp) == ia32_am_O) {
955 DBG((mod, LEVEL_1, "\tgot op with LEA am_O"));
957 offs_lea = get_ia32_am_offs(temp);
958 am_sc = get_ia32_am_sc(temp);
959 am_sc_sign = is_ia32_am_sc_sign(temp);
966 /* default for add -> make right operand to index */
970 DBG((mod, LEVEL_1, "\tgot LEA candidate with index %+F\n", index));
972 /* determine the operand which needs to be checked */
974 if (is_ia32_Lea(left)) {
978 /* check for SHL 1,2,3 */
979 if (pred_is_specific_node(temp, is_ia32_Shl)) {
980 temp = get_Proj_pred(temp);
983 if (get_ia32_Immop_tarval(temp)) {
984 scale = get_tarval_long(get_ia32_Immop_tarval(temp));
987 index = get_irn_n(temp, 2);
989 DBG((mod, LEVEL_1, "\tgot scaled index %+F\n", index));
999 if (! be_is_NoReg(cg, index)) {
1000 /* if we have index, but left == right -> no base */
1001 if (left == right) {
1004 else if (! is_ia32_Lea(left) && (index != right)) {
1005 /* index != right -> we found a good Shl */
1006 /* left != LEA -> this Shl was the left operand */
1007 /* -> base is right operand */
1013 /* Try to assimilate a LEA as left operand */
1014 if (is_ia32_Lea(left) && (get_ia32_am_flavour(left) != ia32_am_O)) {
1015 /* check if we can assimilate the LEA */
1016 int take_attr = do_new_lea(irn, base, index, left, have_am_sc, cg);
1018 if (take_attr == IA32_LEA_ATTR_NONE) {
1019 DBG((mod, LEVEL_1, "\tleave old LEA, creating new one\n"));
1022 DBG((mod, LEVEL_1, "\tgot LEA as left operand ... assimilating\n"));
1023 lea = left; /* for statistics */
1025 if (take_attr & IA32_LEA_ATTR_OFFS)
1026 offs = get_ia32_am_offs(left);
1028 if (take_attr & IA32_LEA_ATTR_AMSC) {
1029 am_sc = get_ia32_am_sc(left);
1031 am_sc_sign = is_ia32_am_sc_sign(left);
1034 if (take_attr & IA32_LEA_ATTR_SCALE)
1035 scale = get_ia32_am_scale(left);
1037 if (take_attr & IA32_LEA_ATTR_BASE)
1038 base = get_irn_n(left, 0);
1040 if (take_attr & IA32_LEA_ATTR_INDEX)
1041 index = get_irn_n(left, 1);
1043 if (take_attr & IA32_LEA_ATTR_FENT)
1044 lea_ent = get_ia32_frame_ent(left);
1048 /* ok, we can create a new LEA */
1050 res = new_rd_ia32_Lea(dbg, irg, block, base, index, mode_Is);
1052 /* add the old offset of a previous LEA */
1054 add_ia32_am_offs(res, offs);
1057 /* add the new offset */
1060 add_ia32_am_offs(res, offs_cnst);
1063 add_ia32_am_offs(res, offs_lea);
1067 /* either lea_O-cnst, -cnst or -lea_O */
1070 add_ia32_am_offs(res, offs_lea);
1073 sub_ia32_am_offs(res, offs_cnst);
1076 sub_ia32_am_offs(res, offs_lea);
1080 /* set the address mode symconst */
1082 set_ia32_am_sc(res, am_sc);
1084 set_ia32_am_sc_sign(res);
1087 /* copy the frame entity (could be set in case of Add */
1088 /* which was a FrameAddr) */
1090 set_ia32_frame_ent(res, lea_ent);
1092 set_ia32_frame_ent(res, get_ia32_frame_ent(irn));
1094 if (get_ia32_frame_ent(res))
1095 set_ia32_use_frame(res);
1098 set_ia32_am_scale(res, scale);
1100 am_flav = ia32_am_N;
1101 /* determine new am flavour */
1102 if (offs || offs_cnst || offs_lea) {
1105 if (! be_is_NoReg(cg, base)) {
1108 if (! be_is_NoReg(cg, index)) {
1114 set_ia32_am_flavour(res, am_flav);
1116 set_ia32_op_type(res, ia32_AddrModeS);
1118 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
1120 DBG((mod, LEVEL_1, "\tLEA [%+F + %+F * %d + %s]\n", base, index, scale, get_ia32_am_offs(res)));
1122 /* we will exchange it, report here before the Proj is created */
1123 if (shift && lea && lea_o)
1124 DBG_OPT_LEA4(irn, lea_o, lea, shift, res);
1125 else if (shift && lea)
1126 DBG_OPT_LEA3(irn, lea, shift, res);
1127 else if (shift && lea_o)
1128 DBG_OPT_LEA3(irn, lea_o, shift, res);
1129 else if (lea && lea_o)
1130 DBG_OPT_LEA3(irn, lea_o, lea, res);
1132 DBG_OPT_LEA2(irn, shift, res);
1134 DBG_OPT_LEA2(irn, lea, res);
1136 DBG_OPT_LEA2(irn, lea_o, res);
1138 DBG_OPT_LEA1(irn, res);
1140 /* get the result Proj of the Add/Sub */
1141 irn = get_res_proj(irn);
1143 assert(irn && "Couldn't find result proj");
1145 /* exchange the old op with the new LEA */
1154 * Merges a Load/Store node with a LEA.
1155 * @param irn The Load/Store node
1156 * @param lea The LEA
1158 static void merge_loadstore_lea(ir_node *irn, ir_node *lea) {
1159 entity *irn_ent = get_ia32_frame_ent(irn);
1160 entity *lea_ent = get_ia32_frame_ent(lea);
1162 /* If the irn and the LEA both have a different frame entity set: do not merge */
1163 if (irn_ent && lea_ent && (irn_ent != lea_ent))
1165 else if (! irn_ent && lea_ent) {
1166 set_ia32_frame_ent(irn, lea_ent);
1167 set_ia32_use_frame(irn);
1170 /* get the AM attributes from the LEA */
1171 add_ia32_am_offs(irn, get_ia32_am_offs(lea));
1172 set_ia32_am_scale(irn, get_ia32_am_scale(lea));
1173 set_ia32_am_flavour(irn, get_ia32_am_flavour(lea));
1175 set_ia32_am_sc(irn, get_ia32_am_sc(lea));
1176 if (is_ia32_am_sc_sign(lea))
1177 set_ia32_am_sc_sign(irn);
1179 set_ia32_op_type(irn, is_ia32_Ld(irn) ? ia32_AddrModeS : ia32_AddrModeD);
1181 /* set base and index */
1182 set_irn_n(irn, 0, get_irn_n(lea, 0));
1183 set_irn_n(irn, 1, get_irn_n(lea, 1));
1185 /* clear remat flag */
1186 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1188 if (is_ia32_Ld(irn))
1189 DBG_OPT_LOAD_LEA(lea, irn);
1191 DBG_OPT_STORE_LEA(lea, irn);
1196 * Sets new_right index of irn to right and new_left index to left.
1197 * Also exchange left and right
1199 static void exchange_left_right(ir_node *irn, ir_node **left, ir_node **right, int new_left, int new_right) {
1202 set_irn_n(irn, new_right, *right);
1203 set_irn_n(irn, new_left, *left);
1209 /* this is only needed for Compares, but currently ALL nodes
1210 * have this attribute :-) */
1211 set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
1215 * Performs address calculation optimization (create LEAs if possible)
1216 * @return 1 if performed optimization, 0 otherwise
1218 static int optimize_address_calculation(ir_node *irn, void *env) {
1219 ia32_code_gen_t *cg = env;
1221 ir_node *block, *noreg_gp, *left, *right;
1223 if (! is_ia32_irn(irn))
1226 /* Following cases can occur: */
1227 /* - Sub (l, imm) -> LEA [base - offset] */
1228 /* - Sub (l, r == LEA with ia32_am_O) -> LEA [base - offset] */
1229 /* - Add (l, imm) -> LEA [base + offset] */
1230 /* - Add (l, r == LEA with ia32_am_O) -> LEA [base + offset] */
1231 /* - Add (l == LEA with ia32_am_O, r) -> LEA [base + offset] */
1232 /* - Add (l, r) -> LEA [base + index * scale] */
1233 /* with scale > 1 iff l/r == shl (1,2,3) */
1235 if (is_ia32_Sub(irn) || is_ia32_Add(irn)) {
1236 left = get_irn_n(irn, 2);
1237 right = get_irn_n(irn, 3);
1238 block = get_nodes_block(irn);
1239 noreg_gp = ia32_new_NoReg_gp(cg);
1241 /* Do not try to create a LEA if one of the operands is a Load. */
1242 /* check is irn is a candidate for address calculation */
1243 if (is_candidate(block, irn, 1)) {
1246 DBG((cg->mod, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn));
1247 res = fold_addr(cg, irn, noreg_gp);
1251 DB((cg->mod, LEVEL_1, "transformed into %+F\n", res));
1253 DB((cg->mod, LEVEL_1, "not transformed\n"));
1256 else if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn)) {
1257 /* - Load -> LEA into Load } TODO: If the LEA is used by more than one Load/Store */
1258 /* - Store -> LEA into Store } it might be better to keep the LEA */
1259 left = get_irn_n(irn, 0);
1261 if (is_ia32_Lea(left)) {
1262 const ir_edge_t *edge, *ne;
1265 /* merge all Loads/Stores connected to this LEA with the LEA */
1266 foreach_out_edge_safe(left, edge, ne) {
1267 src = get_edge_src_irn(edge);
1269 if (src && (is_ia32_Ld(src) || is_ia32_St(src) || is_ia32_Store8Bit(src))) {
1270 DBG((cg->mod, LEVEL_1, "\nmerging %+F into %+F\n", left, irn));
1271 merge_loadstore_lea(src, left);
1283 * Checks for address mode patterns and performs the
1284 * necessary transformations.
1285 * This function is called by a walker.
1287 static void optimize_am(ir_node *irn, void *env) {
1288 ia32_code_gen_t *cg = env;
1292 ir_node *block, *noreg_gp, *noreg_fp;
1293 ir_node *left, *right, *temp;
1294 ir_node *store, *load, *mem_proj;
1295 ir_node *succ, *addr_b, *addr_i;
1296 int check_am_src = 0;
1297 int need_exchange_on_fail = 0;
1298 DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
1300 if (! is_ia32_irn(irn))
1303 dbg = get_irn_dbg_info(irn);
1304 mode = get_irn_mode(irn);
1305 block = get_nodes_block(irn);
1306 noreg_gp = ia32_new_NoReg_gp(cg);
1307 noreg_fp = ia32_new_NoReg_fp(cg);
1309 DBG((mod, LEVEL_1, "checking for AM\n"));
1311 /* fold following patterns: */
1312 /* - op -> Load into AMop with am_Source */
1314 /* - op is am_Source capable AND */
1315 /* - the Load is only used by this op AND */
1316 /* - the Load is in the same block */
1317 /* - Store -> op -> Load into AMop with am_Dest */
1319 /* - op is am_Dest capable AND */
1320 /* - the Store uses the same address as the Load AND */
1321 /* - the Load is only used by this op AND */
1322 /* - the Load and Store are in the same block AND */
1323 /* - nobody else uses the result of the op */
1325 if ((get_ia32_am_support(irn) != ia32_am_None) && ! is_ia32_Lea(irn) && is_candidate(block, irn, 0)) {
1326 DBG((mod, LEVEL_1, "\tfound address mode candidate %+F ... ", irn));
1328 left = get_irn_n(irn, 2);
1329 if (get_irn_arity(irn) == 4) {
1330 /* it's an "unary" operation */
1334 right = get_irn_n(irn, 3);
1337 /* normalize commutative ops */
1338 if (node_is_ia32_comm(irn)) {
1339 /* Assure that right operand is always a Load if there is one */
1340 /* because non-commutative ops can only use Dest AM if the right */
1341 /* operand is a load, so we only need to check right operand. */
1342 if (pred_is_specific_nodeblock(block, left, is_ia32_Ld))
1344 exchange_left_right(irn, &left, &right, 3, 2);
1345 need_exchange_on_fail = 1;
1349 /* check for Store -> op -> Load */
1351 /* Store -> op -> Load optimization is only possible if supported by op */
1352 /* and if right operand is a Load */
1353 if ((get_ia32_am_support(irn) & ia32_am_Dest) &&
1354 pred_is_specific_nodeblock(block, right, is_ia32_Ld))
1357 /* An address mode capable op always has a result Proj. */
1358 /* If this Proj is used by more than one other node, we don't need to */
1359 /* check further, otherwise we check for Store and remember the address, */
1360 /* the Store points to. */
1362 succ = get_res_proj(irn);
1363 assert(succ && "Couldn't find result proj");
1369 /* now check for users and Store */
1370 if (ia32_get_irn_n_edges(succ) == 1) {
1371 succ = get_edge_src_irn(get_irn_out_edge_first(succ));
1373 if (is_ia32_xStore(succ) || is_ia32_Store(succ)) {
1375 addr_b = get_irn_n(store, 0);
1376 addr_i = get_irn_n(store, 1);
1381 /* we found a Store as single user: Now check for Load */
1383 /* Extra check for commutative ops with two Loads */
1384 /* -> put the interesting Load right */
1385 if (node_is_ia32_comm(irn) &&
1386 pred_is_specific_nodeblock(block, left, is_ia32_Ld))
1388 if ((addr_b == get_irn_n(get_Proj_pred(left), 0)) &&
1389 (addr_i == get_irn_n(get_Proj_pred(left), 1)))
1391 /* We exchange left and right, so it's easier to kill */
1392 /* the correct Load later and to handle unary operations. */
1393 set_irn_n(irn, 2, right);
1394 set_irn_n(irn, 3, left);
1400 /* this is only needed for Compares, but currently ALL nodes
1401 * have this attribute :-) */
1402 set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
1406 /* skip the Proj for easier access */
1407 load = get_Proj_pred(right);
1409 /* Compare Load and Store address */
1410 if (load_store_addr_is_equal(load, store, addr_b, addr_i)) {
1411 /* Right Load is from same address, so we can */
1412 /* disconnect the Load and Store here */
1414 /* set new base, index and attributes */
1415 set_irn_n(irn, 0, addr_b);
1416 set_irn_n(irn, 1, addr_i);
1417 add_ia32_am_offs(irn, get_ia32_am_offs(load));
1418 set_ia32_am_scale(irn, get_ia32_am_scale(load));
1419 set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
1420 set_ia32_op_type(irn, ia32_AddrModeD);
1421 set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
1422 set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
1424 set_ia32_am_sc(irn, get_ia32_am_sc(load));
1425 if (is_ia32_am_sc_sign(load))
1426 set_ia32_am_sc_sign(irn);
1428 if (is_ia32_use_frame(load))
1429 set_ia32_use_frame(irn);
1431 /* connect to Load memory and disconnect Load */
1432 if (get_irn_arity(irn) == 5) {
1434 set_irn_n(irn, 4, get_irn_n(load, 2));
1435 set_irn_n(irn, 3, noreg_gp);
1439 set_irn_n(irn, 3, get_irn_n(load, 2));
1440 set_irn_n(irn, 2, noreg_gp);
1443 /* connect the memory Proj of the Store to the op */
1444 mem_proj = get_mem_proj(store);
1445 set_Proj_pred(mem_proj, irn);
1446 set_Proj_proj(mem_proj, 1);
1448 /* clear remat flag */
1449 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1451 DBG_OPT_AM_D(load, store, irn);
1453 DB((mod, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
1456 else if (get_ia32_am_support(irn) & ia32_am_Source) {
1457 /* There was no store, check if we still can optimize for source address mode */
1460 } /* if (support AM Dest) */
1461 else if (get_ia32_am_support(irn) & ia32_am_Source) {
1462 /* op doesn't support am AM Dest -> check for AM Source */
1466 /* was exchanged but optimize failed: exchange back */
1467 if (check_am_src && need_exchange_on_fail)
1468 exchange_left_right(irn, &left, &right, 3, 2);
1470 need_exchange_on_fail = 0;
1472 /* normalize commutative ops */
1473 if (check_am_src && node_is_ia32_comm(irn)) {
1474 /* Assure that left operand is always a Load if there is one */
1475 /* because non-commutative ops can only use Source AM if the */
1476 /* left operand is a Load, so we only need to check the left */
1477 /* operand afterwards. */
1478 if (pred_is_specific_nodeblock(block, right, is_ia32_Ld)) {
1479 exchange_left_right(irn, &left, &right, 3, 2);
1480 need_exchange_on_fail = 1;
1484 /* optimize op -> Load iff Load is only used by this op */
1485 /* and left operand is a Load which only used by this irn */
1487 pred_is_specific_nodeblock(block, left, is_ia32_Ld) &&
1488 (ia32_get_irn_n_edges(left) == 1))
1490 left = get_Proj_pred(left);
1492 addr_b = get_irn_n(left, 0);
1493 addr_i = get_irn_n(left, 1);
1495 /* set new base, index and attributes */
1496 set_irn_n(irn, 0, addr_b);
1497 set_irn_n(irn, 1, addr_i);
1498 add_ia32_am_offs(irn, get_ia32_am_offs(left));
1499 set_ia32_am_scale(irn, get_ia32_am_scale(left));
1500 set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
1501 set_ia32_op_type(irn, ia32_AddrModeS);
1502 set_ia32_frame_ent(irn, get_ia32_frame_ent(left));
1503 set_ia32_ls_mode(irn, get_ia32_ls_mode(left));
1505 set_ia32_am_sc(irn, get_ia32_am_sc(left));
1506 if (is_ia32_am_sc_sign(left))
1507 set_ia32_am_sc_sign(irn);
1509 /* clear remat flag */
1510 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1512 if (is_ia32_use_frame(left))
1513 set_ia32_use_frame(irn);
1515 /* connect to Load memory */
1516 if (get_irn_arity(irn) == 5) {
1518 set_irn_n(irn, 4, get_irn_n(left, 2));
1520 /* this is only needed for Compares, but currently ALL nodes
1521 * have this attribute :-) */
1522 set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
1524 /* disconnect from Load */
1525 /* (make second op -> first, set second in to noreg) */
1526 set_irn_n(irn, 2, get_irn_n(irn, 3));
1527 set_irn_n(irn, 3, noreg_gp);
1531 set_irn_n(irn, 3, get_irn_n(left, 2));
1533 /* disconnect from Load */
1534 set_irn_n(irn, 2, noreg_gp);
1537 DBG_OPT_AM_S(left, irn);
1539 /* If Load has a memory Proj, connect it to the op */
1540 mem_proj = get_mem_proj(left);
1542 set_Proj_pred(mem_proj, irn);
1543 set_Proj_proj(mem_proj, 1);
1546 DB((mod, LEVEL_1, "merged with %+F into source AM\n", left));
1549 /* was exchanged but optimize failed: exchange back */
1550 if (need_exchange_on_fail)
1551 exchange_left_right(irn, &left, &right, 3, 2);
1557 * This function is called by a walker and performs LEA optimization only.
1558 * It's a wrapper for optimize_address_calculation because this one returns
1559 * the transformed irn (or NULL) which gives a type mismatch for walker
1562 static void optimize_lea(ir_node *irn, void *env) {
1563 (void)optimize_address_calculation(irn, env);
1567 * This function first performs LEA optimization and if this failed
1568 * it performs address mode optimization.
1570 static void optimize_all(ir_node *irn, void *env) {
1571 if (! optimize_address_calculation(irn, env)) {
1572 /* irn was not transformed into LEA: check for am */
1573 optimize_am(irn, env);
1578 * Performs address mode optimization.
1580 void ia32_optimize_addressmode(ia32_code_gen_t *cg) {
1581 /* if we are supposed to do AM or LEA optimization: recalculate edges */
1582 if (cg->opt & (IA32_OPT_DOAM | IA32_OPT_LEA)) {
1583 edges_deactivate(cg->irg);
1584 edges_activate(cg->irg);
1587 /* no optimizations at all */
1591 if ((cg->opt & IA32_OPT_DOAM) && (cg->opt & IA32_OPT_LEA)) {
1592 /* optimize AM and LEA */
1593 irg_walk_blkwise_graph(cg->irg, NULL, optimize_all, cg);
1595 else if (cg->opt & IA32_OPT_DOAM) {
1596 /* optimize AM only */
1597 irg_walk_blkwise_graph(cg->irg, NULL, optimize_am, cg);
1600 /* optimize LEA only */
1601 irg_walk_blkwise_graph(cg->irg, NULL, optimize_lea, cg);