2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Matthias Braun, Christian Wuerdig
34 #include "firm_types.h"
46 #include "../benode_t.h"
47 #include "../besched_t.h"
48 #include "../bepeephole.h"
50 #include "ia32_new_nodes.h"
51 #include "ia32_optimize.h"
52 #include "bearch_ia32_t.h"
53 #include "gen_ia32_regalloc_if.h"
54 #include "ia32_transform.h"
55 #include "ia32_dbg_stat.h"
56 #include "ia32_util.h"
57 #include "ia32_architecture.h"
59 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
61 static const arch_env_t *arch_env;
62 static ia32_code_gen_t *cg;
65 * Returns non-zero if the given node produces
68 * @param node the node to check
69 * @param pn if >= 0, the projection number of the used result
71 static int produces_zero_flag(ir_node *node, int pn)
74 const ia32_immediate_attr_t *imm_attr;
76 if (!is_ia32_irn(node))
80 if (pn != pn_ia32_res)
84 switch (get_ia32_irn_opcode(node)) {
102 assert(n_ia32_ShlD_count == n_ia32_ShrD_count);
103 assert(n_ia32_Shl_count == n_ia32_Shr_count
104 && n_ia32_Shl_count == n_ia32_Sar_count);
105 if (is_ia32_ShlD(node) || is_ia32_ShrD(node)) {
106 count = get_irn_n(node, n_ia32_ShlD_count);
108 count = get_irn_n(node, n_ia32_Shl_count);
110 /* when shift count is zero the flags are not affected, so we can only
111 * do this for constants != 0 */
112 if (!is_ia32_Immediate(count))
115 imm_attr = get_ia32_immediate_attr_const(count);
116 if (imm_attr->symconst != NULL)
118 if ((imm_attr->offset & 0x1f) == 0)
129 * If the given node has not mode_T, creates a mode_T version (with a result Proj).
131 * @param node the node to change
133 * @return the new mode_T node (if the mode was changed) or node itself
135 static ir_node *turn_into_mode_t(ir_node *node)
140 const arch_register_t *reg;
142 if(get_irn_mode(node) == mode_T)
145 assert(get_irn_mode(node) == mode_Iu);
147 new_node = exact_copy(node);
148 set_irn_mode(new_node, mode_T);
150 block = get_nodes_block(new_node);
151 res_proj = new_r_Proj(current_ir_graph, block, new_node, mode_Iu,
154 reg = arch_get_irn_register(arch_env, node);
155 arch_set_irn_register(arch_env, res_proj, reg);
157 be_peephole_before_exchange(node, res_proj);
158 sched_add_before(node, new_node);
160 exchange(node, res_proj);
161 be_peephole_after_exchange(res_proj);
167 * Peephole optimization for Test instructions.
168 * We can remove the Test, if a zero flags was produced which is still
171 static void peephole_ia32_Test(ir_node *node)
173 ir_node *left = get_irn_n(node, n_ia32_Test_left);
174 ir_node *right = get_irn_n(node, n_ia32_Test_right);
180 const ir_edge_t *edge;
182 assert(n_ia32_Test_left == n_ia32_Test8Bit_left
183 && n_ia32_Test_right == n_ia32_Test8Bit_right);
185 /* we need a test for 0 */
189 block = get_nodes_block(node);
190 if(get_nodes_block(left) != block)
194 pn = get_Proj_proj(left);
195 left = get_Proj_pred(left);
198 /* happens rarely, but if it does code will panic' */
199 if (is_ia32_Unknown_GP(left))
202 /* walk schedule up and abort when we find left or some other node destroys
204 schedpoint = sched_prev(node);
205 while(schedpoint != left) {
206 schedpoint = sched_prev(schedpoint);
207 if(arch_irn_is(arch_env, schedpoint, modify_flags))
209 if(schedpoint == block)
210 panic("couldn't find left");
213 /* make sure only Lg/Eq tests are used */
214 foreach_out_edge(node, edge) {
215 ir_node *user = get_edge_src_irn(edge);
216 int pnc = get_ia32_condcode(user);
218 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) {
223 if(!produces_zero_flag(left, pn))
226 left = turn_into_mode_t(left);
228 flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
229 flags_proj = new_r_Proj(current_ir_graph, block, left, flags_mode,
231 arch_set_irn_register(arch_env, flags_proj, &ia32_flags_regs[REG_EFLAGS]);
233 assert(get_irn_mode(node) != mode_T);
235 be_peephole_before_exchange(node, flags_proj);
236 exchange(node, flags_proj);
238 be_peephole_after_exchange(flags_proj);
242 * AMD Athlon works faster when RET is not destination of
243 * conditional jump or directly preceded by other jump instruction.
244 * Can be avoided by placing a Rep prefix before the return.
246 static void peephole_ia32_Return(ir_node *node) {
247 ir_node *block, *irn;
249 if (!ia32_cg_config.use_pad_return)
252 block = get_nodes_block(node);
254 /* check if this return is the first on the block */
255 sched_foreach_reverse_from(node, irn) {
256 switch (get_irn_opcode(irn)) {
258 /* the return node itself, ignore */
261 /* ignore the barrier, no code generated */
264 /* arg, IncSP 0 nodes might occur, ignore these */
265 if (be_get_IncSP_offset(irn) == 0)
275 /* ensure, that the 3 byte return is generated
276 * actually the emitter tests again if the block beginning has a label and
277 * isn't just a fallthrough */
278 be_Return_set_emit_pop(node, 1);
281 /* only optimize up to 48 stores behind IncSPs */
282 #define MAXPUSH_OPTIMIZE 48
285 * Tries to create Push's from IncSP, Store combinations.
286 * The Stores are replaced by Push's, the IncSP is modified
287 * (possibly into IncSP 0, but not removed).
289 static void peephole_IncSP_Store_to_push(ir_node *irn)
291 int i, maxslot, inc_ofs;
293 ir_node *stores[MAXPUSH_OPTIMIZE];
299 memset(stores, 0, sizeof(stores));
301 assert(be_is_IncSP(irn));
303 inc_ofs = be_get_IncSP_offset(irn);
308 * We first walk the schedule after the IncSP node as long as we find
309 * suitable Stores that could be transformed to a Push.
310 * We save them into the stores array which is sorted by the frame offset/4
311 * attached to the node
314 for (node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
319 /* it has to be a Store */
320 if (!is_ia32_Store(node))
323 /* it has to use our sp value */
324 if (get_irn_n(node, n_ia32_base) != irn)
326 /* Store has to be attached to NoMem */
327 mem = get_irn_n(node, n_ia32_mem);
331 /* unfortunately we can't support the full AMs possible for push at the
332 * moment. TODO: fix this */
333 if (get_ia32_am_scale(node) > 0 || !is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
336 offset = get_ia32_am_offs_int(node);
337 /* we should NEVER access uninitialized stack BELOW the current SP */
340 offset = inc_ofs - 4 - offset;
342 /* storing at half-slots is bad */
343 if ((offset & 3) != 0)
346 if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
348 storeslot = offset >> 2;
350 /* storing into the same slot twice is bad (and shouldn't happen...) */
351 if (stores[storeslot] != NULL)
354 stores[storeslot] = node;
355 if (storeslot > maxslot)
359 curr_sp = be_get_IncSP_pred(irn);
361 /* walk through the Stores and create Pushs for them */
362 block = get_nodes_block(irn);
363 spmode = get_irn_mode(irn);
365 for (i = 0; i <= maxslot; ++i) {
366 const arch_register_t *spreg;
368 ir_node *val, *mem, *mem_proj;
369 ir_node *store = stores[i];
370 ir_node *noreg = ia32_new_NoReg_gp(cg);
375 val = get_irn_n(store, n_ia32_unary_op);
376 mem = get_irn_n(store, n_ia32_mem);
377 spreg = arch_get_irn_register(cg->arch_env, curr_sp);
379 push = new_rd_ia32_Push(get_irn_dbg_info(store), irg, block, noreg, noreg, mem, val, curr_sp);
381 sched_add_before(irn, push);
383 /* create stackpointer Proj */
384 curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack);
385 arch_set_irn_register(cg->arch_env, curr_sp, spreg);
387 /* create memory Proj */
388 mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
390 /* use the memproj now */
391 exchange(store, mem_proj);
393 /* we can remove the Store now */
399 be_set_IncSP_offset(irn, inc_ofs);
400 be_set_IncSP_pred(irn, curr_sp);
404 * Return true if a mode can be stored in the GP register set
406 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
407 if (mode == mode_fpcw)
409 if (get_mode_size_bits(mode) > 32)
411 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
415 * Tries to create Pops from Load, IncSP combinations.
416 * The Loads are replaced by Pops, the IncSP is modified
417 * (possibly into IncSP 0, but not removed).
419 static void peephole_Load_IncSP_to_pop(ir_node *irn)
421 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
422 int i, maxslot, inc_ofs, ofs;
423 ir_node *node, *pred_sp, *block;
424 ir_node *loads[MAXPUSH_OPTIMIZE];
426 unsigned regmask = 0;
427 unsigned copymask = ~0;
429 memset(loads, 0, sizeof(loads));
430 assert(be_is_IncSP(irn));
432 inc_ofs = -be_get_IncSP_offset(irn);
437 * We first walk the schedule before the IncSP node as long as we find
438 * suitable Loads that could be transformed to a Pop.
439 * We save them into the stores array which is sorted by the frame offset/4
440 * attached to the node
443 pred_sp = be_get_IncSP_pred(irn);
444 for (node = sched_prev(irn); !sched_is_end(node); node = sched_prev(node)) {
448 const arch_register_t *sreg, *dreg;
450 /* it has to be a Load */
451 if (!is_ia32_Load(node)) {
452 if (be_is_Copy(node)) {
453 if (!mode_needs_gp_reg(get_irn_mode(node))) {
454 /* not a GP copy, ignore */
457 dreg = arch_get_irn_register(arch_env, node);
458 sreg = arch_get_irn_register(arch_env, be_get_Copy_op(node));
459 if (regmask & copymask & (1 << sreg->index)) {
462 if (regmask & copymask & (1 << dreg->index)) {
465 /* we CAN skip Copies if neither the destination nor the source
466 * is not in our regmask, ie none of our future Pop will overwrite it */
467 regmask |= (1 << dreg->index) | (1 << sreg->index);
468 copymask &= ~((1 << dreg->index) | (1 << sreg->index));
474 /* we can handle only GP loads */
475 if (!mode_needs_gp_reg(get_ia32_ls_mode(node)))
478 /* it has to use our predecessor sp value */
479 if (get_irn_n(node, n_ia32_base) != pred_sp) {
480 /* it would be ok if this load does not use a Pop result,
481 * but we do not check this */
484 /* Load has to be attached to Spill-Mem */
485 mem = skip_Proj(get_irn_n(node, n_ia32_mem));
486 if (!is_Phi(mem) && !is_ia32_Store(mem) && !is_ia32_Push(mem))
489 /* should have NO index */
490 if (get_ia32_am_scale(node) > 0 || !is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
493 offset = get_ia32_am_offs_int(node);
494 /* we should NEVER access uninitialized stack BELOW the current SP */
497 /* storing at half-slots is bad */
498 if ((offset & 3) != 0)
501 if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
503 /* ignore those outside the possible windows */
504 if (offset > inc_ofs - 4)
506 loadslot = offset >> 2;
508 /* loading from the same slot twice is bad (and shouldn't happen...) */
509 if (loads[loadslot] != NULL)
512 dreg = arch_get_irn_register(arch_env, node);
513 if (regmask & (1 << dreg->index)) {
514 /* this register is already used */
517 regmask |= 1 << dreg->index;
519 loads[loadslot] = node;
520 if (loadslot > maxslot)
527 /* find the first slot */
528 for (i = maxslot; i >= 0; --i) {
529 ir_node *load = loads[i];
535 ofs = inc_ofs - (maxslot + 1) * 4;
538 /* create a new IncSP if needed */
539 block = get_nodes_block(irn);
542 pred_sp = be_new_IncSP(esp, irg, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
543 sched_add_before(irn, pred_sp);
546 /* walk through the Loads and create Pops for them */
547 for (++i; i <= maxslot; ++i) {
548 ir_node *load = loads[i];
550 const ir_edge_t *edge, *tmp;
551 const arch_register_t *reg;
553 mem = get_irn_n(load, n_ia32_mem);
554 reg = arch_get_irn_register(arch_env, load);
556 pop = new_rd_ia32_Pop(get_irn_dbg_info(load), irg, block, mem, pred_sp);
557 arch_set_irn_register(arch_env, pop, reg);
559 /* create stackpointer Proj */
560 pred_sp = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
561 arch_set_irn_register(arch_env, pred_sp, esp);
563 sched_add_before(irn, pop);
566 foreach_out_edge_safe(load, edge, tmp) {
567 ir_node *proj = get_edge_src_irn(edge);
569 set_Proj_pred(proj, pop);
573 /* we can remove the Load now */
577 be_set_IncSP_offset(irn, -ofs);
578 be_set_IncSP_pred(irn, pred_sp);
584 * Find a free GP register if possible, else return NULL.
586 static const arch_register_t *get_free_gp_reg(void)
590 for(i = 0; i < N_ia32_gp_REGS; ++i) {
591 const arch_register_t *reg = &ia32_gp_regs[i];
592 if(arch_register_type_is(reg, ignore))
595 if(be_peephole_get_value(CLASS_ia32_gp, i) == NULL)
596 return &ia32_gp_regs[i];
603 * Creates a Pop instruction before the given schedule point.
605 * @param dbgi debug info
606 * @param irg the graph
607 * @param block the block
608 * @param stack the previous stack value
609 * @param schedpoint the new node is added before this node
610 * @param reg the register to pop
612 * @return the new stack value
614 static ir_node *create_pop(dbg_info *dbgi, ir_graph *irg, ir_node *block,
615 ir_node *stack, ir_node *schedpoint,
616 const arch_register_t *reg)
618 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
624 pop = new_rd_ia32_Pop(dbgi, irg, block, new_NoMem(), stack);
626 stack = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
627 arch_set_irn_register(arch_env, stack, esp);
628 val = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_res);
629 arch_set_irn_register(arch_env, val, reg);
631 sched_add_before(schedpoint, pop);
634 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
635 sched_add_before(schedpoint, keep);
641 * Creates a Push instruction before the given schedule point.
643 * @param dbgi debug info
644 * @param irg the graph
645 * @param block the block
646 * @param stack the previous stack value
647 * @param schedpoint the new node is added before this node
648 * @param reg the register to pop
650 * @return the new stack value
652 static ir_node *create_push(dbg_info *dbgi, ir_graph *irg, ir_node *block,
653 ir_node *stack, ir_node *schedpoint,
654 const arch_register_t *reg)
656 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
657 ir_node *noreg, *nomem, *push, *val;
659 val = new_rd_ia32_ProduceVal(NULL, irg, block);
660 arch_set_irn_register(arch_env, val, reg);
661 sched_add_before(schedpoint, val);
663 noreg = ia32_new_NoReg_gp(cg);
664 nomem = get_irg_no_mem(irg);
665 push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, nomem, val, stack);
666 sched_add_before(schedpoint, push);
668 stack = new_r_Proj(irg, block, push, mode_Iu, pn_ia32_Push_stack);
669 arch_set_irn_register(arch_env, stack, esp);
675 * Optimize an IncSp by replacing it with Push/Pop.
677 static void peephole_be_IncSP(ir_node *node)
679 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
680 const arch_register_t *reg;
681 ir_graph *irg = current_ir_graph;
687 /* first optimize incsp->incsp combinations */
688 node = be_peephole_IncSP_IncSP(node);
690 /* transform IncSP->Store combinations to Push where possible */
691 peephole_IncSP_Store_to_push(node);
693 /* transform Load->IncSP combinations to Pop where possible */
694 peephole_Load_IncSP_to_pop(node);
696 if (arch_get_irn_register(arch_env, node) != esp)
699 /* replace IncSP -4 by Pop freereg when possible */
700 offset = be_get_IncSP_offset(node);
701 if ((offset != -8 || ia32_cg_config.use_add_esp_8) &&
702 (offset != -4 || ia32_cg_config.use_add_esp_4) &&
703 (offset != +4 || ia32_cg_config.use_sub_esp_4) &&
704 (offset != +8 || ia32_cg_config.use_sub_esp_8))
708 /* we need a free register for pop */
709 reg = get_free_gp_reg();
713 dbgi = get_irn_dbg_info(node);
714 block = get_nodes_block(node);
715 stack = be_get_IncSP_pred(node);
717 stack = create_pop(dbgi, irg, block, stack, node, reg);
720 stack = create_pop(dbgi, irg, block, stack, node, reg);
723 dbgi = get_irn_dbg_info(node);
724 block = get_nodes_block(node);
725 stack = be_get_IncSP_pred(node);
726 reg = &ia32_gp_regs[REG_EAX];
728 stack = create_push(dbgi, irg, block, stack, node, reg);
731 stack = create_push(dbgi, irg, block, stack, node, reg);
735 be_peephole_before_exchange(node, stack);
737 exchange(node, stack);
738 be_peephole_after_exchange(stack);
742 * Peephole optimisation for ia32_Const's
744 static void peephole_ia32_Const(ir_node *node)
746 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
747 const arch_register_t *reg;
748 ir_graph *irg = current_ir_graph;
755 /* try to transform a mov 0, reg to xor reg reg */
756 if (attr->offset != 0 || attr->symconst != NULL)
758 if (ia32_cg_config.use_mov_0)
760 /* xor destroys the flags, so no-one must be using them */
761 if (be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
764 reg = arch_get_irn_register(arch_env, node);
765 assert(be_peephole_get_reg_value(reg) == NULL);
767 /* create xor(produceval, produceval) */
768 block = get_nodes_block(node);
769 dbgi = get_irn_dbg_info(node);
770 produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
771 arch_set_irn_register(arch_env, produceval, reg);
773 noreg = ia32_new_NoReg_gp(cg);
774 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_NoMem(),
775 produceval, produceval);
776 arch_set_irn_register(arch_env, xor, reg);
778 sched_add_before(node, produceval);
779 sched_add_before(node, xor);
781 be_peephole_before_exchange(node, xor);
784 be_peephole_after_exchange(xor);
787 static INLINE int is_noreg(ia32_code_gen_t *cg, const ir_node *node)
789 return node == cg->noreg_gp;
792 static ir_node *create_immediate_from_int(ia32_code_gen_t *cg, int val)
794 ir_graph *irg = current_ir_graph;
795 ir_node *start_block = get_irg_start_block(irg);
796 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL,
798 arch_set_irn_register(cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
803 static ir_node *create_immediate_from_am(ia32_code_gen_t *cg,
806 ir_graph *irg = get_irn_irg(node);
807 ir_node *block = get_nodes_block(node);
808 int offset = get_ia32_am_offs_int(node);
809 int sc_sign = is_ia32_am_sc_sign(node);
810 ir_entity *entity = get_ia32_am_sc(node);
813 res = new_rd_ia32_Immediate(NULL, irg, block, entity, sc_sign, offset);
814 arch_set_irn_register(cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
818 static int is_am_one(const ir_node *node)
820 int offset = get_ia32_am_offs_int(node);
821 ir_entity *entity = get_ia32_am_sc(node);
823 return offset == 1 && entity == NULL;
826 static int is_am_minus_one(const ir_node *node)
828 int offset = get_ia32_am_offs_int(node);
829 ir_entity *entity = get_ia32_am_sc(node);
831 return offset == -1 && entity == NULL;
835 * Transforms a LEA into an Add or SHL if possible.
837 static void peephole_ia32_Lea(ir_node *node)
839 const arch_env_t *arch_env = cg->arch_env;
840 ir_graph *irg = current_ir_graph;
843 const arch_register_t *base_reg;
844 const arch_register_t *index_reg;
845 const arch_register_t *out_reg;
856 assert(is_ia32_Lea(node));
858 /* we can only do this if are allowed to globber the flags */
859 if(be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
862 base = get_irn_n(node, n_ia32_Lea_base);
863 index = get_irn_n(node, n_ia32_Lea_index);
865 if(is_noreg(cg, base)) {
869 base_reg = arch_get_irn_register(arch_env, base);
871 if(is_noreg(cg, index)) {
875 index_reg = arch_get_irn_register(arch_env, index);
878 if(base == NULL && index == NULL) {
879 /* we shouldn't construct these in the first place... */
881 ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
886 out_reg = arch_get_irn_register(arch_env, node);
887 scale = get_ia32_am_scale(node);
888 assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
889 /* check if we have immediates values (frame entities should already be
890 * expressed in the offsets) */
891 if(get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
897 /* we can transform leas where the out register is the same as either the
898 * base or index register back to an Add or Shl */
899 if(out_reg == base_reg) {
902 if(!has_immediates) {
903 ir_fprintf(stderr, "Optimisation warning: found lea which is "
908 goto make_add_immediate;
910 if(scale == 0 && !has_immediates) {
915 /* can't create an add */
917 } else if(out_reg == index_reg) {
919 if(has_immediates && scale == 0) {
921 goto make_add_immediate;
922 } else if(!has_immediates && scale > 0) {
924 op2 = create_immediate_from_int(cg, scale);
926 } else if(!has_immediates) {
928 ir_fprintf(stderr, "Optimisation warning: found lea which is "
932 } else if(scale == 0 && !has_immediates) {
937 /* can't create an add */
940 /* can't create an add */
945 if(ia32_cg_config.use_incdec) {
946 if(is_am_one(node)) {
947 dbgi = get_irn_dbg_info(node);
948 block = get_nodes_block(node);
949 res = new_rd_ia32_Inc(dbgi, irg, block, op1);
950 arch_set_irn_register(arch_env, res, out_reg);
953 if(is_am_minus_one(node)) {
954 dbgi = get_irn_dbg_info(node);
955 block = get_nodes_block(node);
956 res = new_rd_ia32_Dec(dbgi, irg, block, op1);
957 arch_set_irn_register(arch_env, res, out_reg);
961 op2 = create_immediate_from_am(cg, node);
964 dbgi = get_irn_dbg_info(node);
965 block = get_nodes_block(node);
966 noreg = ia32_new_NoReg_gp(cg);
968 res = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, nomem, op1, op2);
969 arch_set_irn_register(arch_env, res, out_reg);
970 set_ia32_commutative(res);
974 dbgi = get_irn_dbg_info(node);
975 block = get_nodes_block(node);
976 noreg = ia32_new_NoReg_gp(cg);
978 res = new_rd_ia32_Shl(dbgi, irg, block, op1, op2);
979 arch_set_irn_register(arch_env, res, out_reg);
983 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, node));
985 /* add new ADD/SHL to schedule */
986 DBG_OPT_LEA2ADD(node, res);
988 /* exchange the Add and the LEA */
989 be_peephole_before_exchange(node, res);
990 sched_add_before(node, res);
993 be_peephole_after_exchange(res);
997 * Split a Imul mem, imm into a Load mem and Imul reg, imm if possible.
999 static void peephole_ia32_Imul_split(ir_node *imul) {
1000 const ir_node *right = get_irn_n(imul, n_ia32_IMul_right);
1001 const arch_register_t *reg;
1002 ir_node *load, *block, *base, *index, *mem, *res, *noreg;
1006 if (! is_ia32_Immediate(right) || get_ia32_op_type(imul) != ia32_AddrModeS) {
1007 /* no memory, imm form ignore */
1010 /* we need a free register */
1011 reg = get_free_gp_reg();
1015 /* fine, we can rebuild it */
1016 dbgi = get_irn_dbg_info(imul);
1017 block = get_nodes_block(imul);
1018 irg = current_ir_graph;
1019 base = get_irn_n(imul, n_ia32_IMul_base);
1020 index = get_irn_n(imul, n_ia32_IMul_index);
1021 mem = get_irn_n(imul, n_ia32_IMul_mem);
1022 load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
1024 /* copy all attributes */
1025 set_irn_pinned(load, get_irn_pinned(imul));
1026 set_ia32_op_type(load, ia32_AddrModeS);
1027 set_ia32_ls_mode(load, get_ia32_ls_mode(imul));
1029 set_ia32_am_scale(load, get_ia32_am_scale(imul));
1030 set_ia32_am_sc(load, get_ia32_am_sc(imul));
1031 set_ia32_am_offs_int(load, get_ia32_am_offs_int(imul));
1032 if (is_ia32_am_sc_sign(imul))
1033 set_ia32_am_sc_sign(load);
1034 if (is_ia32_use_frame(imul))
1035 set_ia32_use_frame(load);
1036 set_ia32_frame_ent(load, get_ia32_frame_ent(imul));
1038 sched_add_before(imul, load);
1040 mem = new_rd_Proj(dbgi, irg, block, load, mode_M, pn_ia32_Load_M);
1041 res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
1043 arch_set_irn_register(arch_env, res, reg);
1044 be_peephole_after_exchange(res);
1046 set_irn_n(imul, n_ia32_IMul_mem, mem);
1047 noreg = get_irn_n(imul, n_ia32_IMul_left);
1048 set_irn_n(imul, n_ia32_IMul_left, res);
1049 set_ia32_op_type(imul, ia32_Normal);
1053 * Replace xorps r,r and xorpd r,r by pxor r,r
1055 static void peephole_ia32_xZero(ir_node *xor) {
1056 set_irn_op(xor, op_ia32_xPzero);
1060 * Register a peephole optimisation function.
1062 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func) {
1063 assert(op->ops.generic == NULL);
1064 op->ops.generic = (op_func)func;
1067 /* Perform peephole-optimizations. */
1068 void ia32_peephole_optimization(ia32_code_gen_t *new_cg)
1071 arch_env = cg->arch_env;
1073 /* register peephole optimisations */
1074 clear_irp_opcodes_generic_func();
1075 register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
1076 register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
1077 register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
1078 register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
1079 register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test);
1080 register_peephole_optimisation(op_be_Return, peephole_ia32_Return);
1081 if (! ia32_cg_config.use_imul_mem_imm32)
1082 register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split);
1083 if (ia32_cg_config.use_pxor)
1084 register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero);
1086 be_peephole_opt(cg->birg);
1090 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
1091 * all it's Projs are removed as well.
1092 * @param irn The irn to be removed from schedule
1094 static INLINE void try_kill(ir_node *node)
1096 if(get_irn_mode(node) == mode_T) {
1097 const ir_edge_t *edge, *next;
1098 foreach_out_edge_safe(node, edge, next) {
1099 ir_node *proj = get_edge_src_irn(edge);
1104 if(get_irn_n_edges(node) != 0)
1107 if (sched_is_scheduled(node)) {
1114 static void optimize_conv_store(ir_node *node)
1119 ir_mode *store_mode;
1121 if(!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
1124 assert(n_ia32_Store_val == n_ia32_Store8Bit_val);
1125 pred_proj = get_irn_n(node, n_ia32_Store_val);
1126 if(is_Proj(pred_proj)) {
1127 pred = get_Proj_pred(pred_proj);
1131 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1133 if(get_ia32_op_type(pred) != ia32_Normal)
1136 /* the store only stores the lower bits, so we only need the conv
1137 * it it shrinks the mode */
1138 conv_mode = get_ia32_ls_mode(pred);
1139 store_mode = get_ia32_ls_mode(node);
1140 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
1143 set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val));
1144 if(get_irn_n_edges(pred_proj) == 0) {
1145 be_kill_node(pred_proj);
1146 if(pred != pred_proj)
1151 static void optimize_load_conv(ir_node *node)
1153 ir_node *pred, *predpred;
1157 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1160 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1161 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
1165 predpred = get_Proj_pred(pred);
1166 if(!is_ia32_Load(predpred))
1169 /* the load is sign extending the upper bits, so we only need the conv
1170 * if it shrinks the mode */
1171 load_mode = get_ia32_ls_mode(predpred);
1172 conv_mode = get_ia32_ls_mode(node);
1173 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
1176 if(get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
1177 /* change the load if it has only 1 user */
1178 if(get_irn_n_edges(pred) == 1) {
1180 if(get_mode_sign(conv_mode)) {
1181 newmode = find_signed_mode(load_mode);
1183 newmode = find_unsigned_mode(load_mode);
1185 assert(newmode != NULL);
1186 set_ia32_ls_mode(predpred, newmode);
1188 /* otherwise we have to keep the conv */
1194 exchange(node, pred);
1197 static void optimize_conv_conv(ir_node *node)
1199 ir_node *pred_proj, *pred, *result_conv;
1200 ir_mode *pred_mode, *conv_mode;
1204 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1207 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1208 pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
1209 if(is_Proj(pred_proj))
1210 pred = get_Proj_pred(pred_proj);
1214 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1217 /* we know that after a conv, the upper bits are sign extended
1218 * so we only need the 2nd conv if it shrinks the mode */
1219 conv_mode = get_ia32_ls_mode(node);
1220 conv_mode_bits = get_mode_size_bits(conv_mode);
1221 pred_mode = get_ia32_ls_mode(pred);
1222 pred_mode_bits = get_mode_size_bits(pred_mode);
1224 if(conv_mode_bits == pred_mode_bits
1225 && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1226 result_conv = pred_proj;
1227 } else if(conv_mode_bits <= pred_mode_bits) {
1228 /* if 2nd conv is smaller then first conv, then we can always take the
1230 if(get_irn_n_edges(pred_proj) == 1) {
1231 result_conv = pred_proj;
1232 set_ia32_ls_mode(pred, conv_mode);
1234 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1235 if (get_mode_size_bits(conv_mode) == 8) {
1236 set_irn_op(pred, op_ia32_Conv_I2I8Bit);
1237 set_ia32_in_req_all(pred, get_ia32_in_req_all(node));
1240 /* we don't want to end up with 2 loads, so we better do nothing */
1241 if(get_irn_mode(pred) == mode_T) {
1245 result_conv = exact_copy(pred);
1246 set_ia32_ls_mode(result_conv, conv_mode);
1248 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1249 if (get_mode_size_bits(conv_mode) == 8) {
1250 set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
1251 set_ia32_in_req_all(result_conv, get_ia32_in_req_all(node));
1255 /* if both convs have the same sign, then we can take the smaller one */
1256 if(get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1257 result_conv = pred_proj;
1259 /* no optimisation possible if smaller conv is sign-extend */
1260 if(mode_is_signed(pred_mode)) {
1263 /* we can take the smaller conv if it is unsigned */
1264 result_conv = pred_proj;
1269 exchange(node, result_conv);
1271 if(get_irn_n_edges(pred_proj) == 0) {
1272 be_kill_node(pred_proj);
1273 if(pred != pred_proj)
1276 optimize_conv_conv(result_conv);
1279 static void optimize_node(ir_node *node, void *env)
1283 optimize_load_conv(node);
1284 optimize_conv_store(node);
1285 optimize_conv_conv(node);
1289 * Performs conv and address mode optimization.
1291 void ia32_optimize_graph(ia32_code_gen_t *cg)
1293 irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg);
1296 be_dump(cg->irg, "-opt", dump_ir_block_graph_sched);
1299 void ia32_init_optimize(void)
1301 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");