8 #include "firm_types.h"
16 #include "ia32_new_nodes.h"
17 #include "bearch_ia32_t.h"
18 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
21 #define is_NoMem(irn) (get_irn_op(irn) == op_NoMem)
23 static int be_is_NoReg(be_abi_irg_t *babi, const ir_node *irn) {
24 if (be_abi_get_callee_save_irn(babi, &ia32_gp_regs[REG_XXX]) == irn ||
25 be_abi_get_callee_save_irn(babi, &ia32_fp_regs[REG_XXXX]) == irn)
34 * creates a unique ident by adding a number to a tag
36 * @param tag the tag string, must contain a %d if a number
39 static ident *unique_id(const char *tag)
41 static unsigned id = 0;
44 snprintf(str, sizeof(str), tag, ++id);
45 return new_id_from_str(str);
51 * Transforms a SymConst.
53 * @param mod the debug module
54 * @param block the block the new node should belong to
55 * @param node the ir SymConst node
56 * @param mode mode of the SymConst
57 * @return the created ia32 Const node
59 static ir_node *gen_SymConst(ia32_transform_env_t *env) {
61 dbg_info *dbg = env->dbg;
62 ir_mode *mode = env->mode;
63 ir_graph *irg = env->irg;
64 ir_node *block = env->block;
66 cnst = new_rd_ia32_Const(dbg, irg, block, mode);
67 set_ia32_Const_attr(cnst, env->irn);
72 * Get a primitive type for a mode.
74 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
76 pmap_entry *e = pmap_find(types, mode);
81 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
82 res = new_type_primitive(new_id_from_str(buf), mode);
83 pmap_insert(types, mode, res);
91 * Get an entity that is initialized with a tarval
93 static entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
95 tarval *tv = get_Const_tarval(cnst);
96 pmap_entry *e = pmap_find(cg->tv_ent, tv);
101 ir_mode *mode = get_irn_mode(cnst);
102 ir_type *tp = get_Const_type(cnst);
103 if (tp == firm_unknown_type)
104 tp = get_prim_type(cg->types, mode);
106 res = new_entity(get_glob_type(), unique_id("ia32FloatCnst_%u"), tp);
108 set_entity_ld_ident(res, get_entity_ident(res));
109 set_entity_visibility(res, visibility_local);
110 set_entity_variability(res, variability_constant);
111 set_entity_allocation(res, allocation_static);
113 /* we create a new entity here: It's initialization must resist on the
115 rem = current_ir_graph;
116 current_ir_graph = get_const_code_irg();
117 set_atomic_ent_value(res, new_Const_type(tv, tp));
118 current_ir_graph = rem;
126 * Transforms a Const.
128 * @param mod the debug module
129 * @param block the block the new node should belong to
130 * @param node the ir Const node
131 * @param mode mode of the Const
132 * @return the created ia32 Const node
134 static ir_node *gen_Const(ia32_transform_env_t *env) {
137 ir_graph *irg = env->irg;
138 ir_node *block = env->block;
139 ir_node *node = env->irn;
140 dbg_info *dbg = env->dbg;
141 ir_mode *mode = env->mode;
143 if (mode_is_float(mode)) {
144 sym.entity_p = get_entity_for_tv(env->cg, node);
146 cnst = new_rd_SymConst(dbg, irg, block, sym, symconst_addr_ent);
148 cnst = gen_SymConst(env);
151 cnst = new_rd_ia32_Const(dbg, irg, block, get_irn_mode(node));
152 set_ia32_Const_attr(cnst, node);
160 * Transforms (all) Const's into ia32_Const and places them in the
161 * block where they are used (or in the cfg-pred Block in case of Phi's).
162 * Additionally all mode_P nodes are changed into mode_Is nodes.
164 void ia32_place_consts_set_modes(ir_node *irn, void *env) {
165 ia32_code_gen_t *cg = env;
166 ia32_transform_env_t tenv;
168 ir_node *pred, *cnst;
175 mode = get_irn_mode(irn);
177 /* transform all mode_P nodes into mode_Is nodes */
178 if (mode == mode_P) {
179 set_irn_mode(irn, mode_Is);
183 tenv.block = get_nodes_block(irn);
188 /* Loop over all predecessors and check for Sym/Const nodes */
189 for (i = get_irn_arity(irn) - 1; i >= 0; --i) {
190 pred = get_irn_n(irn, i);
192 opc = get_irn_opcode(pred);
194 tenv.mode = get_irn_mode(pred);
195 tenv.dbg = get_irn_dbg_info(pred);
197 /* If it's a Phi, then we need to create the */
198 /* new Const in it's predecessor block */
200 tenv.block = get_Block_cfgpred_block(get_nodes_block(irn), i);
203 /* put the const into the block where the original const was */
204 if (! cg->opt.placecnst) {
205 tenv.block = get_nodes_block(pred);
210 cnst = gen_Const(&tenv);
213 cnst = gen_SymConst(&tenv);
219 /* if we found a const, then set it */
221 set_irn_n(irn, i, cnst);
227 /******************************************************************
229 * /\ | | | | | \/ | | |
230 * / \ __| | __| |_ __ ___ ___ ___| \ / | ___ __| | ___
231 * / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \
232 * / ____ \ (_| | (_| | | | __/\__ \__ \ | | | (_) | (_| | __/
233 * /_/ \_\__,_|\__,_|_| \___||___/___/_| |_|\___/ \__,_|\___|
235 ******************************************************************/
237 static int node_is_comm(const ir_node *irn) {
238 return is_ia32_irn(irn) ? is_ia32_commutative(irn) : 0;
241 static int ia32_get_irn_n_edges(const ir_node *irn) {
242 const ir_edge_t *edge;
245 foreach_out_edge(irn, edge) {
253 * Returns the first mode_M Proj connected to irn.
255 static ir_node *get_mem_proj(const ir_node *irn) {
256 const ir_edge_t *edge;
259 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
261 foreach_out_edge(irn, edge) {
262 src = get_edge_src_irn(edge);
264 assert(is_Proj(src) && "Proj expected");
266 if (get_irn_mode(src) == mode_M)
274 * Returns the Proj with number 0 connected to irn.
276 static ir_node *get_res_proj(const ir_node *irn) {
277 const ir_edge_t *edge;
280 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
282 foreach_out_edge(irn, edge) {
283 src = get_edge_src_irn(edge);
285 assert(is_Proj(src) && "Proj expected");
287 if (get_Proj_proj(src) == 0)
295 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor.
297 * @param pred The node to be checked
298 * @param is_op_func The check-function
299 * @return 1 if conditions are fulfilled, 0 otherwise
301 static int pred_is_specific_node(const ir_node *pred, int (*is_op_func)(const ir_node *n)) {
302 if (is_Proj(pred) && is_op_func(get_Proj_pred(pred))) {
310 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor
311 * and if the predecessor is in block bl.
313 * @param bl The block
314 * @param pred The node to be checked
315 * @param is_op_func The check-function
316 * @return 1 if conditions are fulfilled, 0 otherwise
318 static int pred_is_specific_nodeblock(const ir_node *bl, const ir_node *pred,
319 int (*is_op_func)(const ir_node *n))
322 pred = get_Proj_pred(pred);
323 if ((bl == get_nodes_block(pred)) && is_op_func(pred)) {
332 * Checks if irn is a candidate for address calculation or address mode.
334 * address calculation (AC):
335 * - none of the operand must be a Load within the same block OR
336 * - all Loads must have more than one user OR
337 * - the irn has a frame entity (it's a former FrameAddr)
340 * - at least one operand has to be a Load within the same block AND
341 * - the load must not have other users than the irn AND
342 * - the irn must not have a frame entity set
344 * @param block The block the Loads must/not be in
345 * @param irn The irn to check
346 * @param check_addr 1 if to check for address calculation, 0 otherwise
347 * return 1 if irn is a candidate for AC or AM, 0 otherwise
349 static int is_candidate(const ir_node *block, const ir_node *irn, int check_addr) {
351 int n, is_cand = check_addr;
353 if (pred_is_specific_nodeblock(block, get_irn_n(irn, 2), is_ia32_Load)) {
354 load_proj = get_irn_n(irn, 2);
355 n = ia32_get_irn_n_edges(load_proj);
356 is_cand = check_addr ? (n == 1 ? 0 : is_cand) : (n == 1 ? 1 : is_cand);
359 if (pred_is_specific_nodeblock(block, get_irn_n(irn, 3), is_ia32_Load)) {
360 load_proj = get_irn_n(irn, 3);
361 n = ia32_get_irn_n_edges(load_proj);
362 is_cand = check_addr ? (n == 1 ? 0 : is_cand) : (n == 1 ? 1 : is_cand);
365 is_cand = get_ia32_frame_ent(irn) ? (check_addr ? 1 : 0) : (check_addr ? 0 : 1);
371 * Compares the base and index addr and the load/store entities
372 * and returns 1 if they are equal.
374 static int load_store_addr_is_equal(const ir_node *load, const ir_node *store,
375 const ir_node *addr_b, const ir_node *addr_i)
377 int is_equal = (addr_b == get_irn_n(load, 0)) && (addr_i == get_irn_n(load, 1));
378 entity *lent = get_ia32_frame_ent(load);
379 entity *sent = get_ia32_frame_ent(store);
381 /* are both entities set and equal? */
382 is_equal = (lent && sent && (lent == sent)) ? 1 : is_equal;
388 * Folds Add or Sub to LEA if possible
390 static ir_node *fold_addr(be_abi_irg_t *babi, ir_node *irn, firm_dbg_module_t *mod, ir_node *noreg) {
391 ir_graph *irg = get_irn_irg(irn);
392 dbg_info *dbg = get_irn_dbg_info(irn);
393 ir_node *block = get_nodes_block(irn);
396 char *offs_cnst = NULL;
397 char *offs_lea = NULL;
401 ir_node *left, *right, *temp;
402 ir_node *base, *index;
403 ia32_am_flavour_t am_flav;
405 if (is_ia32_Add(irn))
408 left = get_irn_n(irn, 2);
409 right = get_irn_n(irn, 3);
417 /* "normalize" arguments in case of add with two operands */
418 if (isadd && ! be_is_NoReg(babi, right)) {
419 /* put LEA == ia32_am_O as right operand */
420 if (is_ia32_Lea(left) && get_ia32_am_flavour(left) == ia32_am_O) {
421 set_irn_n(irn, 2, right);
422 set_irn_n(irn, 3, left);
428 /* put LEA != ia32_am_O as left operand */
429 if (is_ia32_Lea(right) && get_ia32_am_flavour(right) != ia32_am_O) {
430 set_irn_n(irn, 2, right);
431 set_irn_n(irn, 3, left);
437 /* put SHL as left operand iff left is NOT a LEA */
438 if (! is_ia32_Lea(left) && pred_is_specific_node(right, is_ia32_Shl)) {
439 set_irn_n(irn, 2, right);
440 set_irn_n(irn, 3, left);
447 /* check if operand is either const */
448 if (get_ia32_cnst(irn)) {
449 DBG((mod, LEVEL_1, "\tfound op with imm"));
451 offs_cnst = get_ia32_cnst(irn);
455 /* determine the operand which needs to be checked */
456 if (be_is_NoReg(babi, right)) {
463 /* check if right operand is AMConst (LEA with ia32_am_O) */
464 if (is_ia32_Lea(temp) && get_ia32_am_flavour(temp) == ia32_am_O) {
465 DBG((mod, LEVEL_1, "\tgot op with LEA am_O"));
467 offs_lea = get_ia32_am_offs(temp);
472 /* default for add -> make right operand to index */
476 DBG((mod, LEVEL_1, "\tgot LEA candidate with index %+F\n", index));
478 /* determine the operand which needs to be checked */
480 if (is_ia32_Lea(left)) {
484 /* check for SHL 1,2,3 */
485 if (pred_is_specific_node(temp, is_ia32_Shl)) {
486 temp = get_Proj_pred(temp);
488 if (get_ia32_Immop_tarval(temp)) {
489 scale = get_tarval_long(get_ia32_Immop_tarval(temp));
492 index = get_irn_n(temp, 2);
494 DBG((mod, LEVEL_1, "\tgot scaled index %+F\n", index));
500 if (! be_is_NoReg(babi, index)) {
501 /* if we have index, but left == right -> no base */
505 else if (! is_ia32_Lea(left) && (index != right)) {
506 /* index != right -> we found a good Shl */
507 /* left != LEA -> this Shl was the left operand */
508 /* -> base is right operand */
514 /* Try to assimilate a LEA as left operand */
515 if (is_ia32_Lea(left) && (get_ia32_am_flavour(left) != ia32_am_O)) {
516 am_flav = get_ia32_am_flavour(left);
518 /* If we have an Add with a real right operand (not NoReg) and */
519 /* the LEA contains already an index calculation then we create */
521 /* If the LEA contains already a frame_entity then we also */
522 /* create a new one otherwise we would loose it. */
523 if (isadd && ((!be_is_NoReg(babi, index) && (am_flav & ia32_am_I)) || get_ia32_frame_ent(left))) {
524 DBG((mod, LEVEL_1, "\tleave old LEA, creating new one\n"));
527 DBG((mod, LEVEL_1, "\tgot LEA as left operand ... assimilating\n"));
528 offs = get_ia32_am_offs(left);
529 base = get_irn_n(left, 0);
530 index = get_irn_n(left, 1);
531 scale = get_ia32_am_scale(left);
535 /* ok, we can create a new LEA */
537 res = new_rd_ia32_Lea(dbg, irg, block, base, index, mode_Is);
539 /* add the old offset of a previous LEA */
541 add_ia32_am_offs(res, offs);
544 /* add the new offset */
547 add_ia32_am_offs(res, offs_cnst);
550 add_ia32_am_offs(res, offs_lea);
554 /* either lea_O-cnst, -cnst or -lea_O */
557 add_ia32_am_offs(res, offs_lea);
560 sub_ia32_am_offs(res, offs_cnst);
563 sub_ia32_am_offs(res, offs_lea);
567 /* copy the frame entity (could be set in case of Add */
568 /* which was a FrameAddr) */
569 set_ia32_frame_ent(res, get_ia32_frame_ent(irn));
571 if (is_ia32_use_frame(irn))
572 set_ia32_use_frame(res);
575 set_ia32_am_scale(res, scale);
578 /* determine new am flavour */
579 if (offs || offs_cnst || offs_lea) {
582 if (! be_is_NoReg(babi, base)) {
585 if (! be_is_NoReg(babi, index)) {
591 set_ia32_am_flavour(res, am_flav);
593 set_ia32_op_type(res, ia32_AddrModeS);
595 DBG((mod, LEVEL_1, "\tLEA [%+F + %+F * %d + %s]\n", base, index, scale, get_ia32_am_offs(res)));
597 /* get the result Proj of the Add/Sub */
598 irn = get_res_proj(irn);
600 assert(irn && "Couldn't find result proj");
602 /* exchange the old op with the new LEA */
610 * Optimizes a pattern around irn to address mode if possible.
612 void ia32_optimize_am(ir_node *irn, void *env) {
613 ia32_code_gen_t *cg = env;
614 firm_dbg_module_t *mod = cg->mod;
616 be_abi_irg_t *babi = cg->birg->abi;
619 ir_node *block, *noreg_gp, *noreg_fp;
620 ir_node *left, *right, *temp;
621 ir_node *store, *load, *mem_proj;
622 ir_node *succ, *addr_b, *addr_i;
623 int check_am_src = 0;
625 if (! is_ia32_irn(irn))
628 dbg = get_irn_dbg_info(irn);
629 mode = get_irn_mode(irn);
630 block = get_nodes_block(irn);
631 noreg_gp = ia32_new_NoReg_gp(cg);
632 noreg_fp = ia32_new_NoReg_fp(cg);
634 DBG((mod, LEVEL_1, "checking for AM\n"));
636 /* 1st part: check for address calculations and transform the into Lea */
638 /* Following cases can occur: */
639 /* - Sub (l, imm) -> LEA [base - offset] */
640 /* - Sub (l, r == LEA with ia32_am_O) -> LEA [base - offset] */
641 /* - Add (l, imm) -> LEA [base + offset] */
642 /* - Add (l, r == LEA with ia32_am_O) -> LEA [base + offset] */
643 /* - Add (l == LEA with ia32_am_O, r) -> LEA [base + offset] */
644 /* - Add (l, r) -> LEA [base + index * scale] */
645 /* with scale > 1 iff l/r == shl (1,2,3) */
647 if (is_ia32_Sub(irn) || is_ia32_Add(irn)) {
648 left = get_irn_n(irn, 2);
649 right = get_irn_n(irn, 3);
651 /* Do not try to create a LEA if one of the operands is a Load. */
652 /* check is irn is a candidate for address calculation */
653 if (is_candidate(block, irn, 1)) {
654 DBG((mod, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn));
655 res = fold_addr(babi, irn, mod, noreg_gp);
658 DB((mod, LEVEL_1, "transformed into %+F\n", res));
660 DB((mod, LEVEL_1, "not transformed\n"));
664 /* 2nd part: fold following patterns: */
665 /* - Load -> LEA into Load } TODO: If the LEA is used by more than one Load/Store */
666 /* - Store -> LEA into Store } it might be better to keep the LEA */
667 /* - op -> Load into AMop with am_Source */
669 /* - op is am_Source capable AND */
670 /* - the Load is only used by this op AND */
671 /* - the Load is in the same block */
672 /* - Store -> op -> Load into AMop with am_Dest */
674 /* - op is am_Dest capable AND */
675 /* - the Store uses the same address as the Load AND */
676 /* - the Load is only used by this op AND */
677 /* - the Load and Store are in the same block AND */
678 /* - nobody else uses the result of the op */
680 if ((res == irn) && (get_ia32_am_support(irn) != ia32_am_None) && !is_ia32_Lea(irn)) {
681 /* 1st: check for Load/Store -> LEA */
682 if (is_ia32_Ld(irn) || is_ia32_St(irn)) {
683 left = get_irn_n(irn, 0);
685 if (is_ia32_Lea(left)) {
686 DBG((mod, LEVEL_1, "\nmerging %+F into %+F\n", left, irn));
688 /* get the AM attributes from the LEA */
689 add_ia32_am_offs(irn, get_ia32_am_offs(left));
690 set_ia32_am_scale(irn, get_ia32_am_scale(left));
691 set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
693 set_ia32_op_type(irn, is_ia32_St(irn) ? ia32_AddrModeD : ia32_AddrModeS);
695 /* set base and index */
696 set_irn_n(irn, 0, get_irn_n(left, 0));
697 set_irn_n(irn, 1, get_irn_n(left, 1));
700 /* check if the node is an address mode candidate */
701 else if (is_candidate(block, irn, 0)) {
702 DBG((mod, LEVEL_1, "\tfound address mode candidate %+F ... ", irn));
704 left = get_irn_n(irn, 2);
705 if (get_irn_arity(irn) == 4) {
706 /* it's an "unary" operation */
710 right = get_irn_n(irn, 3);
713 /* normalize commutative ops */
714 if (node_is_comm(irn)) {
715 /* Assure that right operand is always a Load if there is one */
716 /* because non-commutative ops can only use Dest AM if the right */
717 /* operand is a load, so we only need to check right operand. */
718 if (pred_is_specific_nodeblock(block, left, is_ia32_Ld))
720 set_irn_n(irn, 2, right);
721 set_irn_n(irn, 3, left);
729 /* check for Store -> op -> Load */
731 /* Store -> op -> Load optimization is only possible if supported by op */
732 /* and if right operand is a Load */
733 if ((get_ia32_am_support(irn) & ia32_am_Dest) &&
734 pred_is_specific_nodeblock(block, right, is_ia32_Ld))
737 /* An address mode capable op always has a result Proj. */
738 /* If this Proj is used by more than one other node, we don't need to */
739 /* check further, otherwise we check for Store and remember the address, */
740 /* the Store points to. */
742 succ = get_res_proj(irn);
743 assert(succ && "Couldn't find result proj");
749 /* now check for users and Store */
750 if (ia32_get_irn_n_edges(succ) == 1) {
751 succ = get_edge_src_irn(get_irn_out_edge_first(succ));
753 if (is_ia32_fStore(succ) || is_ia32_Store(succ)) {
755 addr_b = get_irn_n(store, 0);
757 /* Could be that the Store is connected to the address */
758 /* calculating LEA while the Load is already transformed. */
759 if (is_ia32_Lea(addr_b)) {
761 addr_b = get_irn_n(succ, 0);
762 addr_i = get_irn_n(succ, 1);
771 /* we found a Store as single user: Now check for Load */
773 /* Extra check for commutative ops with two Loads */
774 /* -> put the interesting Load right */
775 if (node_is_comm(irn) &&
776 pred_is_specific_nodeblock(block, left, is_ia32_Ld))
778 if ((addr_b == get_irn_n(get_Proj_pred(left), 0)) &&
779 (addr_i == get_irn_n(get_Proj_pred(left), 1)))
781 /* We exchange left and right, so it's easier to kill */
782 /* the correct Load later and to handle unary operations. */
783 set_irn_n(irn, 2, right);
784 set_irn_n(irn, 3, left);
792 /* skip the Proj for easier access */
793 load = get_Proj_pred(right);
795 /* Compare Load and Store address */
796 if (load_store_addr_is_equal(load, store, addr_b, addr_i)) {
797 /* Right Load is from same address, so we can */
798 /* disconnect the Load and Store here */
800 /* set new base, index and attributes */
801 set_irn_n(irn, 0, addr_b);
802 set_irn_n(irn, 1, addr_i);
803 add_ia32_am_offs(irn, get_ia32_am_offs(load));
804 set_ia32_am_scale(irn, get_ia32_am_scale(load));
805 set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
806 set_ia32_op_type(irn, ia32_AddrModeD);
807 set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
808 set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
810 if (is_ia32_use_frame(load))
811 set_ia32_use_frame(irn);
813 /* connect to Load memory and disconnect Load */
814 if (get_irn_arity(irn) == 5) {
816 set_irn_n(irn, 4, get_irn_n(load, 2));
817 set_irn_n(irn, 3, noreg_gp);
821 set_irn_n(irn, 3, get_irn_n(load, 2));
822 set_irn_n(irn, 2, noreg_gp);
825 /* connect the memory Proj of the Store to the op */
826 mem_proj = get_mem_proj(store);
827 set_Proj_pred(mem_proj, irn);
828 set_Proj_proj(mem_proj, 1);
830 DB((mod, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
833 else if (get_ia32_am_support(irn) & ia32_am_Source) {
834 /* There was no store, check if we still can optimize for source address mode */
837 } /* if (support AM Dest) */
838 else if (get_ia32_am_support(irn) & ia32_am_Source) {
839 /* op doesn't support am AM Dest -> check for AM Source */
843 /* normalize commutative ops */
844 if (node_is_comm(irn)) {
845 /* Assure that left operand is always a Load if there is one */
846 /* because non-commutative ops can only use Source AM if the */
847 /* left operand is a Load, so we only need to check the left */
848 /* operand afterwards. */
849 if (pred_is_specific_nodeblock(block, right, is_ia32_Ld)) {
850 set_irn_n(irn, 2, right);
851 set_irn_n(irn, 3, left);
859 /* optimize op -> Load iff Load is only used by this op */
860 /* and left operand is a Load which only used by this irn */
862 pred_is_specific_nodeblock(block, left, is_ia32_Ld) &&
863 (ia32_get_irn_n_edges(left) == 1))
865 left = get_Proj_pred(left);
867 addr_b = get_irn_n(left, 0);
868 addr_i = get_irn_n(left, 1);
870 /* set new base, index and attributes */
871 set_irn_n(irn, 0, addr_b);
872 set_irn_n(irn, 1, addr_i);
873 add_ia32_am_offs(irn, get_ia32_am_offs(left));
874 set_ia32_am_scale(irn, get_ia32_am_scale(left));
875 set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
876 set_ia32_op_type(irn, ia32_AddrModeS);
877 set_ia32_frame_ent(irn, get_ia32_frame_ent(left));
878 set_ia32_ls_mode(irn, get_ia32_ls_mode(left));
880 if (is_ia32_use_frame(left))
881 set_ia32_use_frame(irn);
883 /* connect to Load memory */
884 if (get_irn_arity(irn) == 5) {
886 set_irn_n(irn, 4, get_irn_n(left, 2));
890 set_irn_n(irn, 3, get_irn_n(left, 2));
893 /* disconnect from Load */
894 set_irn_n(irn, 2, noreg_gp);
896 /* If Load has a memory Proj, connect it to the op */
897 mem_proj = get_mem_proj(left);
899 set_Proj_pred(mem_proj, irn);
900 set_Proj_proj(mem_proj, 1);
903 DB((mod, LEVEL_1, "merged with %+F into source AM\n", left));