8 #include "firm_types.h"
16 #include "ia32_new_nodes.h"
17 #include "bearch_ia32_t.h"
18 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
21 #define is_NoMem(irn) (get_irn_op(irn) == op_NoMem)
23 static int be_is_NoReg(be_abi_irg_t *babi, const ir_node *irn) {
24 if (be_abi_get_callee_save_irn(babi, &ia32_gp_regs[REG_XXX]) == irn ||
25 be_abi_get_callee_save_irn(babi, &ia32_fp_regs[REG_XXXX]) == irn)
34 * creates a unique ident by adding a number to a tag
36 * @param tag the tag string, must contain a %d if a number
39 static ident *unique_id(const char *tag)
41 static unsigned id = 0;
44 snprintf(str, sizeof(str), tag, ++id);
45 return new_id_from_str(str);
51 * Transforms a SymConst.
53 * @param mod the debug module
54 * @param block the block the new node should belong to
55 * @param node the ir SymConst node
56 * @param mode mode of the SymConst
57 * @return the created ia32 Const node
59 static ir_node *gen_SymConst(ia32_transform_env_t *env) {
61 dbg_info *dbg = env->dbg;
62 ir_mode *mode = env->mode;
63 ir_graph *irg = env->irg;
64 ir_node *block = env->block;
66 cnst = new_rd_ia32_Const(dbg, irg, block, mode);
67 set_ia32_Const_attr(cnst, env->irn);
72 * Get a primitive type for a mode.
74 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
76 pmap_entry *e = pmap_find(types, mode);
81 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
82 res = new_type_primitive(new_id_from_str(buf), mode);
83 pmap_insert(types, mode, res);
91 * Get an entity that is initialized with a tarval
93 static entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
95 tarval *tv = get_Const_tarval(cnst);
96 pmap_entry *e = pmap_find(cg->tv_ent, tv);
101 ir_mode *mode = get_irn_mode(cnst);
102 ir_type *tp = get_Const_type(cnst);
103 if (tp == firm_unknown_type)
104 tp = get_prim_type(cg->types, mode);
106 res = new_entity(get_glob_type(), unique_id("ia32FloatCnst_%u"), tp);
108 set_entity_ld_ident(res, get_entity_ident(res));
109 set_entity_visibility(res, visibility_local);
110 set_entity_variability(res, variability_constant);
111 set_entity_allocation(res, allocation_static);
113 /* we create a new entity here: It's initialization must resist on the
115 rem = current_ir_graph;
116 current_ir_graph = get_const_code_irg();
117 set_atomic_ent_value(res, new_Const_type(tv, tp));
118 current_ir_graph = rem;
126 * Transforms a Const.
128 * @param mod the debug module
129 * @param block the block the new node should belong to
130 * @param node the ir Const node
131 * @param mode mode of the Const
132 * @return the created ia32 Const node
134 static ir_node *gen_Const(ia32_transform_env_t *env) {
137 ir_graph *irg = env->irg;
138 ir_node *block = env->block;
139 ir_node *node = env->irn;
140 dbg_info *dbg = env->dbg;
141 ir_mode *mode = env->mode;
143 if (mode_is_float(mode)) {
144 sym.entity_p = get_entity_for_tv(env->cg, node);
146 cnst = new_rd_SymConst(dbg, irg, block, sym, symconst_addr_ent);
148 cnst = gen_SymConst(env);
151 cnst = new_rd_ia32_Const(dbg, irg, block, get_irn_mode(node));
152 set_ia32_Const_attr(cnst, node);
160 * Transforms (all) Const's into ia32_Const and places them in the
161 * block where they are used (or in the cfg-pred Block in case of Phi's).
162 * Additionally all mode_P nodes are changed into mode_Is nodes.
164 void ia32_place_consts_set_modes(ir_node *irn, void *env) {
165 ia32_code_gen_t *cg = env;
166 ia32_transform_env_t tenv;
168 ir_node *pred, *cnst;
175 mode = get_irn_mode(irn);
177 /* transform all mode_P nodes into mode_Is nodes */
178 if (mode == mode_P) {
179 set_irn_mode(irn, mode_Is);
183 tenv.block = get_nodes_block(irn);
188 /* Loop over all predecessors and check for Sym/Const nodes */
189 for (i = get_irn_arity(irn) - 1; i >= 0; --i) {
190 pred = get_irn_n(irn, i);
192 opc = get_irn_opcode(pred);
194 tenv.mode = get_irn_mode(pred);
195 tenv.dbg = get_irn_dbg_info(pred);
197 /* If it's a Phi, then we need to create the */
198 /* new Const in it's predecessor block */
200 tenv.block = get_Block_cfgpred_block(get_nodes_block(irn), i);
203 /* put the const into the block where the original const was */
204 if (! cg->opt.placecnst) {
205 tenv.block = get_nodes_block(pred);
210 cnst = gen_Const(&tenv);
213 cnst = gen_SymConst(&tenv);
219 /* if we found a const, then set it */
221 set_irn_n(irn, i, cnst);
227 /******************************************************************
229 * /\ | | | | | \/ | | |
230 * / \ __| | __| |_ __ ___ ___ ___| \ / | ___ __| | ___
231 * / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \
232 * / ____ \ (_| | (_| | | | __/\__ \__ \ | | | (_) | (_| | __/
233 * /_/ \_\__,_|\__,_|_| \___||___/___/_| |_|\___/ \__,_|\___|
235 ******************************************************************/
237 static int node_is_comm(const ir_node *irn) {
238 return is_ia32_irn(irn) ? is_ia32_commutative(irn) : 0;
241 static int ia32_get_irn_n_edges(const ir_node *irn) {
242 const ir_edge_t *edge;
245 foreach_out_edge(irn, edge) {
253 * Returns the first mode_M Proj connected to irn.
255 static ir_node *get_mem_proj(const ir_node *irn) {
256 const ir_edge_t *edge;
259 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
261 foreach_out_edge(irn, edge) {
262 src = get_edge_src_irn(edge);
264 assert(is_Proj(src) && "Proj expected");
266 if (get_irn_mode(src) == mode_M)
274 * Returns the Proj with number 0 connected to irn.
276 static ir_node *get_res_proj(const ir_node *irn) {
277 const ir_edge_t *edge;
280 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
282 foreach_out_edge(irn, edge) {
283 src = get_edge_src_irn(edge);
285 assert(is_Proj(src) && "Proj expected");
287 if (get_Proj_proj(src) == 0)
295 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor.
297 * @param pred The node to be checked
298 * @param is_op_func The check-function
299 * @return 1 if conditions are fulfilled, 0 otherwise
301 static int pred_is_specific_node(const ir_node *pred, int (*is_op_func)(const ir_node *n)) {
302 if (is_Proj(pred) && is_op_func(get_Proj_pred(pred))) {
310 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor
311 * and if the predecessor is in block bl.
313 * @param bl The block
314 * @param pred The node to be checked
315 * @param is_op_func The check-function
316 * @return 1 if conditions are fulfilled, 0 otherwise
318 static int pred_is_specific_nodeblock(const ir_node *bl, const ir_node *pred,
319 int (*is_op_func)(const ir_node *n))
322 pred = get_Proj_pred(pred);
323 if ((bl == get_nodes_block(pred)) && is_op_func(pred)) {
331 static int is_addr_candidate(const ir_node *block, const ir_node *irn) {
336 * Checks if irn is a candidate for address calculation or address mode.
338 * address calculation (AC):
339 * - none of the operand must be a Load within the same block OR
340 * - all Loads must have more than one user OR
341 * - the irn has a frame entity (it's a former FrameAddr)
344 * - at least one operand has to be a Load within the same block AND
345 * - the load must not have other users than the irn AND
346 * - the irn must not have a frame entity set
348 * @param block The block the Loads must/not be in
349 * @param irn The irn to check
350 * @param check_addr 1 if to check for address calculation, 0 otherwise
351 * return 1 if irn is a candidate for AC or AM, 0 otherwise
353 static int is_candidate(const ir_node *block, const ir_node *irn, int check_addr) {
355 int n, is_cand = check_addr;
357 if (pred_is_specific_nodeblock(block, get_irn_n(irn, 2), is_ia32_Load)) {
358 load_proj = get_irn_n(irn, 2);
359 n = ia32_get_irn_n_edges(load_proj);
360 is_cand = check_addr ? (n == 1 ? 0 : is_cand) : (n == 1 ? 1 : is_cand);
363 if (pred_is_specific_nodeblock(block, get_irn_n(irn, 3), is_ia32_Load)) {
364 load_proj = get_irn_n(irn, 3);
365 n = ia32_get_irn_n_edges(load_proj);
366 is_cand = check_addr ? (n == 1 ? 0 : is_cand) : (n == 1 ? 1 : is_cand);
369 is_cand = get_ia32_frame_ent(irn) ? (check_addr ? 1 : 0) : (check_addr ? 0 : 1);
375 * Compares the base and index addr and the load/store entities
376 * and returns 1 if they are equal.
378 static int load_store_addr_is_equal(const ir_node *load, const ir_node *store,
379 const ir_node *addr_b, const ir_node *addr_i)
381 int is_equal = (addr_b == get_irn_n(load, 0)) && (addr_i == get_irn_n(load, 1));
382 entity *lent = get_ia32_frame_ent(load);
383 entity *sent = get_ia32_frame_ent(store);
385 /* are both entities set and equal? */
386 is_equal = (lent && sent && (lent == sent)) ? 1 : is_equal;
392 * Folds Add or Sub to LEA if possible
394 static ir_node *fold_addr(be_abi_irg_t *babi, ir_node *irn, firm_dbg_module_t *mod, ir_node *noreg) {
395 ir_graph *irg = get_irn_irg(irn);
396 dbg_info *dbg = get_irn_dbg_info(irn);
397 ir_node *block = get_nodes_block(irn);
400 char *offs_cnst = NULL;
401 char *offs_lea = NULL;
405 ir_node *left, *right, *temp;
406 ir_node *base, *index;
407 ia32_am_flavour_t am_flav;
409 if (is_ia32_Add(irn))
412 left = get_irn_n(irn, 2);
413 right = get_irn_n(irn, 3);
421 /* "normalize" arguments in case of add with two operands */
422 if (isadd && ! be_is_NoReg(babi, right)) {
423 /* put LEA == ia32_am_O as right operand */
424 if (is_ia32_Lea(left) && get_ia32_am_flavour(left) == ia32_am_O) {
425 set_irn_n(irn, 2, right);
426 set_irn_n(irn, 3, left);
432 /* put LEA != ia32_am_O as left operand */
433 if (is_ia32_Lea(right) && get_ia32_am_flavour(right) != ia32_am_O) {
434 set_irn_n(irn, 2, right);
435 set_irn_n(irn, 3, left);
441 /* put SHL as left operand iff left is NOT a LEA */
442 if (! is_ia32_Lea(left) && pred_is_specific_node(right, is_ia32_Shl)) {
443 set_irn_n(irn, 2, right);
444 set_irn_n(irn, 3, left);
451 /* check if operand is either const */
452 if (get_ia32_cnst(irn)) {
453 DBG((mod, LEVEL_1, "\tfound op with imm"));
455 offs_cnst = get_ia32_cnst(irn);
459 /* determine the operand which needs to be checked */
460 if (be_is_NoReg(babi, right)) {
467 /* check if right operand is AMConst (LEA with ia32_am_O) */
468 if (is_ia32_Lea(temp) && get_ia32_am_flavour(temp) == ia32_am_O) {
469 DBG((mod, LEVEL_1, "\tgot op with LEA am_O"));
471 offs_lea = get_ia32_am_offs(temp);
476 /* default for add -> make right operand to index */
480 DBG((mod, LEVEL_1, "\tgot LEA candidate with index %+F\n", index));
482 /* determine the operand which needs to be checked */
484 if (is_ia32_Lea(left)) {
488 /* check for SHL 1,2,3 */
489 if (pred_is_specific_node(temp, is_ia32_Shl)) {
490 temp = get_Proj_pred(temp);
492 if (get_ia32_Immop_tarval(temp)) {
493 scale = get_tarval_long(get_ia32_Immop_tarval(temp));
496 index = get_irn_n(temp, 2);
498 DBG((mod, LEVEL_1, "\tgot scaled index %+F\n", index));
504 if (! be_is_NoReg(babi, index)) {
505 /* if we have index, but left == right -> no base */
509 else if (! is_ia32_Lea(left) && (index != right)) {
510 /* index != right -> we found a good Shl */
511 /* left != LEA -> this Shl was the left operand */
512 /* -> base is right operand */
518 /* Try to assimilate a LEA as left operand */
519 if (is_ia32_Lea(left) && (get_ia32_am_flavour(left) != ia32_am_O)) {
520 am_flav = get_ia32_am_flavour(left);
522 /* If we have an Add with a real right operand (not NoReg) and */
523 /* the LEA contains already an index calculation then we create */
525 /* If the LEA contains already a frame_entity then we also */
526 /* create a new one otherwise we would loose it. */
527 if (isadd && ((!be_is_NoReg(babi, index) && (am_flav & ia32_am_I)) || get_ia32_frame_ent(left))) {
528 DBG((mod, LEVEL_1, "\tleave old LEA, creating new one\n"));
531 DBG((mod, LEVEL_1, "\tgot LEA as left operand ... assimilating\n"));
532 offs = get_ia32_am_offs(left);
533 base = get_irn_n(left, 0);
534 index = get_irn_n(left, 1);
535 scale = get_ia32_am_scale(left);
539 /* ok, we can create a new LEA */
541 res = new_rd_ia32_Lea(dbg, irg, block, base, index, mode_Is);
543 /* add the old offset of a previous LEA */
545 add_ia32_am_offs(res, offs);
548 /* add the new offset */
551 add_ia32_am_offs(res, offs_cnst);
554 add_ia32_am_offs(res, offs_lea);
558 /* either lea_O-cnst, -cnst or -lea_O */
561 add_ia32_am_offs(res, offs_lea);
564 sub_ia32_am_offs(res, offs_cnst);
567 sub_ia32_am_offs(res, offs_lea);
571 /* copy the frame entity (could be set in case of Add */
572 /* which was a FrameAddr) */
573 set_ia32_frame_ent(res, get_ia32_frame_ent(irn));
575 if (is_ia32_use_frame(irn))
576 set_ia32_use_frame(res);
579 set_ia32_am_scale(res, scale);
582 /* determine new am flavour */
583 if (offs || offs_cnst || offs_lea) {
586 if (! be_is_NoReg(babi, base)) {
589 if (! be_is_NoReg(babi, index)) {
595 set_ia32_am_flavour(res, am_flav);
597 set_ia32_op_type(res, ia32_AddrModeS);
599 DBG((mod, LEVEL_1, "\tLEA [%+F + %+F * %d + %s]\n", base, index, scale, get_ia32_am_offs(res)));
601 /* get the result Proj of the Add/Sub */
602 irn = get_res_proj(irn);
604 assert(irn && "Couldn't find result proj");
606 /* exchange the old op with the new LEA */
614 * Optimizes a pattern around irn to address mode if possible.
616 void ia32_optimize_am(ir_node *irn, void *env) {
617 ia32_code_gen_t *cg = env;
618 firm_dbg_module_t *mod = cg->mod;
620 be_abi_irg_t *babi = cg->birg->abi;
623 ir_node *block, *noreg_gp, *noreg_fp;
624 ir_node *left, *right, *temp;
625 ir_node *store, *load, *mem_proj;
626 ir_node *succ, *addr_b, *addr_i;
627 int check_am_src = 0;
629 if (! is_ia32_irn(irn))
632 dbg = get_irn_dbg_info(irn);
633 mode = get_irn_mode(irn);
634 block = get_nodes_block(irn);
635 noreg_gp = ia32_new_NoReg_gp(cg);
636 noreg_fp = ia32_new_NoReg_fp(cg);
638 DBG((mod, LEVEL_1, "checking for AM\n"));
640 /* 1st part: check for address calculations and transform the into Lea */
642 /* Following cases can occur: */
643 /* - Sub (l, imm) -> LEA [base - offset] */
644 /* - Sub (l, r == LEA with ia32_am_O) -> LEA [base - offset] */
645 /* - Add (l, imm) -> LEA [base + offset] */
646 /* - Add (l, r == LEA with ia32_am_O) -> LEA [base + offset] */
647 /* - Add (l == LEA with ia32_am_O, r) -> LEA [base + offset] */
648 /* - Add (l, r) -> LEA [base + index * scale] */
649 /* with scale > 1 iff l/r == shl (1,2,3) */
651 if (is_ia32_Sub(irn) || is_ia32_Add(irn)) {
652 left = get_irn_n(irn, 2);
653 right = get_irn_n(irn, 3);
655 /* Do not try to create a LEA if one of the operands is a Load. */
656 /* check is irn is a candidate for address calculation */
657 if (is_candidate(block, irn, 1)) {
658 DBG((mod, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn));
659 res = fold_addr(babi, irn, mod, noreg_gp);
662 DB((mod, LEVEL_1, "transformed into %+F\n", res));
664 DB((mod, LEVEL_1, "not transformed\n"));
668 /* 2nd part: fold following patterns: */
669 /* - Load -> LEA into Load } TODO: If the LEA is used by more than one Load/Store */
670 /* - Store -> LEA into Store } it might be better to keep the LEA */
671 /* - op -> Load into AMop with am_Source */
673 /* - op is am_Source capable AND */
674 /* - the Load is only used by this op AND */
675 /* - the Load is in the same block */
676 /* - Store -> op -> Load into AMop with am_Dest */
678 /* - op is am_Dest capable AND */
679 /* - the Store uses the same address as the Load AND */
680 /* - the Load is only used by this op AND */
681 /* - the Load and Store are in the same block AND */
682 /* - nobody else uses the result of the op */
684 if ((res == irn) && (get_ia32_am_support(irn) != ia32_am_None) && !is_ia32_Lea(irn)) {
685 /* 1st: check for Load/Store -> LEA */
686 if (is_ia32_Ld(irn) || is_ia32_St(irn)) {
687 left = get_irn_n(irn, 0);
689 if (is_ia32_Lea(left)) {
690 DBG((mod, LEVEL_1, "\nmerging %+F into %+F\n", left, irn));
692 /* get the AM attributes from the LEA */
693 add_ia32_am_offs(irn, get_ia32_am_offs(left));
694 set_ia32_am_scale(irn, get_ia32_am_scale(left));
695 set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
697 set_ia32_op_type(irn, is_ia32_St(irn) ? ia32_AddrModeD : ia32_AddrModeS);
699 /* set base and index */
700 set_irn_n(irn, 0, get_irn_n(left, 0));
701 set_irn_n(irn, 1, get_irn_n(left, 1));
704 /* check if the node is an address mode candidate */
705 else if (is_candidate(block, irn, 0)) {
706 DBG((mod, LEVEL_1, "\tfound address mode candidate %+F ... ", irn));
708 left = get_irn_n(irn, 2);
709 if (get_irn_arity(irn) == 4) {
710 /* it's an "unary" operation */
714 right = get_irn_n(irn, 3);
717 /* normalize commutative ops */
718 if (node_is_comm(irn)) {
719 /* Assure that right operand is always a Load if there is one */
720 /* because non-commutative ops can only use Dest AM if the right */
721 /* operand is a load, so we only need to check right operand. */
722 if (pred_is_specific_nodeblock(block, left, is_ia32_Ld))
724 set_irn_n(irn, 2, right);
725 set_irn_n(irn, 3, left);
733 /* check for Store -> op -> Load */
735 /* Store -> op -> Load optimization is only possible if supported by op */
736 /* and if right operand is a Load */
737 if ((get_ia32_am_support(irn) & ia32_am_Dest) &&
738 pred_is_specific_nodeblock(block, right, is_ia32_Ld))
741 /* An address mode capable op always has a result Proj. */
742 /* If this Proj is used by more than one other node, we don't need to */
743 /* check further, otherwise we check for Store and remember the address, */
744 /* the Store points to. */
746 succ = get_res_proj(irn);
747 assert(succ && "Couldn't find result proj");
753 /* now check for users and Store */
754 if (ia32_get_irn_n_edges(succ) == 1) {
755 succ = get_edge_src_irn(get_irn_out_edge_first(succ));
757 if (is_ia32_fStore(succ) || is_ia32_Store(succ)) {
759 addr_b = get_irn_n(store, 0);
761 /* Could be that the Store is connected to the address */
762 /* calculating LEA while the Load is already transformed. */
763 if (is_ia32_Lea(addr_b)) {
765 addr_b = get_irn_n(succ, 0);
766 addr_i = get_irn_n(succ, 1);
775 /* we found a Store as single user: Now check for Load */
777 /* Extra check for commutative ops with two Loads */
778 /* -> put the interesting Load right */
779 if (node_is_comm(irn) &&
780 pred_is_specific_nodeblock(block, left, is_ia32_Ld))
782 if ((addr_b == get_irn_n(get_Proj_pred(left), 0)) &&
783 (addr_i == get_irn_n(get_Proj_pred(left), 1)))
785 /* We exchange left and right, so it's easier to kill */
786 /* the correct Load later and to handle unary operations. */
787 set_irn_n(irn, 2, right);
788 set_irn_n(irn, 3, left);
796 /* skip the Proj for easier access */
797 load = get_Proj_pred(right);
799 /* Compare Load and Store address */
800 if (load_store_addr_is_equal(load, store, addr_b, addr_i)) {
801 /* Right Load is from same address, so we can */
802 /* disconnect the Load and Store here */
804 /* set new base, index and attributes */
805 set_irn_n(irn, 0, addr_b);
806 set_irn_n(irn, 1, addr_i);
807 add_ia32_am_offs(irn, get_ia32_am_offs(load));
808 set_ia32_am_scale(irn, get_ia32_am_scale(load));
809 set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
810 set_ia32_op_type(irn, ia32_AddrModeD);
811 set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
812 set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
814 if (is_ia32_use_frame(load))
815 set_ia32_use_frame(irn);
817 /* connect to Load memory and disconnect Load */
818 if (get_irn_arity(irn) == 5) {
820 set_irn_n(irn, 4, get_irn_n(load, 2));
821 set_irn_n(irn, 3, noreg_gp);
825 set_irn_n(irn, 3, get_irn_n(load, 2));
826 set_irn_n(irn, 2, noreg_gp);
829 /* connect the memory Proj of the Store to the op */
830 mem_proj = get_mem_proj(store);
831 set_Proj_pred(mem_proj, irn);
832 set_Proj_proj(mem_proj, 1);
834 DB((mod, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
837 else if (get_ia32_am_support(irn) & ia32_am_Source) {
838 /* There was no store, check if we still can optimize for source address mode */
841 } /* if (support AM Dest) */
842 else if (get_ia32_am_support(irn) & ia32_am_Source) {
843 /* op doesn't support am AM Dest -> check for AM Source */
847 /* normalize commutative ops */
848 if (node_is_comm(irn)) {
849 /* Assure that left operand is always a Load if there is one */
850 /* because non-commutative ops can only use Source AM if the */
851 /* left operand is a Load, so we only need to check the left */
852 /* operand afterwards. */
853 if (pred_is_specific_nodeblock(block, right, is_ia32_Ld)) {
854 set_irn_n(irn, 2, right);
855 set_irn_n(irn, 3, left);
863 /* optimize op -> Load iff Load is only used by this op */
864 /* and left operand is a Load which only used by this irn */
866 pred_is_specific_nodeblock(block, left, is_ia32_Ld) &&
867 (ia32_get_irn_n_edges(left) == 1))
869 left = get_Proj_pred(left);
871 addr_b = get_irn_n(left, 0);
872 addr_i = get_irn_n(left, 1);
874 /* set new base, index and attributes */
875 set_irn_n(irn, 0, addr_b);
876 set_irn_n(irn, 1, addr_i);
877 add_ia32_am_offs(irn, get_ia32_am_offs(left));
878 set_ia32_am_scale(irn, get_ia32_am_scale(left));
879 set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
880 set_ia32_op_type(irn, ia32_AddrModeS);
881 set_ia32_frame_ent(irn, get_ia32_frame_ent(left));
882 set_ia32_ls_mode(irn, get_ia32_ls_mode(left));
884 if (is_ia32_use_frame(left))
885 set_ia32_use_frame(irn);
887 /* connect to Load memory */
888 if (get_irn_arity(irn) == 5) {
890 set_irn_n(irn, 4, get_irn_n(left, 2));
894 set_irn_n(irn, 3, get_irn_n(left, 2));
897 /* disconnect from Load */
898 set_irn_n(irn, 2, noreg_gp);
900 /* If Load has a memory Proj, connect it to the op */
901 mem_proj = get_mem_proj(left);
903 set_Proj_pred(mem_proj, irn);
904 set_Proj_proj(mem_proj, 1);
907 DB((mod, LEVEL_1, "merged with %+F into source AM\n", left));