nsz Git - libfirm/blob - ir/be/ia32/ia32_optimize.c

   1 #ifdef HAVE_CONFIG_H
   2 #include "config.h"
   3 #endif
   4
   5 #include "irnode.h"
   6 #include "irprog_t.h"
   7 #include "ircons.h"
   8 #include "firm_types.h"
   9 #include "iredges.h"
  10 #include "tv.h"
  11 #include "irgmod.h"
  12
  13 #include "../benode_t.h"
  14
  15 #include "ia32_new_nodes.h"
  16 #include "bearch_ia32_t.h"
  17
  18 #undef is_NoMem
  19 #define is_NoMem(irn) (get_irn_op(irn) == op_NoMem)
  20
  21 /**
  22  * creates a unique ident by adding a number to a tag
  23  *
  24  * @param tag   the tag string, must contain a %d if a number
  25  *              should be added
  26  */
  27 static ident *unique_id(const char *tag)
  28 {
  29         static unsigned id = 0;
  30         char str[256];
  31
  32         snprintf(str, sizeof(str), tag, ++id);
  33         return new_id_from_str(str);
  34 }
  35
  36
  37
  38 /**
  39  * Transforms a SymConst.
  40  *
  41  * @param mod     the debug module
  42  * @param block   the block the new node should belong to
  43  * @param node    the ir SymConst node
  44  * @param mode    mode of the SymConst
  45  * @return the created ia32 Const node
  46  */
  47 static ir_node *gen_SymConst(ia32_transform_env_t *env) {
  48         ir_node  *cnst;
  49         dbg_info *dbg   = env->dbg;
  50         ir_mode  *mode  = env->mode;
  51         ir_graph *irg   = env->irg;
  52         ir_node  *block = env->block;
  53
  54         cnst = new_rd_ia32_Const(dbg, irg, block, mode);
  55         set_ia32_Const_attr(cnst, env->irn);
  56         return cnst;
  57 }
  58
  59 /**
  60  * Get a primitive type for a mode.
  61  */
  62 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
  63 {
  64         pmap_entry *e = pmap_find(types, mode);
  65         ir_type *res;
  66
  67         if (! e) {
  68                 char buf[64];
  69                 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
  70                 res = new_type_primitive(new_id_from_str(buf), mode);
  71                 pmap_insert(types, mode, res);
  72         }
  73         else
  74                 res = e->value;
  75         return res;
  76 }
  77
  78 /**
  79  * Get an entity that is initialized with a tarval
  80  */
  81 static entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
  82 {
  83         tarval *tv    = get_Const_tarval(cnst);
  84         pmap_entry *e = pmap_find(cg->tv_ent, tv);
  85         entity *res;
  86         ir_graph *rem;
  87
  88         if (! e) {
  89                 ir_mode *mode = get_irn_mode(cnst);
  90                 ir_type *tp = get_Const_type(cnst);
  91                 if (tp == firm_unknown_type)
  92                         tp = get_prim_type(cg->types, mode);
  93
  94                 res = new_entity(get_glob_type(), unique_id("ia32FloatCnst_%u"), tp);
  95
  96                 set_entity_ld_ident(res, get_entity_ident(res));
  97                 set_entity_visibility(res, visibility_local);
  98                 set_entity_variability(res, variability_constant);
  99                 set_entity_allocation(res, allocation_static);
 100
 101                  /* we create a new entity here: It's initialization must resist on the
 102                     const code irg */
 103                 rem = current_ir_graph;
 104                 current_ir_graph = get_const_code_irg();
 105                 set_atomic_ent_value(res, new_Const_type(tv, tp));
 106                 current_ir_graph = rem;
 107         }
 108         else
 109                 res = e->value;
 110         return res;
 111 }
 112
 113 /**
 114  * Transforms a Const.
 115  *
 116  * @param mod     the debug module
 117  * @param block   the block the new node should belong to
 118  * @param node    the ir Const node
 119  * @param mode    mode of the Const
 120  * @return the created ia32 Const node
 121  */
 122 static ir_node *gen_Const(ia32_transform_env_t *env) {
 123         ir_node *cnst;
 124         symconst_symbol sym;
 125         ir_graph *irg   = env->irg;
 126         ir_node  *block = env->block;
 127         ir_node  *node  = env->irn;
 128         dbg_info *dbg   = env->dbg;
 129         ir_mode  *mode  = env->mode;
 130
 131         if (mode_is_float(mode)) {
 132                 sym.entity_p = get_entity_for_tv(env->cg, node);
 133
 134                 cnst = new_rd_SymConst(dbg, irg, block, sym, symconst_addr_ent);
 135                 env->irn = cnst;
 136                 cnst = gen_SymConst(env);
 137         }
 138         else {
 139                 cnst = new_rd_ia32_Const(dbg, irg, block, get_irn_mode(node));
 140                 set_ia32_Const_attr(cnst, node);
 141         }
 142         return cnst;
 143 }
 144
 145
 146
 147 /**
 148  * Transforms (all) Const's into ia32_Const and places them in the
 149  * block where they are used (or in the cfg-pred Block in case of Phi's)
 150  */
 151 void ia32_place_consts(ir_node *irn, void *env) {
 152         ia32_code_gen_t      *cg = env;
 153         ia32_transform_env_t  tenv;
 154         ir_mode              *mode;
 155         ir_node              *pred, *cnst;
 156         int                   i;
 157         opcode                opc;
 158
 159         if (is_Block(irn))
 160                 return;
 161
 162         mode = get_irn_mode(irn);
 163
 164         tenv.arch_env = cg->arch_env;
 165         tenv.block    = get_nodes_block(irn);
 166         tenv.cg       = cg;
 167         tenv.irg      = cg->irg;
 168         tenv.mod      = cg->mod;
 169
 170         /* Loop over all predecessors and check for Sym/Const nodes */
 171         for (i = get_irn_arity(irn) - 1; i >= 0; --i) {
 172                 pred      = get_irn_n(irn, i);
 173                 cnst      = NULL;
 174                 opc       = get_irn_opcode(pred);
 175                 tenv.irn  = pred;
 176                 tenv.mode = get_irn_mode(pred);
 177                 tenv.dbg  = get_irn_dbg_info(pred);
 178
 179                 /* If it's a Phi, then we need to create the */
 180                 /* new Const in it's predecessor block       */
 181                 if (is_Phi(irn)) {
 182                         tenv.block = get_Block_cfgpred_block(get_nodes_block(irn), i);
 183                 }
 184
 185                 switch (opc) {
 186                         case iro_Const:
 187                                 cnst = gen_Const(&tenv);
 188                                 break;
 189                         case iro_SymConst:
 190                                 cnst = gen_SymConst(&tenv);
 191                                 break;
 192                         default:
 193                                 break;
 194                 }
 195
 196                 /* if we found a const, then set it */
 197                 if (cnst) {
 198                         set_irn_n(irn, i, cnst);
 199                 }
 200         }
 201 }
 202
 203
 204 /******************************************************************
 205  *              _     _                   __  __           _
 206  *     /\      | |   | |                 |  \/  |         | |
 207  *    /  \   __| | __| |_ __ ___  ___ ___| \  / | ___   __| | ___
 208  *   / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \
 209  *  / ____ \ (_| | (_| | | |  __/\__ \__ \ |  | | (_) | (_| |  __/
 210  * /_/    \_\__,_|\__,_|_|  \___||___/___/_|  |_|\___/ \__,_|\___|
 211  *
 212  ******************************************************************/
 213
 214 static int node_is_comm(const ir_node *irn) {
 215         if (is_ia32_Add(irn)  ||
 216                 is_ia32_fAdd(irn) ||
 217                 is_ia32_Mul(irn)  ||
 218                 is_ia32_Mulh(irn) ||
 219                 is_ia32_fMul(irn) ||
 220                 is_ia32_And(irn)  ||
 221                 is_ia32_fAnd(irn) ||
 222                 is_ia32_Or(irn)   ||
 223                 is_ia32_fOr(irn)  ||
 224                 is_ia32_Eor(irn)  ||
 225                 is_ia32_fEor(irn) ||
 226                 is_ia32_Min(irn)  ||
 227                 is_ia32_fMin(irn) ||
 228                 is_ia32_Max(irn)  ||
 229                 is_ia32_fMax(irn))
 230         {
 231                 return 1;
 232         }
 233
 234         return 0;
 235 }
 236
 237 /**
 238  * Returns the first mode_M Proj connected to irn.
 239  */
 240 static ir_node *get_mem_proj(const ir_node *irn) {
 241         const ir_edge_t *edge;
 242         ir_node         *src;
 243
 244         assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
 245
 246         foreach_out_edge(irn, edge) {
 247                 src = get_edge_src_irn(edge);
 248
 249                 assert(is_Proj(src) && "Proj expected");
 250
 251                 if (get_irn_mode(src) == mode_M)
 252                         return src;
 253         }
 254
 255         return NULL;
 256 }
 257
 258 /**
 259  * Returns the Proj with number 0 connected to irn.
 260  */
 261 static ir_node *get_res_proj(const ir_node *irn) {
 262         const ir_edge_t *edge;
 263         ir_node         *src;
 264
 265         assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
 266
 267         foreach_out_edge(irn, edge) {
 268                 src = get_edge_src_irn(edge);
 269
 270                 assert(is_Proj(src) && "Proj expected");
 271
 272                 if (get_Proj_proj(src) == 0)
 273                         return src;
 274         }
 275
 276         return NULL;
 277 }
 278
 279
 280 /**
 281  * Determines if irn is a Proj and if is_op_func returns true for it's predecessor.
 282  */
 283 static int pred_is_specific_node(const ir_node *irn, int (*is_op_func)(const ir_node *n)) {
 284         if (is_Proj(irn) && is_op_func(get_Proj_pred(irn))) {
 285                 return 1;
 286         }
 287
 288         return 0;
 289 }
 290
 291 /**
 292  * Folds Add or Sub to LEA if possible
 293  */
 294 static ir_node *fold_addr(ir_node *irn, firm_dbg_module_t *mod, ir_node *noreg) {
 295         ir_graph *irg      = get_irn_irg(irn);
 296         ir_mode  *mode     = get_irn_mode(irn);
 297         dbg_info *dbg      = get_irn_dbg_info(irn);
 298         ir_node  *block    = get_nodes_block(irn);
 299         ir_node  *res      = irn;
 300         char     *offs     = NULL;
 301         char     *new_offs = NULL;
 302         int       scale    = 0;
 303         int       isadd    = 0;
 304         int       dolea    = 0;
 305         ir_node  *left, *right, *temp;
 306         ir_node  *base, *index;
 307         ia32_am_flavour_t am_flav;
 308
 309         if (is_ia32_Add(irn))
 310                 isadd = 1;
 311
 312         left  = get_irn_n(irn, 2);
 313         right = get_irn_n(irn, 3);
 314
 315         /* "normalize" arguments in case of add */
 316         if  (isadd) {
 317                 /* put LEA == ia32_am_O as right operand */
 318                 if (is_ia32_Lea(left) && get_ia32_am_flavour(left) == ia32_am_O) {
 319                         set_irn_n(irn, 2, right);
 320                         set_irn_n(irn, 3, left);
 321                         temp  = left;
 322                         left  = right;
 323                         right = temp;
 324                 }
 325
 326                 /* put LEA != ia32_am_O as left operand */
 327                 if (is_ia32_Lea(right) && get_ia32_am_flavour(right) != ia32_am_O) {
 328                         set_irn_n(irn, 2, right);
 329                         set_irn_n(irn, 3, left);
 330                         temp  = left;
 331                         left  = right;
 332                         right = temp;
 333                 }
 334
 335                 /* put SHL as right operand */
 336                 if (pred_is_specific_node(left, is_ia32_Shl)) {
 337                         set_irn_n(irn, 2, right);
 338                         set_irn_n(irn, 3, left);
 339                         temp  = left;
 340                         left  = right;
 341                         right = temp;
 342                 }
 343         }
 344
 345         /* Left operand could already be a LEA */
 346         if (is_ia32_Lea(left)) {
 347                 DBG((mod, LEVEL_1, "\tgot LEA as left operand\n"));
 348
 349                 base  = get_irn_n(left, 0);
 350                 index = get_irn_n(left, 1);
 351                 offs  = get_ia32_am_offs(left);
 352                 scale = get_ia32_am_scale(left);
 353         }
 354         else {
 355                 base  = left;
 356                 index = noreg;
 357                 offs  = NULL;
 358                 scale = 0;
 359
 360         }
 361
 362         /* check if operand is either const or right operand is AMConst (LEA with ia32_am_O) */
 363         if (get_ia32_cnst(irn)) {
 364                 DBG((mod, LEVEL_1, "\tfound op with imm"));
 365
 366                 new_offs = get_ia32_cnst(irn);
 367                 dolea    = 1;
 368         }
 369         else if (is_ia32_Lea(right) && get_ia32_am_flavour(right) == ia32_am_O) {
 370                 DBG((mod, LEVEL_1, "\tgot op with LEA am_O"));
 371
 372                 new_offs = get_ia32_am_offs(right);
 373                 dolea    = 1;
 374         }
 375         /* we can only get an additional index if there isn't already one */
 376         else if (isadd && be_is_NoReg(index)) {
 377                 /* default for add -> make right operand to index */
 378                 index = right;
 379                 dolea = 1;
 380
 381                 DBG((mod, LEVEL_1, "\tgot LEA candidate with index %+F\n", index));
 382                 /* check for SHL 1,2,3 */
 383                 if (pred_is_specific_node(right, is_ia32_Shl)) {
 384                         temp = get_Proj_pred(right);
 385
 386                         if (get_ia32_Immop_tarval(temp)) {
 387                                 scale = get_tarval_long(get_ia32_Immop_tarval(temp));
 388
 389                                 if (scale <= 3) {
 390                                         index = get_irn_n(temp, 2);
 391
 392                                         DBG((mod, LEVEL_1, "\tgot scaled index %+F\n", index));
 393                                 }
 394                         }
 395                 }
 396         }
 397
 398         /* ok, we can create a new LEA */
 399         if (dolea) {
 400                 res = new_rd_ia32_Lea(dbg, irg, block, base, index, mode_Is);
 401
 402                 /* add the old offset of a previous LEA */
 403                 if (offs) {
 404                         add_ia32_am_offs(res, offs);
 405                 }
 406
 407                 /* add the new offset */
 408                 if (isadd) {
 409                         if (new_offs) {
 410                                 add_ia32_am_offs(res, new_offs);
 411                         }
 412                 }
 413                 else {
 414                         sub_ia32_am_offs(res, new_offs);
 415                 }
 416
 417                 /* set scale */
 418                 set_ia32_am_scale(res, scale);
 419
 420                 am_flav = ia32_am_N;
 421                 /* determine new am flavour */
 422                 if (offs || new_offs) {
 423                         am_flav |= ia32_O;
 424                 }
 425                 if (! be_is_NoReg(base)) {
 426                         am_flav |= ia32_B;
 427                 }
 428                 if (! be_is_NoReg(index)) {
 429                         am_flav |= ia32_I;
 430                 }
 431                 if (scale > 0) {
 432                         am_flav |= ia32_S;
 433                 }
 434                 set_ia32_am_flavour(res, am_flav);
 435
 436                 set_ia32_op_type(res, ia32_AddrModeS);
 437
 438                 DBG((mod, LEVEL_1, "\tLEA [%+F + %+F * %d + %s]\n", base, index, scale, get_ia32_am_offs(res)));
 439
 440                 /* get the result Proj of the Add/Sub */
 441                 irn = get_res_proj(irn);
 442
 443                 assert(irn && "Couldn't find result proj");
 444
 445                 /* exchange the old op with the new LEA */
 446                 exchange(irn, res);
 447         }
 448
 449         return res;
 450 }
 451
 452 /**
 453  * Optimizes a pattern around irn to address mode if possible.
 454  */
 455 void ia32_optimize_am(ir_node *irn, void *env) {
 456         ia32_code_gen_t   *cg  = env;
 457         ir_graph          *irg = cg->irg;
 458         firm_dbg_module_t *mod = cg->mod;
 459         ir_node           *res = irn;
 460         dbg_info          *dbg;
 461         ir_mode           *mode;
 462         ir_node           *block, *noreg_gp, *noreg_fp;
 463         ir_node           *left, *right, *temp;
 464         ir_node           *store, *mem_proj;
 465         ir_node           *succ, *addr_b, *addr_i;
 466         int                check_am_src = 0;
 467
 468         if (! is_ia32_irn(irn))
 469                 return;
 470
 471         dbg      = get_irn_dbg_info(irn);
 472         mode     = get_irn_mode(irn);
 473         block    = get_nodes_block(irn);
 474         noreg_gp = ia32_new_NoReg_gp(cg);
 475         noreg_fp = ia32_new_NoReg_fp(cg);
 476
 477         DBG((mod, LEVEL_1, "checking for AM\n"));
 478
 479         /* 1st part: check for address calculations and transform the into Lea */
 480
 481         /* Following cases can occur: */
 482         /* - Sub (l, imm) -> LEA [base - offset] */
 483         /* - Sub (l, r == LEA with ia32_am_O)   -> LEA [base - offset] */
 484         /* - Add (l, imm) -> LEA [base + offset] */
 485         /* - Add (l, r == LEA with ia32_am_O)  -> LEA [base + offset] */
 486         /* - Add (l == LEA with ia32_am_O, r)  -> LEA [base + offset] */
 487         /* - Add (l, r) -> LEA [base + index * scale] */
 488         /*              with scale > 1 iff l/r == shl (1,2,3) */
 489
 490         if (is_ia32_Sub(irn) || is_ia32_Add(irn)) {
 491                 left  = get_irn_n(irn, 2);
 492                 right = get_irn_n(irn, 3);
 493
 494             /* Do not try to create a LEA if one of the operands is a Load. */
 495                 if (! pred_is_specific_node(left,  is_ia32_Load)  &&
 496                         ! pred_is_specific_node(right, is_ia32_Load))
 497                 {
 498                         res = fold_addr(irn, mod, noreg_gp);
 499                 }
 500         }
 501
 502         /* 2nd part: fold following patterns:
 503         /* - Load  -> LEA into Load  } TODO: If the LEA is used by more than one Load/Store */
 504         /* - Store -> LEA into Store }       it might be better to keep the LEA             */
 505         /* - op -> Load into AMop with am_Source
 506         /*   conditions:                */
 507         /*     - op is am_Source capable AND   */
 508         /*     - the Load is only used by this op AND */
 509         /*     - the Load is in the same block */
 510         /* - Store -> op -> Load  into AMop with am_Dest  */
 511         /*   conditions:                */
 512         /*     - op is am_Dest capable AND   */
 513         /*     - the Store uses the same address as the Load AND */
 514         /*     - the Load is only used by this op AND */
 515         /*     - the Load and Store are in the same block AND  */
 516         /*     - nobody else uses the result of the op */
 517
 518         if ((res == irn) && (get_ia32_am_support(irn) != ia32_am_None) && !is_ia32_Lea(irn)) {
 519                 /* 1st: check for Load/Store -> LEA   */
 520                 if (is_ia32_Load(irn)  || is_ia32_fLoad(irn) ||
 521                         is_ia32_Store(irn) || is_ia32_fStore(irn))
 522                 {
 523                         left = get_irn_n(irn, 0);
 524
 525                         if (is_ia32_Lea(left)) {
 526                                 /* get the AM attributes from the LEA */
 527                                 add_ia32_am_offs(irn, get_ia32_am_offs(left));
 528                                 set_ia32_am_scale(irn, get_ia32_am_scale(left));
 529                                 set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
 530                                 set_ia32_op_type(irn, get_ia32_op_type(left));
 531
 532                                 /* set base and index */
 533                                 set_irn_n(irn, 0, get_irn_n(left, 0));
 534                                 set_irn_n(irn, 1, get_irn_n(left, 1));
 535                         }
 536                 }
 537                 /* check if at least one operand is a Load */
 538                 else if (pred_is_specific_node(get_irn_n(irn, 2), is_ia32_Load)  ||
 539                                  pred_is_specific_node(get_irn_n(irn, 2), is_ia32_fLoad) ||
 540                                  pred_is_specific_node(get_irn_n(irn, 3), is_ia32_Load)  ||
 541                                  pred_is_specific_node(get_irn_n(irn, 3), is_ia32_fLoad))
 542                 {
 543
 544                         /* normalize commutative ops */
 545                         if (node_is_comm(irn)) {
 546                                 left  = get_irn_n(irn, 2);
 547                                 right = get_irn_n(irn, 3);
 548
 549                                 /* assure that Left operand is always a Load if there is one */
 550                                 if (pred_is_specific_node(right, is_ia32_Load) ||
 551                                         pred_is_specific_node(right, is_ia32_fLoad))
 552                                 {
 553                                         set_irn_n(irn, 2, right);
 554                                         set_irn_n(irn, 3, left);
 555
 556                                         temp  = left;
 557                                         left  = right;
 558                                         right = temp;
 559                                 }
 560                         }
 561
 562                         /* check for Store -> op -> Load */
 563
 564                         /* Store -> op -> Load optimization is only possible if supported by op */
 565                         if (get_ia32_am_support(irn) & ia32_am_Dest) {
 566
 567                                 /* An address mode capable op always has a result Proj.                  */
 568                                 /* If this Proj is used by more than one other node, we don't need to    */
 569                                 /* check further, otherwise we check for Store and remember the address, */
 570                                 /* the Store points to. */
 571
 572                                 succ = get_res_proj(irn);
 573                                 assert(succ && "Couldn't find result proj");
 574
 575                                 addr_b = NULL;
 576                                 addr_i = NULL;
 577                                 store  = NULL;
 578
 579                                 /* now check for users and Store */
 580                                 if (get_irn_n_edges(succ) == 1) {
 581                                         succ = get_edge_src_irn(get_irn_out_edge_first(succ));
 582
 583                                         if (is_ia32_fStore(succ) || is_ia32_Store(succ)) {
 584                                                 store  = succ;
 585                                                 addr_b = get_irn_n(store, 0);
 586
 587                                                 /* Could be that the Store is connected to the address    */
 588                                                 /* calculating LEA while the Load is already transformed. */
 589                                                 if (is_ia32_Lea(addr_b)) {
 590                                                         succ   = addr_b;
 591                                                         addr_b = get_irn_n(succ, 0);
 592                                                         addr_i = get_irn_n(succ, 1);
 593                                                 }
 594                                                 else {
 595                                                         addr_i = noreg_gp;
 596                                                 }
 597                                         }
 598                                 }
 599
 600                                 if (store) {
 601                                         /* we found a Store as single user: Now check for Load */
 602                                         left  = get_irn_n(irn, 2);
 603                                         right = get_irn_n(irn, 3);
 604
 605                                         /* Could be that the right operand is also a Load, so we make */
 606                                         /* sure that the "interesting" Load is always the left one    */
 607
 608                                         /* right != NoMem means, we have a "binary" operation */
 609                                         if (! is_NoMem(right) &&
 610                                                 (pred_is_specific_node(right, is_ia32_Load) ||
 611                                                  pred_is_specific_node(right, is_ia32_fLoad)))
 612                                         {
 613                                                 if ((addr_b == get_irn_n(get_Proj_pred(right), 0)) &&
 614                                                         (addr_i == get_irn_n(get_Proj_pred(right), 1)))
 615                                                 {
 616                                                         /* We exchange left and right, so it's easier to kill     */
 617                                                         /* the correct Load later and to handle unary operations. */
 618                                                         set_irn_n(irn, 2, right);
 619                                                         set_irn_n(irn, 3, left);
 620
 621                                                         temp  = left;
 622                                                         left  = right;
 623                                                         right = temp;
 624                                                 }
 625                                         }
 626
 627                                         /* skip the Proj for easier access */
 628                                         left  = get_Proj_pred(left);
 629
 630                                         /* Compare Load and Store address */
 631                                         if ((addr_b == get_irn_n(left, 0)) && (addr_i == get_irn_n(left, 1)))
 632                                         {
 633                                                 /* Left Load is from same address, so we can */
 634                                                 /* disconnect the Load and Store here        */
 635
 636                                                 /* set new base, index and attributes */
 637                                                 set_irn_n(irn, 0, addr_b);
 638                                                 set_irn_n(irn, 1, addr_i);
 639                                                 add_ia32_am_offs(irn, get_ia32_am_offs(left));
 640                                                 set_ia32_am_scale(irn, get_ia32_am_scale(left));
 641                                                 set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
 642                                                 set_ia32_op_type(irn, ia32_AddrModeD);
 643
 644                                                 /* connect to Load memory */
 645                                                 if (get_irn_arity(irn) == 5) {
 646                                                         /* binary AMop */
 647                                                         set_irn_n(irn, 4, get_irn_n(left, 2));
 648                                                 }
 649                                                 else {
 650                                                         /* unary AMop */
 651                                                         set_irn_n(irn, 3, get_irn_n(left, 2));
 652                                                 }
 653
 654                                                 /* disconnect from Load */
 655                                                 set_irn_n(irn, 2, noreg_gp);
 656
 657                                                 /* connect the memory Proj of the Store to the op */
 658                                                 mem_proj = get_mem_proj(store);
 659                                                 set_Proj_pred(mem_proj, irn);
 660                                                 set_Proj_proj(mem_proj, 1);
 661                                         }
 662                                 } /* if (store) */
 663                                 else if (get_ia32_am_support(irn) & ia32_am_Source) {
 664                                         /* There was no store, check if we still can optimize for source address mode */
 665                                         check_am_src = 1;
 666                                 }
 667                         } /* if (support AM Dest) */
 668                         else {
 669                                 /* op doesn't support am AM Dest -> check for AM Source */
 670                                 check_am_src = 1;
 671                         }
 672
 673                         /* optimize op -> Load iff Load is only used by this op */
 674                         if (check_am_src) {
 675                                 left = get_irn_n(irn, 2);
 676
 677                                 if (get_irn_n_edges(left) == 1) {
 678                                         left = get_Proj_pred(left);
 679
 680                                         addr_b = get_irn_n(left, 0);
 681                                         addr_i = get_irn_n(left, 1);
 682
 683                                         /* set new base, index and attributes */
 684                                         set_irn_n(irn, 0, addr_b);
 685                                         set_irn_n(irn, 1, addr_i);
 686                                         add_ia32_am_offs(irn, get_ia32_am_offs(left));
 687                                         set_ia32_am_scale(irn, get_ia32_am_scale(left));
 688                                         set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
 689                                         set_ia32_op_type(irn, ia32_AddrModeS);
 690
 691                                         /* connect to Load memory */
 692                                         if (get_irn_arity(irn) == 5) {
 693                                                 /* binary AMop */
 694                                                 set_irn_n(irn, 4, get_irn_n(left, 2));
 695                                         }
 696                                         else {
 697                                                 /* unary AMop */
 698                                                 set_irn_n(irn, 3, get_irn_n(left, 2));
 699                                         }
 700
 701                                         /* disconnect from Load */
 702                                         set_irn_n(irn, 2, noreg_gp);
 703
 704                                         /* If Load has a memory Proj, connect it to the op */
 705                                         mem_proj = get_mem_proj(left);
 706                                         if (mem_proj) {
 707                                                 set_Proj_pred(mem_proj, irn);
 708                                                 set_Proj_proj(mem_proj, 1);
 709                                         }
 710                                 }
 711                         }
 712                 }
 713         }
 714 }