2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Matthias Braun, Christian Wuerdig
34 #include "firm_types.h"
46 #include "../benode_t.h"
47 #include "../besched_t.h"
48 #include "../bepeephole.h"
50 #include "ia32_new_nodes.h"
51 #include "ia32_optimize.h"
52 #include "bearch_ia32_t.h"
53 #include "gen_ia32_regalloc_if.h"
54 #include "ia32_transform.h"
55 #include "ia32_dbg_stat.h"
56 #include "ia32_util.h"
57 #include "ia32_architecture.h"
59 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
61 static const arch_env_t *arch_env;
62 static ia32_code_gen_t *cg;
64 static void peephole_IncSP_IncSP(ir_node *node);
67 static void peephole_ia32_Store_IncSP_to_push(ir_node *node)
69 ir_node *base = get_irn_n(node, n_ia32_Store_base);
70 ir_node *index = get_irn_n(node, n_ia32_Store_index);
71 ir_node *mem = get_irn_n(node, n_ia32_Store_mem);
72 ir_node *incsp = base;
84 /* nomem inidicates the store doesn't alias with anything else */
88 /* find an IncSP in front of us, we might have to skip barriers for this */
89 while(is_Proj(incsp)) {
90 ir_node *proj_pred = get_Proj_pred(incsp);
91 if(!be_is_Barrier(proj_pred))
93 incsp = get_irn_n(proj_pred, get_Proj_proj(incsp));
95 if(!be_is_IncSP(incsp))
98 peephole_IncSP_IncSP(incsp);
100 /* must be in the same block */
101 if(get_nodes_block(incsp) != get_nodes_block(node))
104 if(!is_ia32_NoReg_GP(index) || get_ia32_am_sc(node) != NULL) {
105 panic("Invalid storeAM found (%+F)", node);
108 /* we should be the store to the end of the stackspace */
109 offset = be_get_IncSP_offset(incsp);
110 mode = get_ia32_ls_mode(node);
111 node_offset = get_ia32_am_offs_int(node);
112 if(node_offset != offset - get_mode_size_bytes(mode))
115 /* we can use a push instead of the store */
116 irg = current_ir_graph;
117 block = get_nodes_block(node);
118 dbgi = get_irn_dbg_info(node);
119 noreg = ia32_new_NoReg_gp(cg);
120 base = be_get_IncSP_pred(incsp);
121 val = get_irn_n(node, n_ia32_Store_val);
122 push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, mem, val, base);
124 proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
126 be_set_IncSP_offset(incsp, offset - get_mode_size_bytes(mode));
128 sched_add_before(node, push);
131 be_peephole_before_exchange(node, proj);
132 exchange(node, proj);
133 be_peephole_after_exchange(proj);
136 static void peephole_ia32_Store(ir_node *node)
138 peephole_ia32_Store_IncSP_to_push(node);
142 static int produces_zero_flag(ir_node *node, int pn)
145 const ia32_immediate_attr_t *imm_attr;
147 if(!is_ia32_irn(node))
151 if(pn != pn_ia32_res)
155 switch(get_ia32_irn_opcode(node)) {
173 assert(n_ia32_ShlD_count == n_ia32_ShrD_count);
174 assert(n_ia32_Shl_count == n_ia32_Shr_count
175 && n_ia32_Shl_count == n_ia32_Sar_count);
176 if(is_ia32_ShlD(node) || is_ia32_ShrD(node)) {
177 count = get_irn_n(node, n_ia32_ShlD_count);
179 count = get_irn_n(node, n_ia32_Shl_count);
181 /* when shift count is zero the flags are not affected, so we can only
182 * do this for constants != 0 */
183 if(!is_ia32_Immediate(count))
186 imm_attr = get_ia32_immediate_attr_const(count);
187 if(imm_attr->symconst != NULL)
189 if((imm_attr->offset & 0x1f) == 0)
199 static ir_node *turn_into_mode_t(ir_node *node)
204 const arch_register_t *reg;
206 if(get_irn_mode(node) == mode_T)
209 assert(get_irn_mode(node) == mode_Iu);
211 new_node = exact_copy(node);
212 set_irn_mode(new_node, mode_T);
214 block = get_nodes_block(new_node);
215 res_proj = new_r_Proj(current_ir_graph, block, new_node, mode_Iu,
218 reg = arch_get_irn_register(arch_env, node);
219 arch_set_irn_register(arch_env, res_proj, reg);
221 be_peephole_before_exchange(node, res_proj);
222 sched_add_before(node, new_node);
224 exchange(node, res_proj);
225 be_peephole_after_exchange(res_proj);
230 static void peephole_ia32_Test(ir_node *node)
232 ir_node *left = get_irn_n(node, n_ia32_Test_left);
233 ir_node *right = get_irn_n(node, n_ia32_Test_right);
239 const ir_edge_t *edge;
241 assert(n_ia32_Test_left == n_ia32_Test8Bit_left
242 && n_ia32_Test_right == n_ia32_Test8Bit_right);
244 /* we need a test for 0 */
248 block = get_nodes_block(node);
249 if(get_nodes_block(left) != block)
253 pn = get_Proj_proj(left);
254 left = get_Proj_pred(left);
257 /* happens rarely, but if it does code will panic' */
258 if (is_ia32_Unknown_GP(left))
261 /* walk schedule up and abort when we find left or some other node destroys
263 schedpoint = sched_prev(node);
264 while(schedpoint != left) {
265 schedpoint = sched_prev(schedpoint);
266 if(arch_irn_is(arch_env, schedpoint, modify_flags))
268 if(schedpoint == block)
269 panic("couldn't find left");
272 /* make sure only Lg/Eq tests are used */
273 foreach_out_edge(node, edge) {
274 ir_node *user = get_edge_src_irn(edge);
275 int pnc = get_ia32_condcode(user);
277 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) {
282 if(!produces_zero_flag(left, pn))
285 left = turn_into_mode_t(left);
287 flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
288 flags_proj = new_r_Proj(current_ir_graph, block, left, flags_mode,
290 arch_set_irn_register(arch_env, flags_proj, &ia32_flags_regs[REG_EFLAGS]);
292 assert(get_irn_mode(node) != mode_T);
294 be_peephole_before_exchange(node, flags_proj);
295 exchange(node, flags_proj);
297 be_peephole_after_exchange(flags_proj);
301 * AMD Athlon works faster when RET is not destination of
302 * conditional jump or directly preceded by other jump instruction.
303 * Can be avoided by placing a Rep prefix before the return.
305 static void peephole_ia32_Return(ir_node *node) {
306 ir_node *block, *irn;
308 if (!ia32_cg_config.use_pad_return)
311 block = get_nodes_block(node);
313 if (get_Block_n_cfgpreds(block) == 1) {
314 ir_node *pred = get_Block_cfgpred(block, 0);
317 /* The block of the return has only one predecessor,
318 which jumps directly to this block.
319 This jump will be encoded as a fall through, so we
321 However, the predecessor might be empty, so it must be
322 ensured that empty blocks are gone away ... */
327 /* check if this return is the first on the block */
328 sched_foreach_reverse_from(node, irn) {
329 switch (be_get_irn_opcode(irn)) {
331 /* the return node itself, ignore */
334 /* ignore the barrier, no code generated */
337 /* arg, IncSP 0 nodes might occur, ignore these */
338 if (be_get_IncSP_offset(irn) == 0)
347 /* yep, return is the first real instruction in this block */
350 /* add an rep prefix to the return */
351 ir_node *rep = new_rd_ia32_RepPrefix(get_irn_dbg_info(node), current_ir_graph, block);
353 sched_add_before(node, rep);
356 /* ensure, that the 3 byte return is generated */
357 be_Return_set_emit_pop(node, 1);
361 /* only optimize up to 48 stores behind IncSPs */
362 #define MAXPUSH_OPTIMIZE 48
365 * Tries to create pushs from IncSP,Store combinations.
366 * The Stores are replaced by Push's, the IncSP is modified
367 * (possibly into IncSP 0, but not removed).
369 static void peephole_IncSP_Store_to_push(ir_node *irn)
374 ir_node *stores[MAXPUSH_OPTIMIZE];
375 ir_node *block = get_nodes_block(irn);
376 ir_graph *irg = cg->irg;
378 ir_mode *spmode = get_irn_mode(irn);
380 memset(stores, 0, sizeof(stores));
382 assert(be_is_IncSP(irn));
384 offset = be_get_IncSP_offset(irn);
389 * We first walk the schedule after the IncSP node as long as we find
390 * suitable stores that could be transformed to a push.
391 * We save them into the stores array which is sorted by the frame offset/4
392 * attached to the node
394 for(node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
399 // it has to be a store
400 if(!is_ia32_Store(node))
403 // it has to use our sp value
404 if(get_irn_n(node, n_ia32_base) != irn)
406 // store has to be attached to NoMem
407 mem = get_irn_n(node, n_ia32_mem);
412 /* unfortunately we can't support the full AMs possible for push at the
413 * moment. TODO: fix this */
414 if(get_ia32_am_scale(node) > 0 || !is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
417 offset = get_ia32_am_offs_int(node);
419 storeslot = offset / 4;
420 if(storeslot >= MAXPUSH_OPTIMIZE)
423 // storing into the same slot twice is bad (and shouldn't happen...)
424 if(stores[storeslot] != NULL)
427 // storing at half-slots is bad
431 stores[storeslot] = node;
434 curr_sp = be_get_IncSP_pred(irn);
436 // walk the stores in inverse order and create pushs for them
437 i = (offset / 4) - 1;
438 if(i >= MAXPUSH_OPTIMIZE) {
439 i = MAXPUSH_OPTIMIZE - 1;
442 for( ; i >= 0; --i) {
443 const arch_register_t *spreg;
445 ir_node *val, *mem, *mem_proj;
446 ir_node *store = stores[i];
447 ir_node *noreg = ia32_new_NoReg_gp(cg);
449 if(store == NULL || is_Bad(store))
452 val = get_irn_n(store, n_ia32_unary_op);
453 mem = get_irn_n(store, n_ia32_mem);
454 spreg = arch_get_irn_register(cg->arch_env, curr_sp);
456 push = new_rd_ia32_Push(get_irn_dbg_info(store), irg, block, noreg, noreg, mem, val, curr_sp);
458 sched_add_before(irn, push);
460 // create stackpointer proj
461 curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack);
462 arch_set_irn_register(cg->arch_env, curr_sp, spreg);
464 // create memory proj
465 mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
467 // use the memproj now
468 exchange(store, mem_proj);
470 // we can remove the store now
476 be_set_IncSP_offset(irn, offset);
477 be_set_IncSP_pred(irn, curr_sp);
481 * Tries to optimize two following IncSP.
483 static void peephole_IncSP_IncSP(ir_node *node)
488 ir_node *pred = be_get_IncSP_pred(node);
491 if(!be_is_IncSP(pred))
494 if(get_irn_n_edges(pred) > 1)
497 pred_offs = be_get_IncSP_offset(pred);
498 curr_offs = be_get_IncSP_offset(node);
500 if(pred_offs == BE_STACK_FRAME_SIZE_EXPAND) {
501 if(curr_offs != BE_STACK_FRAME_SIZE_SHRINK) {
505 } else if(pred_offs == BE_STACK_FRAME_SIZE_SHRINK) {
506 if(curr_offs != BE_STACK_FRAME_SIZE_EXPAND) {
510 } else if(curr_offs == BE_STACK_FRAME_SIZE_EXPAND
511 || curr_offs == BE_STACK_FRAME_SIZE_SHRINK) {
514 offs = curr_offs + pred_offs;
517 /* add pred offset to ours and remove pred IncSP */
518 be_set_IncSP_offset(node, offs);
520 predpred = be_get_IncSP_pred(pred);
521 be_peephole_before_exchange(pred, predpred);
523 /* rewire dependency edges */
524 edges_reroute_kind(pred, predpred, EDGE_KIND_DEP, current_ir_graph);
525 be_set_IncSP_pred(node, predpred);
529 be_peephole_after_exchange(predpred);
533 * Find a free GP register if possible, else return NULL.
535 static const arch_register_t *get_free_gp_reg(void)
539 for(i = 0; i < N_ia32_gp_REGS; ++i) {
540 const arch_register_t *reg = &ia32_gp_regs[i];
541 if(arch_register_type_is(reg, ignore))
544 if(be_peephole_get_value(CLASS_ia32_gp, i) == NULL)
545 return &ia32_gp_regs[i];
551 static void peephole_be_IncSP(ir_node *node)
553 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
554 const arch_register_t *reg;
564 /* first optimize incsp->incsp combinations */
565 peephole_IncSP_IncSP(node);
567 /* transform IncSP->Store combinations to Push where possible */
568 peephole_IncSP_Store_to_push(node);
570 if (arch_get_irn_register(arch_env, node) != esp)
573 /* replace IncSP -4 by Pop freereg when possible */
574 offset = be_get_IncSP_offset(node);
575 if ((offset != -8 || !ia32_cg_config.use_add_esp_8) &&
576 (offset != -4 || !ia32_cg_config.use_add_esp_4) &&
577 (offset != +4 || !ia32_cg_config.use_sub_esp_4) &&
578 (offset != +8 || !ia32_cg_config.use_sub_esp_8))
582 /* we need a free register for pop */
583 reg = get_free_gp_reg();
587 irg = current_ir_graph;
588 dbgi = get_irn_dbg_info(node);
589 block = get_nodes_block(node);
590 stack = be_get_IncSP_pred(node);
591 pop = new_rd_ia32_Pop(dbgi, irg, block, new_NoMem(), stack);
593 stack = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
594 arch_set_irn_register(arch_env, stack, esp);
595 val = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_res);
596 arch_set_irn_register(arch_env, val, reg);
598 sched_add_before(node, pop);
600 keep = sched_next(node);
601 if (!be_is_Keep(keep)) {
604 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
605 sched_add_before(node, keep);
607 be_Keep_add_node(keep, &ia32_reg_classes[CLASS_ia32_gp], val);
611 pop2 = new_rd_ia32_Pop(dbgi, irg, block, new_NoMem(), stack);
613 stack = new_r_Proj(irg, block, pop2, mode_Iu, pn_ia32_Pop_stack);
614 arch_set_irn_register(arch_env, stack, esp);
615 val = new_r_Proj(irg, block, pop2, mode_Iu, pn_ia32_Pop_res);
616 arch_set_irn_register(arch_env, val, reg);
618 sched_add_after(pop, pop2);
619 be_Keep_add_node(keep, &ia32_reg_classes[CLASS_ia32_gp], val);
626 be_peephole_before_exchange(node, stack);
628 exchange(node, stack);
629 be_peephole_after_exchange(stack);
633 * Peephole optimisation for ia32_Const's
635 static void peephole_ia32_Const(ir_node *node)
637 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
638 const arch_register_t *reg;
639 ir_graph *irg = current_ir_graph;
646 /* try to transform a mov 0, reg to xor reg reg */
647 if (attr->offset != 0 || attr->symconst != NULL)
649 if (ia32_cg_config.use_mov_0)
651 /* xor destroys the flags, so no-one must be using them */
652 if (be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
655 reg = arch_get_irn_register(arch_env, node);
656 assert(be_peephole_get_reg_value(reg) == NULL);
658 /* create xor(produceval, produceval) */
659 block = get_nodes_block(node);
660 dbgi = get_irn_dbg_info(node);
661 produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
662 arch_set_irn_register(arch_env, produceval, reg);
664 noreg = ia32_new_NoReg_gp(cg);
665 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_NoMem(),
666 produceval, produceval);
667 arch_set_irn_register(arch_env, xor, reg);
669 sched_add_before(node, produceval);
670 sched_add_before(node, xor);
672 be_peephole_before_exchange(node, xor);
675 be_peephole_after_exchange(xor);
678 static INLINE int is_noreg(ia32_code_gen_t *cg, const ir_node *node)
680 return node == cg->noreg_gp;
683 static ir_node *create_immediate_from_int(ia32_code_gen_t *cg, int val)
685 ir_graph *irg = current_ir_graph;
686 ir_node *start_block = get_irg_start_block(irg);
687 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL,
689 arch_set_irn_register(cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
694 static ir_node *create_immediate_from_am(ia32_code_gen_t *cg,
697 ir_graph *irg = get_irn_irg(node);
698 ir_node *block = get_nodes_block(node);
699 int offset = get_ia32_am_offs_int(node);
700 int sc_sign = is_ia32_am_sc_sign(node);
701 ir_entity *entity = get_ia32_am_sc(node);
704 res = new_rd_ia32_Immediate(NULL, irg, block, entity, sc_sign, offset);
705 arch_set_irn_register(cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
709 static int is_am_one(const ir_node *node)
711 int offset = get_ia32_am_offs_int(node);
712 ir_entity *entity = get_ia32_am_sc(node);
714 return offset == 1 && entity == NULL;
717 static int is_am_minus_one(const ir_node *node)
719 int offset = get_ia32_am_offs_int(node);
720 ir_entity *entity = get_ia32_am_sc(node);
722 return offset == -1 && entity == NULL;
726 * Transforms a LEA into an Add or SHL if possible.
728 static void peephole_ia32_Lea(ir_node *node)
730 const arch_env_t *arch_env = cg->arch_env;
731 ir_graph *irg = current_ir_graph;
734 const arch_register_t *base_reg;
735 const arch_register_t *index_reg;
736 const arch_register_t *out_reg;
747 assert(is_ia32_Lea(node));
749 /* we can only do this if are allowed to globber the flags */
750 if(be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
753 base = get_irn_n(node, n_ia32_Lea_base);
754 index = get_irn_n(node, n_ia32_Lea_index);
756 if(is_noreg(cg, base)) {
760 base_reg = arch_get_irn_register(arch_env, base);
762 if(is_noreg(cg, index)) {
766 index_reg = arch_get_irn_register(arch_env, index);
769 if(base == NULL && index == NULL) {
770 /* we shouldn't construct these in the first place... */
772 ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
777 out_reg = arch_get_irn_register(arch_env, node);
778 scale = get_ia32_am_scale(node);
779 assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
780 /* check if we have immediates values (frame entities should already be
781 * expressed in the offsets) */
782 if(get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
788 /* we can transform leas where the out register is the same as either the
789 * base or index register back to an Add or Shl */
790 if(out_reg == base_reg) {
793 if(!has_immediates) {
794 ir_fprintf(stderr, "Optimisation warning: found lea which is "
799 goto make_add_immediate;
801 if(scale == 0 && !has_immediates) {
806 /* can't create an add */
808 } else if(out_reg == index_reg) {
810 if(has_immediates && scale == 0) {
812 goto make_add_immediate;
813 } else if(!has_immediates && scale > 0) {
815 op2 = create_immediate_from_int(cg, scale);
817 } else if(!has_immediates) {
819 ir_fprintf(stderr, "Optimisation warning: found lea which is "
823 } else if(scale == 0 && !has_immediates) {
828 /* can't create an add */
831 /* can't create an add */
836 if(ia32_cg_config.use_incdec) {
837 if(is_am_one(node)) {
838 dbgi = get_irn_dbg_info(node);
839 block = get_nodes_block(node);
840 res = new_rd_ia32_Inc(dbgi, irg, block, op1);
841 arch_set_irn_register(arch_env, res, out_reg);
844 if(is_am_minus_one(node)) {
845 dbgi = get_irn_dbg_info(node);
846 block = get_nodes_block(node);
847 res = new_rd_ia32_Dec(dbgi, irg, block, op1);
848 arch_set_irn_register(arch_env, res, out_reg);
852 op2 = create_immediate_from_am(cg, node);
855 dbgi = get_irn_dbg_info(node);
856 block = get_nodes_block(node);
857 noreg = ia32_new_NoReg_gp(cg);
859 res = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, nomem, op1, op2);
860 arch_set_irn_register(arch_env, res, out_reg);
861 set_ia32_commutative(res);
865 dbgi = get_irn_dbg_info(node);
866 block = get_nodes_block(node);
867 noreg = ia32_new_NoReg_gp(cg);
869 res = new_rd_ia32_Shl(dbgi, irg, block, op1, op2);
870 arch_set_irn_register(arch_env, res, out_reg);
874 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, node));
876 /* add new ADD/SHL to schedule */
877 DBG_OPT_LEA2ADD(node, res);
879 /* exchange the Add and the LEA */
880 be_peephole_before_exchange(node, res);
881 sched_add_before(node, res);
884 be_peephole_after_exchange(res);
888 * Split a Imul mem, imm into a Load mem and Imul reg, imm if possible.
890 static void peephole_ia32_Imul_split(ir_node *imul) {
891 const ir_node *right = get_irn_n(imul, n_ia32_IMul_right);
892 const arch_register_t *reg;
893 ir_node *load, *block, *base, *index, *mem, *res, *noreg;
897 if (! is_ia32_Immediate(right) || get_ia32_op_type(imul) != ia32_AddrModeS) {
898 /* no memory, imm form ignore */
901 /* we need a free register */
902 reg = get_free_gp_reg();
906 /* fine, we can rebuild it */
907 dbgi = get_irn_dbg_info(imul);
908 block = get_nodes_block(imul);
909 irg = current_ir_graph;
910 base = get_irn_n(imul, n_ia32_IMul_base);
911 index = get_irn_n(imul, n_ia32_IMul_index);
912 mem = get_irn_n(imul, n_ia32_IMul_mem);
913 load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
915 /* copy all attributes */
916 set_irn_pinned(load, get_irn_pinned(imul));
917 set_ia32_op_type(load, ia32_AddrModeS);
918 set_ia32_ls_mode(load, get_ia32_ls_mode(imul));
920 set_ia32_am_scale(load, get_ia32_am_scale(imul));
921 set_ia32_am_sc(load, get_ia32_am_sc(imul));
922 set_ia32_am_offs_int(load, get_ia32_am_offs_int(imul));
923 if (is_ia32_am_sc_sign(imul))
924 set_ia32_am_sc_sign(load);
925 if (is_ia32_use_frame(imul))
926 set_ia32_use_frame(load);
927 set_ia32_frame_ent(load, get_ia32_frame_ent(imul));
929 sched_add_before(imul, load);
931 mem = new_rd_Proj(dbgi, irg, block, load, mode_M, pn_ia32_Load_M);
932 res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
934 arch_set_irn_register(arch_env, res, reg);
935 be_peephole_after_exchange(res);
937 set_irn_n(imul, n_ia32_IMul_mem, mem);
938 noreg = get_irn_n(imul, n_ia32_IMul_left);
939 set_irn_n(imul, n_ia32_IMul_left, res);
940 set_ia32_op_type(imul, ia32_Normal);
944 * Replace xorps r,r and xorpd r,r by pxor r,r
946 static void peephole_ia32_xZero(ir_node *xor) {
947 set_irn_op(xor, op_ia32_xPzero);
951 * Register a peephole optimisation function.
953 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func) {
954 assert(op->ops.generic == NULL);
955 op->ops.generic = (op_func)func;
958 /* Perform peephole-optimizations. */
959 void ia32_peephole_optimization(ia32_code_gen_t *new_cg)
962 arch_env = cg->arch_env;
964 /* register peephole optimisations */
965 clear_irp_opcodes_generic_func();
966 register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
967 //register_peephole_optimisation(op_ia32_Store, peephole_ia32_Store);
968 register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
969 register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
970 register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
971 register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test);
972 register_peephole_optimisation(op_be_Return, peephole_ia32_Return);
973 if (! ia32_cg_config.use_imul_mem_imm32)
974 register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split);
975 if (ia32_cg_config.use_pxor)
976 register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero);
978 be_peephole_opt(cg->birg);
982 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
983 * all it's Projs are removed as well.
984 * @param irn The irn to be removed from schedule
986 static INLINE void try_kill(ir_node *node)
988 if(get_irn_mode(node) == mode_T) {
989 const ir_edge_t *edge, *next;
990 foreach_out_edge_safe(node, edge, next) {
991 ir_node *proj = get_edge_src_irn(edge);
996 if(get_irn_n_edges(node) != 0)
999 if (sched_is_scheduled(node)) {
1006 static void optimize_conv_store(ir_node *node)
1011 ir_mode *store_mode;
1013 if(!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
1016 assert(n_ia32_Store_val == n_ia32_Store8Bit_val);
1017 pred_proj = get_irn_n(node, n_ia32_Store_val);
1018 if(is_Proj(pred_proj)) {
1019 pred = get_Proj_pred(pred_proj);
1023 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1025 if(get_ia32_op_type(pred) != ia32_Normal)
1028 /* the store only stores the lower bits, so we only need the conv
1029 * it it shrinks the mode */
1030 conv_mode = get_ia32_ls_mode(pred);
1031 store_mode = get_ia32_ls_mode(node);
1032 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
1035 set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val));
1036 if(get_irn_n_edges(pred_proj) == 0) {
1037 be_kill_node(pred_proj);
1038 if(pred != pred_proj)
1043 static void optimize_load_conv(ir_node *node)
1045 ir_node *pred, *predpred;
1049 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1052 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1053 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
1057 predpred = get_Proj_pred(pred);
1058 if(!is_ia32_Load(predpred))
1061 /* the load is sign extending the upper bits, so we only need the conv
1062 * if it shrinks the mode */
1063 load_mode = get_ia32_ls_mode(predpred);
1064 conv_mode = get_ia32_ls_mode(node);
1065 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
1068 if(get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
1069 /* change the load if it has only 1 user */
1070 if(get_irn_n_edges(pred) == 1) {
1072 if(get_mode_sign(conv_mode)) {
1073 newmode = find_signed_mode(load_mode);
1075 newmode = find_unsigned_mode(load_mode);
1077 assert(newmode != NULL);
1078 set_ia32_ls_mode(predpred, newmode);
1080 /* otherwise we have to keep the conv */
1086 exchange(node, pred);
1089 static void optimize_conv_conv(ir_node *node)
1091 ir_node *pred_proj, *pred, *result_conv;
1092 ir_mode *pred_mode, *conv_mode;
1096 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1099 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1100 pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
1101 if(is_Proj(pred_proj))
1102 pred = get_Proj_pred(pred_proj);
1106 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1109 /* we know that after a conv, the upper bits are sign extended
1110 * so we only need the 2nd conv if it shrinks the mode */
1111 conv_mode = get_ia32_ls_mode(node);
1112 conv_mode_bits = get_mode_size_bits(conv_mode);
1113 pred_mode = get_ia32_ls_mode(pred);
1114 pred_mode_bits = get_mode_size_bits(pred_mode);
1116 if(conv_mode_bits == pred_mode_bits
1117 && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1118 result_conv = pred_proj;
1119 } else if(conv_mode_bits <= pred_mode_bits) {
1120 /* if 2nd conv is smaller then first conv, then we can always take the
1122 if(get_irn_n_edges(pred_proj) == 1) {
1123 result_conv = pred_proj;
1124 set_ia32_ls_mode(pred, conv_mode);
1126 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1127 if (get_mode_size_bits(conv_mode) == 8) {
1128 set_irn_op(pred, op_ia32_Conv_I2I8Bit);
1129 set_ia32_in_req_all(pred, get_ia32_in_req_all(node));
1132 /* we don't want to end up with 2 loads, so we better do nothing */
1133 if(get_irn_mode(pred) == mode_T) {
1137 result_conv = exact_copy(pred);
1138 set_ia32_ls_mode(result_conv, conv_mode);
1140 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1141 if (get_mode_size_bits(conv_mode) == 8) {
1142 set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
1143 set_ia32_in_req_all(result_conv, get_ia32_in_req_all(node));
1147 /* if both convs have the same sign, then we can take the smaller one */
1148 if(get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1149 result_conv = pred_proj;
1151 /* no optimisation possible if smaller conv is sign-extend */
1152 if(mode_is_signed(pred_mode)) {
1155 /* we can take the smaller conv if it is unsigned */
1156 result_conv = pred_proj;
1161 exchange(node, result_conv);
1163 if(get_irn_n_edges(pred_proj) == 0) {
1164 be_kill_node(pred_proj);
1165 if(pred != pred_proj)
1168 optimize_conv_conv(result_conv);
1171 static void optimize_node(ir_node *node, void *env)
1175 optimize_load_conv(node);
1176 optimize_conv_store(node);
1177 optimize_conv_conv(node);
1181 * Performs conv and address mode optimization.
1183 void ia32_optimize_graph(ia32_code_gen_t *cg)
1185 irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg);
1188 be_dump(cg->irg, "-opt", dump_ir_block_graph_sched);
1191 void ia32_init_optimize(void)
1193 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");