2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Matthias Braun, Christian Wuerdig
32 #include "firm_types.h"
47 #include "bepeephole.h"
49 #include "ia32_new_nodes.h"
50 #include "ia32_optimize.h"
51 #include "bearch_ia32_t.h"
52 #include "gen_ia32_regalloc_if.h"
53 #include "ia32_common_transform.h"
54 #include "ia32_transform.h"
55 #include "ia32_dbg_stat.h"
56 #include "ia32_architecture.h"
58 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
60 static void copy_mark(const ir_node *old, ir_node *newn)
62 if (is_ia32_is_reload(old))
63 set_ia32_is_reload(newn);
64 if (is_ia32_is_spill(old))
65 set_ia32_is_spill(newn);
66 if (is_ia32_is_remat(old))
67 set_ia32_is_remat(newn);
70 typedef enum produces_flag_t {
73 produces_zero_in_carry
77 * Return which usable flag the given node produces about the result.
78 * That is zero (ZF) and sign(SF).
79 * We do not check for carry (CF) or overflow (OF).
81 * @param node the node to check
82 * @param pn the projection number of the used result
84 static produces_flag_t check_produces_zero_sign(ir_node *node, int pn)
87 const ia32_immediate_attr_t *imm_attr;
89 if (!is_ia32_irn(node))
90 return produces_no_flag;
92 switch (get_ia32_irn_opcode(node)) {
107 assert((int)n_ia32_ShlD_count == (int)n_ia32_ShrD_count);
108 count = get_irn_n(node, n_ia32_ShlD_count);
109 goto check_shift_amount;
114 assert((int)n_ia32_Shl_count == (int)n_ia32_Shr_count
115 && (int)n_ia32_Shl_count == (int)n_ia32_Sar_count);
116 count = get_irn_n(node, n_ia32_Shl_count);
118 /* when shift count is zero the flags are not affected, so we can only
119 * do this for constants != 0 */
120 if (!is_ia32_Immediate(count))
121 return produces_no_flag;
123 imm_attr = get_ia32_immediate_attr_const(count);
124 if (imm_attr->symconst != NULL)
125 return produces_no_flag;
126 if ((imm_attr->offset & 0x1f) == 0)
127 return produces_no_flag;
131 return pn == pn_ia32_Mul_res_high ?
132 produces_zero_in_carry : produces_no_flag;
135 return produces_no_flag;
138 return pn == pn_ia32_res ? produces_zero_sign : produces_no_flag;
142 * Replace Cmp(x, 0) by a Test(x, x)
144 static void peephole_ia32_Cmp(ir_node *const node)
148 ia32_immediate_attr_t const *imm;
154 ia32_attr_t const *attr;
157 arch_register_t const *reg;
158 ir_edge_t const *edge;
159 ir_edge_t const *tmp;
161 if (get_ia32_op_type(node) != ia32_Normal)
164 right = get_irn_n(node, n_ia32_Cmp_right);
165 if (!is_ia32_Immediate(right))
168 imm = get_ia32_immediate_attr_const(right);
169 if (imm->symconst != NULL || imm->offset != 0)
172 dbgi = get_irn_dbg_info(node);
173 irg = get_irn_irg(node);
174 block = get_nodes_block(node);
175 noreg = ia32_new_NoReg_gp(irg);
176 nomem = get_irg_no_mem(current_ir_graph);
177 op = get_irn_n(node, n_ia32_Cmp_left);
178 attr = get_ia32_attr(node);
179 ins_permuted = attr->data.ins_permuted;
181 if (is_ia32_Cmp(node)) {
182 test = new_bd_ia32_Test(dbgi, block, noreg, noreg, nomem,
183 op, op, ins_permuted);
185 test = new_bd_ia32_Test8Bit(dbgi, block, noreg, noreg, nomem,
186 op, op, ins_permuted);
188 set_ia32_ls_mode(test, get_ia32_ls_mode(node));
190 reg = arch_get_irn_register_out(node, pn_ia32_Cmp_eflags);
191 arch_set_irn_register_out(test, pn_ia32_Test_eflags, reg);
193 foreach_out_edge_safe(node, edge, tmp) {
194 ir_node *const user = get_edge_src_irn(edge);
197 exchange(user, test);
200 sched_add_before(node, test);
201 copy_mark(node, test);
202 be_peephole_exchange(node, test);
206 * Peephole optimization for Test instructions.
207 * - Remove the Test, if an appropriate flag was produced which is still live
208 * - Change a Test(x, c) to 8Bit, if 0 <= c < 256 (3 byte shorter opcode)
210 static void peephole_ia32_Test(ir_node *node)
212 ir_node *left = get_irn_n(node, n_ia32_Test_left);
213 ir_node *right = get_irn_n(node, n_ia32_Test_right);
215 assert((int)n_ia32_Test_left == (int)n_ia32_Test8Bit_left
216 && (int)n_ia32_Test_right == (int)n_ia32_Test8Bit_right);
218 if (left == right) { /* we need a test for 0 */
219 ir_node *block = get_nodes_block(node);
220 int pn = pn_ia32_res;
226 const ir_edge_t *edge;
227 produces_flag_t produced;
229 if (get_nodes_block(left) != block)
233 pn = get_Proj_proj(op);
234 op = get_Proj_pred(op);
237 /* walk schedule up and abort when we find left or some other node
238 * destroys the flags */
241 schedpoint = sched_prev(schedpoint);
242 if (schedpoint == op)
244 if (arch_irn_is(schedpoint, modify_flags))
246 if (schedpoint == block)
247 panic("couldn't find left");
250 produced = check_produces_zero_sign(op, pn);
251 if (produced == produces_no_flag)
254 /* make sure users only look at the sign/zero flag */
255 foreach_out_edge(node, edge) {
256 ir_node *user = get_edge_src_irn(edge);
257 ia32_condition_code_t cc = get_ia32_condcode(user);
259 if (cc == ia32_cc_equal || cc == ia32_cc_not_equal)
261 if (produced == produces_zero_sign
262 && (cc == ia32_cc_sign || cc == ia32_cc_not_sign)) {
268 op_mode = get_ia32_ls_mode(op);
270 op_mode = get_irn_mode(op);
272 /* Make sure we operate on the same bit size */
273 if (get_mode_size_bits(op_mode) != get_mode_size_bits(get_ia32_ls_mode(node)))
276 if (produced == produces_zero_in_carry) {
277 /* patch users to look at the carry instead of the zero flag */
278 foreach_out_edge(node, edge) {
279 ir_node *user = get_edge_src_irn(edge);
280 ia32_condition_code_t cc = get_ia32_condcode(user);
283 case ia32_cc_equal: cc = ia32_cc_above_equal; break;
284 case ia32_cc_not_equal: cc = ia32_cc_below; break;
285 default: panic("unexpected pn");
287 set_ia32_condcode(user, cc);
291 if (get_irn_mode(op) != mode_T) {
292 set_irn_mode(op, mode_T);
294 /* If there are other users, reroute them to result proj */
295 if (get_irn_n_edges(op) != 2) {
296 ir_node *res = new_r_Proj(op, mode_Iu, pn_ia32_res);
298 edges_reroute(op, res);
299 /* Reattach the result proj to left */
300 set_Proj_pred(res, op);
303 if (get_irn_n_edges(left) == 2)
307 flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
308 flags_proj = new_r_Proj(op, flags_mode, pn_ia32_flags);
309 arch_set_irn_register(flags_proj, &ia32_registers[REG_EFLAGS]);
311 assert(get_irn_mode(node) != mode_T);
313 be_peephole_exchange(node, flags_proj);
314 } else if (is_ia32_Immediate(right)) {
315 ia32_immediate_attr_t const *const imm = get_ia32_immediate_attr_const(right);
318 /* A test with a symconst is rather strange, but better safe than sorry */
319 if (imm->symconst != NULL)
322 offset = imm->offset;
323 if (get_ia32_op_type(node) == ia32_AddrModeS) {
324 ia32_attr_t *const attr = get_ia32_attr(node);
326 if ((offset & 0xFFFFFF00) == 0) {
327 /* attr->am_offs += 0; */
328 } else if ((offset & 0xFFFF00FF) == 0) {
329 ir_node *imm_node = ia32_create_Immediate(NULL, 0, offset>>8);
330 set_irn_n(node, n_ia32_Test_right, imm_node);
332 } else if ((offset & 0xFF00FFFF) == 0) {
333 ir_node *imm_node = ia32_create_Immediate(NULL, 0, offset>>16);
334 set_irn_n(node, n_ia32_Test_right, imm_node);
336 } else if ((offset & 0x00FFFFFF) == 0) {
337 ir_node *imm_node = ia32_create_Immediate(NULL, 0, offset>>24);
338 set_irn_n(node, n_ia32_Test_right, imm_node);
343 } else if (offset < 256) {
344 arch_register_t const* const reg = arch_get_irn_register(left);
346 if (reg != &ia32_registers[REG_EAX] &&
347 reg != &ia32_registers[REG_EBX] &&
348 reg != &ia32_registers[REG_ECX] &&
349 reg != &ia32_registers[REG_EDX]) {
356 /* Technically we should build a Test8Bit because of the register
357 * constraints, but nobody changes registers at this point anymore. */
358 set_ia32_ls_mode(node, mode_Bu);
363 * AMD Athlon works faster when RET is not destination of
364 * conditional jump or directly preceded by other jump instruction.
365 * Can be avoided by placing a Rep prefix before the return.
367 static void peephole_ia32_Return(ir_node *node)
371 if (!ia32_cg_config.use_pad_return)
374 /* check if this return is the first on the block */
375 sched_foreach_reverse_from(node, irn) {
376 switch (get_irn_opcode(irn)) {
378 /* the return node itself, ignore */
382 /* ignore no code generated */
385 /* arg, IncSP 0 nodes might occur, ignore these */
386 if (be_get_IncSP_offset(irn) == 0)
396 /* ensure, that the 3 byte return is generated */
397 be_Return_set_emit_pop(node, 1);
400 /* only optimize up to 48 stores behind IncSPs */
401 #define MAXPUSH_OPTIMIZE 48
404 * Tries to create Push's from IncSP, Store combinations.
405 * The Stores are replaced by Push's, the IncSP is modified
406 * (possibly into IncSP 0, but not removed).
408 static void peephole_IncSP_Store_to_push(ir_node *irn)
414 ir_node *stores[MAXPUSH_OPTIMIZE];
419 ir_node *first_push = NULL;
420 ir_edge_t const *edge;
421 ir_edge_t const *next;
423 memset(stores, 0, sizeof(stores));
425 assert(be_is_IncSP(irn));
427 inc_ofs = be_get_IncSP_offset(irn);
432 * We first walk the schedule after the IncSP node as long as we find
433 * suitable Stores that could be transformed to a Push.
434 * We save them into the stores array which is sorted by the frame offset/4
435 * attached to the node
438 for (node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
443 /* it has to be a Store */
444 if (!is_ia32_Store(node))
447 /* it has to use our sp value */
448 if (get_irn_n(node, n_ia32_base) != irn)
450 /* Store has to be attached to NoMem */
451 mem = get_irn_n(node, n_ia32_mem);
455 /* unfortunately we can't support the full AMs possible for push at the
456 * moment. TODO: fix this */
457 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
460 offset = get_ia32_am_offs_int(node);
461 /* we should NEVER access uninitialized stack BELOW the current SP */
464 /* storing at half-slots is bad */
465 if ((offset & 3) != 0)
468 if (inc_ofs - 4 < offset || offset >= MAXPUSH_OPTIMIZE * 4)
470 storeslot = offset >> 2;
472 /* storing into the same slot twice is bad (and shouldn't happen...) */
473 if (stores[storeslot] != NULL)
476 stores[storeslot] = node;
477 if (storeslot > maxslot)
483 for (i = -1; i < maxslot; ++i) {
484 if (stores[i + 1] == NULL)
488 /* walk through the Stores and create Pushs for them */
489 block = get_nodes_block(irn);
490 spmode = get_irn_mode(irn);
491 irg = get_irn_irg(irn);
492 for (; i >= 0; --i) {
493 const arch_register_t *spreg;
495 ir_node *val, *mem, *mem_proj;
496 ir_node *store = stores[i];
497 ir_node *noreg = ia32_new_NoReg_gp(irg);
499 val = get_irn_n(store, n_ia32_unary_op);
500 mem = get_irn_n(store, n_ia32_mem);
501 spreg = arch_get_irn_register(curr_sp);
503 push = new_bd_ia32_Push(get_irn_dbg_info(store), block, noreg, noreg,
505 copy_mark(store, push);
507 if (first_push == NULL)
510 sched_add_after(skip_Proj(curr_sp), push);
512 /* create stackpointer Proj */
513 curr_sp = new_r_Proj(push, spmode, pn_ia32_Push_stack);
514 arch_set_irn_register(curr_sp, spreg);
516 /* create memory Proj */
517 mem_proj = new_r_Proj(push, mode_M, pn_ia32_Push_M);
519 /* rewire Store Projs */
520 foreach_out_edge_safe(store, edge, next) {
521 ir_node *proj = get_edge_src_irn(edge);
524 switch (get_Proj_proj(proj)) {
525 case pn_ia32_Store_M:
526 exchange(proj, mem_proj);
529 panic("unexpected Proj on Store->IncSp");
533 /* use the memproj now */
534 be_peephole_exchange(store, push);
539 foreach_out_edge_safe(irn, edge, next) {
540 ir_node *const src = get_edge_src_irn(edge);
541 int const pos = get_edge_src_pos(edge);
543 if (src == first_push)
546 set_irn_n(src, pos, curr_sp);
549 be_set_IncSP_offset(irn, inc_ofs);
554 * Creates a Push instruction before the given schedule point.
556 * @param dbgi debug info
557 * @param block the block
558 * @param stack the previous stack value
559 * @param schedpoint the new node is added before this node
560 * @param reg the register to pop
562 * @return the new stack value
564 static ir_node *create_push(dbg_info *dbgi, ir_node *block,
565 ir_node *stack, ir_node *schedpoint)
567 const arch_register_t *esp = &ia32_registers[REG_ESP];
569 ir_node *val = ia32_new_NoReg_gp(cg);
570 ir_node *noreg = ia32_new_NoReg_gp(cg);
571 ir_graph *irg = get_irn_irg(block);
572 ir_node *nomem = get_irg_no_mem(irg);
573 ir_node *push = new_bd_ia32_Push(dbgi, block, noreg, noreg, nomem, val, stack);
574 sched_add_before(schedpoint, push);
576 stack = new_r_Proj(push, mode_Iu, pn_ia32_Push_stack);
577 arch_set_irn_register(stack, esp);
582 static void peephole_store_incsp(ir_node *store)
593 ir_node *am_base = get_irn_n(store, n_ia32_Store_base);
594 if (!be_is_IncSP(am_base)
595 || get_nodes_block(am_base) != get_nodes_block(store))
597 mem = get_irn_n(store, n_ia32_Store_mem);
598 if (!is_ia32_NoReg_GP(get_irn_n(store, n_ia32_Store_index))
602 int incsp_offset = be_get_IncSP_offset(am_base);
603 if (incsp_offset <= 0)
606 /* we have to be at offset 0 */
607 int my_offset = get_ia32_am_offs_int(store);
608 if (my_offset != 0) {
609 /* TODO here: find out whether there is a store with offset 0 before
610 * us and whether we can move it down to our place */
613 ir_mode *ls_mode = get_ia32_ls_mode(store);
614 int my_store_size = get_mode_size_bytes(ls_mode);
616 if (my_offset + my_store_size > incsp_offset)
619 /* correctness checking:
620 - noone else must write to that stackslot
621 (because after translation incsp won't allocate it anymore)
623 sched_foreach_reverse_from(store, node) {
629 /* make sure noone else can use the space on the stack */
630 arity = get_irn_arity(node);
631 for (i = 0; i < arity; ++i) {
632 ir_node *pred = get_irn_n(node, i);
636 if (i == n_ia32_base &&
637 (get_ia32_op_type(node) == ia32_AddrModeS
638 || get_ia32_op_type(node) == ia32_AddrModeD)) {
639 int node_offset = get_ia32_am_offs_int(node);
640 ir_mode *node_ls_mode = get_ia32_ls_mode(node);
641 int node_size = get_mode_size_bytes(node_ls_mode);
642 /* overlapping with our position? abort */
643 if (node_offset < my_offset + my_store_size
644 && node_offset + node_size >= my_offset)
646 /* otherwise it's fine */
650 /* strange use of esp: abort */
655 /* all ok, change to push */
656 dbgi = get_irn_dbg_info(store);
657 block = get_nodes_block(store);
658 noreg = ia32_new_NoReg_gp(cg);
659 val = get_irn_n(store, n_ia32_Store_val);
661 push = new_bd_ia32_Push(dbgi, block, noreg, noreg, mem,
663 create_push(dbgi, current_ir_graph, block, am_base, store);
668 * Return true if a mode can be stored in the GP register set
670 static inline int mode_needs_gp_reg(ir_mode *mode)
672 if (mode == ia32_mode_fpcw)
674 if (get_mode_size_bits(mode) > 32)
676 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
680 * Tries to create Pops from Load, IncSP combinations.
681 * The Loads are replaced by Pops, the IncSP is modified
682 * (possibly into IncSP 0, but not removed).
684 static void peephole_Load_IncSP_to_pop(ir_node *irn)
686 const arch_register_t *esp = &ia32_registers[REG_ESP];
687 int i, maxslot, inc_ofs, ofs;
688 ir_node *node, *pred_sp, *block;
689 ir_node *loads[MAXPUSH_OPTIMIZE];
690 unsigned regmask = 0;
691 unsigned copymask = ~0;
693 memset(loads, 0, sizeof(loads));
694 assert(be_is_IncSP(irn));
696 inc_ofs = -be_get_IncSP_offset(irn);
701 * We first walk the schedule before the IncSP node as long as we find
702 * suitable Loads that could be transformed to a Pop.
703 * We save them into the stores array which is sorted by the frame offset/4
704 * attached to the node
707 pred_sp = be_get_IncSP_pred(irn);
708 for (node = sched_prev(irn); !sched_is_end(node); node = sched_prev(node)) {
711 const arch_register_t *sreg, *dreg;
713 /* it has to be a Load */
714 if (!is_ia32_Load(node)) {
715 if (be_is_Copy(node)) {
716 if (!mode_needs_gp_reg(get_irn_mode(node))) {
717 /* not a GP copy, ignore */
720 dreg = arch_get_irn_register(node);
721 sreg = arch_get_irn_register(be_get_Copy_op(node));
722 if (regmask & copymask & (1 << sreg->index)) {
725 if (regmask & copymask & (1 << dreg->index)) {
728 /* we CAN skip Copies if neither the destination nor the source
729 * is not in our regmask, ie none of our future Pop will overwrite it */
730 regmask |= (1 << dreg->index) | (1 << sreg->index);
731 copymask &= ~((1 << dreg->index) | (1 << sreg->index));
737 /* we can handle only GP loads */
738 if (!mode_needs_gp_reg(get_ia32_ls_mode(node)))
741 /* it has to use our predecessor sp value */
742 if (get_irn_n(node, n_ia32_base) != pred_sp) {
743 /* it would be ok if this load does not use a Pop result,
744 * but we do not check this */
748 /* should have NO index */
749 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
752 offset = get_ia32_am_offs_int(node);
753 /* we should NEVER access uninitialized stack BELOW the current SP */
756 /* storing at half-slots is bad */
757 if ((offset & 3) != 0)
760 if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
762 /* ignore those outside the possible windows */
763 if (offset > inc_ofs - 4)
765 loadslot = offset >> 2;
767 /* loading from the same slot twice is bad (and shouldn't happen...) */
768 if (loads[loadslot] != NULL)
771 dreg = arch_get_irn_register_out(node, pn_ia32_Load_res);
772 if (regmask & (1 << dreg->index)) {
773 /* this register is already used */
776 regmask |= 1 << dreg->index;
778 loads[loadslot] = node;
779 if (loadslot > maxslot)
786 /* find the first slot */
787 for (i = maxslot; i >= 0; --i) {
788 ir_node *load = loads[i];
794 ofs = inc_ofs - (maxslot + 1) * 4;
797 /* create a new IncSP if needed */
798 block = get_nodes_block(irn);
800 pred_sp = be_new_IncSP(esp, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
801 sched_add_before(irn, pred_sp);
804 /* walk through the Loads and create Pops for them */
805 for (++i; i <= maxslot; ++i) {
806 ir_node *load = loads[i];
808 const ir_edge_t *edge, *tmp;
809 const arch_register_t *reg;
811 mem = get_irn_n(load, n_ia32_mem);
812 reg = arch_get_irn_register_out(load, pn_ia32_Load_res);
814 pop = new_bd_ia32_Pop(get_irn_dbg_info(load), block, mem, pred_sp);
815 arch_set_irn_register_out(pop, pn_ia32_Load_res, reg);
817 copy_mark(load, pop);
819 /* create stackpointer Proj */
820 pred_sp = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack);
821 arch_set_irn_register(pred_sp, esp);
823 sched_add_before(irn, pop);
826 foreach_out_edge_safe(load, edge, tmp) {
827 ir_node *proj = get_edge_src_irn(edge);
829 set_Proj_pred(proj, pop);
832 /* we can remove the Load now */
837 be_set_IncSP_offset(irn, -ofs);
838 be_set_IncSP_pred(irn, pred_sp);
843 * Find a free GP register if possible, else return NULL.
845 static const arch_register_t *get_free_gp_reg(ir_graph *irg)
847 be_irg_t *birg = be_birg_from_irg(irg);
850 for (i = 0; i < N_ia32_gp_REGS; ++i) {
851 const arch_register_t *reg = &ia32_reg_classes[CLASS_ia32_gp].regs[i];
852 if (!rbitset_is_set(birg->allocatable_regs, reg->global_index))
855 if (be_peephole_get_value(reg->global_index) == NULL)
863 * Creates a Pop instruction before the given schedule point.
865 * @param dbgi debug info
866 * @param block the block
867 * @param stack the previous stack value
868 * @param schedpoint the new node is added before this node
869 * @param reg the register to pop
871 * @return the new stack value
873 static ir_node *create_pop(dbg_info *dbgi, ir_node *block,
874 ir_node *stack, ir_node *schedpoint,
875 const arch_register_t *reg)
877 const arch_register_t *esp = &ia32_registers[REG_ESP];
878 ir_graph *irg = get_irn_irg(block);
884 pop = new_bd_ia32_Pop(dbgi, block, get_irg_no_mem(irg), stack);
886 stack = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack);
887 arch_set_irn_register(stack, esp);
888 val = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_res);
889 arch_set_irn_register(val, reg);
891 sched_add_before(schedpoint, pop);
894 keep = be_new_Keep(block, 1, in);
895 sched_add_before(schedpoint, keep);
901 * Optimize an IncSp by replacing it with Push/Pop.
903 static void peephole_be_IncSP(ir_node *node)
905 const arch_register_t *esp = &ia32_registers[REG_ESP];
906 const arch_register_t *reg;
912 /* first optimize incsp->incsp combinations */
913 node = be_peephole_IncSP_IncSP(node);
915 /* transform IncSP->Store combinations to Push where possible */
916 peephole_IncSP_Store_to_push(node);
918 /* transform Load->IncSP combinations to Pop where possible */
919 peephole_Load_IncSP_to_pop(node);
921 if (arch_get_irn_register(node) != esp)
924 /* replace IncSP -4 by Pop freereg when possible */
925 offset = be_get_IncSP_offset(node);
926 if ((offset != -8 || ia32_cg_config.use_add_esp_8) &&
927 (offset != -4 || ia32_cg_config.use_add_esp_4) &&
928 (offset != +4 || ia32_cg_config.use_sub_esp_4) &&
929 (offset != +8 || ia32_cg_config.use_sub_esp_8))
933 /* we need a free register for pop */
934 reg = get_free_gp_reg(get_irn_irg(node));
938 dbgi = get_irn_dbg_info(node);
939 block = get_nodes_block(node);
940 stack = be_get_IncSP_pred(node);
942 stack = create_pop(dbgi, block, stack, node, reg);
945 stack = create_pop(dbgi, block, stack, node, reg);
948 dbgi = get_irn_dbg_info(node);
949 block = get_nodes_block(node);
950 stack = be_get_IncSP_pred(node);
951 stack = new_bd_ia32_PushEax(dbgi, block, stack);
952 arch_set_irn_register(stack, esp);
953 sched_add_before(node, stack);
956 stack = new_bd_ia32_PushEax(dbgi, block, stack);
957 arch_set_irn_register(stack, esp);
958 sched_add_before(node, stack);
962 be_peephole_exchange(node, stack);
966 * Peephole optimisation for ia32_Const's
968 static void peephole_ia32_Const(ir_node *node)
970 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
971 const arch_register_t *reg;
976 /* try to transform a mov 0, reg to xor reg reg */
977 if (attr->offset != 0 || attr->symconst != NULL)
979 if (ia32_cg_config.use_mov_0)
981 /* xor destroys the flags, so no-one must be using them */
982 if (be_peephole_get_value(REG_EFLAGS) != NULL)
985 reg = arch_get_irn_register(node);
986 assert(be_peephole_get_reg_value(reg) == NULL);
988 /* create xor(produceval, produceval) */
989 block = get_nodes_block(node);
990 dbgi = get_irn_dbg_info(node);
991 xorn = new_bd_ia32_Xor0(dbgi, block);
992 arch_set_irn_register(xorn, reg);
994 sched_add_before(node, xorn);
996 copy_mark(node, xorn);
997 be_peephole_exchange(node, xorn);
1000 static inline int is_noreg(const ir_node *node)
1002 return is_ia32_NoReg_GP(node);
1005 ir_node *ia32_immediate_from_long(long val)
1007 ir_graph *irg = current_ir_graph;
1008 ir_node *start_block = get_irg_start_block(irg);
1010 = new_bd_ia32_Immediate(NULL, start_block, NULL, 0, 0, val);
1011 arch_set_irn_register(immediate, &ia32_registers[REG_GP_NOREG]);
1016 static ir_node *create_immediate_from_am(const ir_node *node)
1018 ir_node *block = get_nodes_block(node);
1019 int offset = get_ia32_am_offs_int(node);
1020 int sc_sign = is_ia32_am_sc_sign(node);
1021 const ia32_attr_t *attr = get_ia32_attr_const(node);
1022 int sc_no_pic_adjust = attr->data.am_sc_no_pic_adjust;
1023 ir_entity *entity = get_ia32_am_sc(node);
1026 res = new_bd_ia32_Immediate(NULL, block, entity, sc_sign, sc_no_pic_adjust,
1028 arch_set_irn_register(res, &ia32_registers[REG_GP_NOREG]);
1032 static int is_am_one(const ir_node *node)
1034 int offset = get_ia32_am_offs_int(node);
1035 ir_entity *entity = get_ia32_am_sc(node);
1037 return offset == 1 && entity == NULL;
1040 static int is_am_minus_one(const ir_node *node)
1042 int offset = get_ia32_am_offs_int(node);
1043 ir_entity *entity = get_ia32_am_sc(node);
1045 return offset == -1 && entity == NULL;
1049 * Transforms a LEA into an Add or SHL if possible.
1051 static void peephole_ia32_Lea(ir_node *node)
1056 const arch_register_t *base_reg;
1057 const arch_register_t *index_reg;
1058 const arch_register_t *out_reg;
1069 assert(is_ia32_Lea(node));
1071 /* we can only do this if it is allowed to clobber the flags */
1072 if (be_peephole_get_value(REG_EFLAGS) != NULL)
1075 base = get_irn_n(node, n_ia32_Lea_base);
1076 index = get_irn_n(node, n_ia32_Lea_index);
1078 if (is_noreg(base)) {
1082 base_reg = arch_get_irn_register(base);
1084 if (is_noreg(index)) {
1088 index_reg = arch_get_irn_register(index);
1091 if (base == NULL && index == NULL) {
1092 /* we shouldn't construct these in the first place... */
1093 #ifdef DEBUG_libfirm
1094 ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
1099 out_reg = arch_get_irn_register(node);
1100 scale = get_ia32_am_scale(node);
1101 assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
1102 /* check if we have immediates values (frame entities should already be
1103 * expressed in the offsets) */
1104 if (get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
1110 /* we can transform leas where the out register is the same as either the
1111 * base or index register back to an Add or Shl */
1112 if (out_reg == base_reg) {
1113 if (index == NULL) {
1114 #ifdef DEBUG_libfirm
1115 if (!has_immediates) {
1116 ir_fprintf(stderr, "Optimisation warning: found lea which is "
1121 goto make_add_immediate;
1123 if (scale == 0 && !has_immediates) {
1128 /* can't create an add */
1130 } else if (out_reg == index_reg) {
1132 if (has_immediates && scale == 0) {
1134 goto make_add_immediate;
1135 } else if (!has_immediates && scale > 0) {
1137 op2 = ia32_immediate_from_long(scale);
1139 } else if (!has_immediates) {
1140 #ifdef DEBUG_libfirm
1141 ir_fprintf(stderr, "Optimisation warning: found lea which is "
1145 } else if (scale == 0 && !has_immediates) {
1150 /* can't create an add */
1153 /* can't create an add */
1158 if (ia32_cg_config.use_incdec) {
1159 if (is_am_one(node)) {
1160 dbgi = get_irn_dbg_info(node);
1161 block = get_nodes_block(node);
1162 res = new_bd_ia32_Inc(dbgi, block, op1);
1163 arch_set_irn_register(res, out_reg);
1166 if (is_am_minus_one(node)) {
1167 dbgi = get_irn_dbg_info(node);
1168 block = get_nodes_block(node);
1169 res = new_bd_ia32_Dec(dbgi, block, op1);
1170 arch_set_irn_register(res, out_reg);
1174 op2 = create_immediate_from_am(node);
1177 dbgi = get_irn_dbg_info(node);
1178 block = get_nodes_block(node);
1179 irg = get_irn_irg(node);
1180 noreg = ia32_new_NoReg_gp(irg);
1181 nomem = get_irg_no_mem(irg);
1182 res = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, op1, op2);
1183 arch_set_irn_register(res, out_reg);
1184 set_ia32_commutative(res);
1188 dbgi = get_irn_dbg_info(node);
1189 block = get_nodes_block(node);
1190 irg = get_irn_irg(node);
1191 noreg = ia32_new_NoReg_gp(irg);
1192 nomem = get_irg_no_mem(irg);
1193 res = new_bd_ia32_Shl(dbgi, block, op1, op2);
1194 arch_set_irn_register(res, out_reg);
1198 SET_IA32_ORIG_NODE(res, node);
1200 /* add new ADD/SHL to schedule */
1201 DBG_OPT_LEA2ADD(node, res);
1203 /* exchange the Add and the LEA */
1204 sched_add_before(node, res);
1205 copy_mark(node, res);
1206 be_peephole_exchange(node, res);
1210 * Split a Imul mem, imm into a Load mem and Imul reg, imm if possible.
1212 static void peephole_ia32_Imul_split(ir_node *imul)
1214 const ir_node *right = get_irn_n(imul, n_ia32_IMul_right);
1215 const arch_register_t *reg;
1218 if (!is_ia32_Immediate(right) || get_ia32_op_type(imul) != ia32_AddrModeS) {
1219 /* no memory, imm form ignore */
1222 /* we need a free register */
1223 reg = get_free_gp_reg(get_irn_irg(imul));
1227 /* fine, we can rebuild it */
1228 res = ia32_turn_back_am(imul);
1229 arch_set_irn_register(res, reg);
1233 * Replace xorps r,r and xorpd r,r by pxor r,r
1235 static void peephole_ia32_xZero(ir_node *xorn)
1237 set_irn_op(xorn, op_ia32_xPzero);
1241 * Replace 16bit sign extension from ax to eax by shorter cwtl
1243 static void peephole_ia32_Conv_I2I(ir_node *node)
1245 const arch_register_t *eax = &ia32_registers[REG_EAX];
1246 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1247 ir_node *val = get_irn_n(node, n_ia32_Conv_I2I_val);
1252 if (get_mode_size_bits(smaller_mode) != 16 ||
1253 !mode_is_signed(smaller_mode) ||
1254 eax != arch_get_irn_register(val) ||
1255 eax != arch_get_irn_register_out(node, pn_ia32_Conv_I2I_res))
1258 dbgi = get_irn_dbg_info(node);
1259 block = get_nodes_block(node);
1260 cwtl = new_bd_ia32_Cwtl(dbgi, block, val);
1261 arch_set_irn_register(cwtl, eax);
1262 sched_add_before(node, cwtl);
1263 be_peephole_exchange(node, cwtl);
1267 * Register a peephole optimisation function.
1269 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func)
1271 assert(op->ops.generic == NULL);
1272 op->ops.generic = (op_func)func;
1275 /* Perform peephole-optimizations. */
1276 void ia32_peephole_optimization(ir_graph *irg)
1278 /* register peephole optimisations */
1279 clear_irp_opcodes_generic_func();
1280 register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
1281 register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
1282 register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
1283 register_peephole_optimisation(op_ia32_Cmp, peephole_ia32_Cmp);
1284 register_peephole_optimisation(op_ia32_Cmp8Bit, peephole_ia32_Cmp);
1285 register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
1286 register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test);
1287 register_peephole_optimisation(op_be_Return, peephole_ia32_Return);
1288 if (! ia32_cg_config.use_imul_mem_imm32)
1289 register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split);
1290 if (ia32_cg_config.use_pxor)
1291 register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero);
1292 if (ia32_cg_config.use_short_sex_eax)
1293 register_peephole_optimisation(op_ia32_Conv_I2I, peephole_ia32_Conv_I2I);
1295 be_peephole_opt(irg);
1299 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
1300 * all its Projs are removed as well.
1301 * @param irn The irn to be removed from schedule
1303 static inline void try_kill(ir_node *node)
1305 if (get_irn_mode(node) == mode_T) {
1306 const ir_edge_t *edge, *next;
1307 foreach_out_edge_safe(node, edge, next) {
1308 ir_node *proj = get_edge_src_irn(edge);
1313 if (get_irn_n_edges(node) != 0)
1316 if (sched_is_scheduled(node)) {
1323 static void optimize_conv_store(ir_node *node)
1328 ir_mode *store_mode;
1330 if (!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
1333 assert((int)n_ia32_Store_val == (int)n_ia32_Store8Bit_val);
1334 pred_proj = get_irn_n(node, n_ia32_Store_val);
1335 if (is_Proj(pred_proj)) {
1336 pred = get_Proj_pred(pred_proj);
1340 if (!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1342 if (get_ia32_op_type(pred) != ia32_Normal)
1345 /* the store only stores the lower bits, so we only need the conv
1346 * it it shrinks the mode */
1347 conv_mode = get_ia32_ls_mode(pred);
1348 store_mode = get_ia32_ls_mode(node);
1349 if (get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
1352 set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val));
1353 if (get_irn_n_edges(pred_proj) == 0) {
1354 kill_node(pred_proj);
1355 if (pred != pred_proj)
1360 static void optimize_load_conv(ir_node *node)
1362 ir_node *pred, *predpred;
1366 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1369 assert((int)n_ia32_Conv_I2I_val == (int)n_ia32_Conv_I2I8Bit_val);
1370 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
1374 predpred = get_Proj_pred(pred);
1375 if (!is_ia32_Load(predpred))
1378 /* the load is sign extending the upper bits, so we only need the conv
1379 * if it shrinks the mode */
1380 load_mode = get_ia32_ls_mode(predpred);
1381 conv_mode = get_ia32_ls_mode(node);
1382 if (get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
1385 if (get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
1386 /* change the load if it has only 1 user */
1387 if (get_irn_n_edges(pred) == 1) {
1389 if (get_mode_sign(conv_mode)) {
1390 newmode = find_signed_mode(load_mode);
1392 newmode = find_unsigned_mode(load_mode);
1394 assert(newmode != NULL);
1395 set_ia32_ls_mode(predpred, newmode);
1397 /* otherwise we have to keep the conv */
1403 exchange(node, pred);
1406 static void optimize_conv_conv(ir_node *node)
1408 ir_node *pred_proj, *pred, *result_conv;
1409 ir_mode *pred_mode, *conv_mode;
1413 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1416 assert((int)n_ia32_Conv_I2I_val == (int)n_ia32_Conv_I2I8Bit_val);
1417 pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
1418 if (is_Proj(pred_proj))
1419 pred = get_Proj_pred(pred_proj);
1423 if (!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1426 /* we know that after a conv, the upper bits are sign extended
1427 * so we only need the 2nd conv if it shrinks the mode */
1428 conv_mode = get_ia32_ls_mode(node);
1429 conv_mode_bits = get_mode_size_bits(conv_mode);
1430 pred_mode = get_ia32_ls_mode(pred);
1431 pred_mode_bits = get_mode_size_bits(pred_mode);
1433 if (conv_mode_bits == pred_mode_bits
1434 && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1435 result_conv = pred_proj;
1436 } else if (conv_mode_bits <= pred_mode_bits) {
1437 /* if 2nd conv is smaller then first conv, then we can always take the
1439 if (get_irn_n_edges(pred_proj) == 1) {
1440 result_conv = pred_proj;
1441 set_ia32_ls_mode(pred, conv_mode);
1443 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1444 if (get_mode_size_bits(conv_mode) == 8) {
1445 const arch_register_req_t **reqs = arch_get_irn_register_reqs_in(node);
1446 set_irn_op(pred, op_ia32_Conv_I2I8Bit);
1447 arch_set_irn_register_reqs_in(pred, reqs);
1450 /* we don't want to end up with 2 loads, so we better do nothing */
1451 if (get_irn_mode(pred) == mode_T) {
1455 result_conv = exact_copy(pred);
1456 set_ia32_ls_mode(result_conv, conv_mode);
1458 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1459 if (get_mode_size_bits(conv_mode) == 8) {
1460 const arch_register_req_t **reqs = arch_get_irn_register_reqs_in(node);
1461 set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
1462 arch_set_irn_register_reqs_in(result_conv, reqs);
1466 /* if both convs have the same sign, then we can take the smaller one */
1467 if (get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1468 result_conv = pred_proj;
1470 /* no optimisation possible if smaller conv is sign-extend */
1471 if (mode_is_signed(pred_mode)) {
1474 /* we can take the smaller conv if it is unsigned */
1475 result_conv = pred_proj;
1479 /* Some user (like Phis) won't be happy if we change the mode. */
1480 set_irn_mode(result_conv, get_irn_mode(node));
1483 exchange(node, result_conv);
1485 if (get_irn_n_edges(pred_proj) == 0) {
1486 kill_node(pred_proj);
1487 if (pred != pred_proj)
1490 optimize_conv_conv(result_conv);
1493 static void optimize_node(ir_node *node, void *env)
1497 optimize_load_conv(node);
1498 optimize_conv_store(node);
1499 optimize_conv_conv(node);
1503 * Performs conv and address mode optimization.
1505 void ia32_optimize_graph(ir_graph *irg)
1507 irg_walk_blkwise_graph(irg, NULL, optimize_node, NULL);
1510 void ia32_init_optimize(void)
1512 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");